JPH11110227A - Device and method for information processing and storage medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a supporting tool for improving development efficiency of a program. SOLUTION: A jump/call type command that has a possibility not to sequentially change a program counter contained in an application program is retrieved (S75). Then, with regard to the retrieved jump/call type command, when a user specifies whether it is branched or not or how many times a loop jump should be performed, a simulation is executed according to that specification (S86), monitoring results of monitoring sequence of execution of the application program or a change in address of a memory are displayed (S87).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, an information processing method, and a recording medium, and more particularly to an information processing apparatus and an information processing method suitable for use in, for example, development of an application program of a DSP (Digital Signal Processor). The present invention relates to a method and a recording medium.

[0002]

2. Description of the Related Art Recent electronic devices include a DSP and a CPU (CeC).
ntral Processing Unit) and the like, and its DSP and CPU execute a predetermined application program so that various advanced processes can be performed.

[0003]

With the recent advance and development of technology, high-speed and high-performance DSPs and CPUs have been developed and realized.
In addition to hardware such as a CPU and a CPU, application programs (software) to be executed by them are realized only when they are provided.

[0004] Therefore, it is essential to develop an application program capable of sufficiently exhibiting the functions of hardware, and there is a demand for a support tool for efficient development of the application program.

[0005] The present invention has been made in view of such a situation, and aims to efficiently develop a program.

[0006]

An information processing apparatus according to claim 1, wherein a search means for searching a processor program, which is a program to be executed by a processor, for instructions that may change the execution order,
Specifying means for specifying whether to change the execution order of the processor program according to the instruction searched by the searching means, and executing means for virtually executing the processor program based on the specification performed by the specifying means And display means for displaying the execution order of the processor program by the execution means.

According to a fourth aspect of the present invention, in the information processing method, an instruction which may change the execution order is searched from a processor program which is a program to be executed by a processor, and the execution order of the processor program is changed by the instruction. When designation of whether or not to change is performed, the processor program is virtually executed based on the designation, and the execution order is displayed.

According to a fifth aspect of the present invention, there is provided a recording medium which retrieves, from a processor program which is a program to be executed by a processor, instructions having a possibility of changing the execution order.
A computer for causing a computer to virtually execute a processor program based on the designation when the execution order of the processor program is to be changed and to display the execution order based on the designation. The program is recorded.

[0009] In the information processing apparatus according to the first aspect, the search means is configured to search a processor program, which is a program executed by the processor, for an instruction that may change the execution order. The designation means designates whether or not to change the execution order of the processor program according to the instruction retrieved by the retrieval means. The execution means virtually executes the processor program based on the designation made by the designation means, and the display means displays the execution order of the processor program by the execution means.

In the information processing method according to the fourth aspect, an instruction which may change the execution order is searched from a processor program which is a program to be executed by the processor, and the execution order of the processor program is determined by the instruction. Is specified, the processor program is virtually executed based on the specification, and the execution order is displayed.

According to a fifth aspect of the present invention, in the recording medium, an instruction that may change the execution order is searched for from a processor program that is a program to be executed by the processor, and the execution order of the processor program is determined by the instruction. A computer program for causing a computer to virtually execute a processor program based on the designation when the designation is made or not and to display the execution order is recorded. .

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below, but before that, the correspondence between each means of the invention described in the claims and the following embodiments will be clarified. For this reason, the features of the present invention are described as follows by adding the corresponding embodiment (however, an example) in parentheses after each means.

That is, the information processing apparatus according to claim 1 is
An information processing apparatus that performs virtually the same processing as a predetermined processor, and searches for a processor program that is a program to be executed by the processor for instructions that may change the execution order. Processing step S7 of the program shown in FIG.
5) and designation means for designating whether to change the execution order of the processor program according to the instructions retrieved by the retrieval means (for example,
An execution unit (for example, processing step S86 of the program shown in FIG. 22) for virtually executing the processor program based on the designation made by the designation unit; Display means for displaying the execution order of the processor program by (for example,
And the like (third screen shown in FIG. 19).

Of course, this description does not mean that each means is limited to those described above.

FIG. 1 shows a program development support system to which the present invention is applied (a system refers to a system in which a plurality of devices are logically aggregated, and it does not matter whether the devices of each configuration are in the same housing or not. 2) shows a configuration example of an embodiment.

This program development support system is, for example, a program development support tool for efficiently developing a DSP application program (processor program), and is configured on a computer basis.

That is, the program development system is roughly composed of the computer 1 and the DSP board 21. Then, the computer 1 reads the ROM (Read O
nlyMemory) 2, CPU 3, RAM (Random Access Mem)
ory) 4, input control unit 5, display control unit 8, hard disk control unit 10, CD (Compact Disc) control unit 12, printer control unit 14, and communication I / F (Interface) 15.
Are connected to each other via a bus 16. Further, the computer 1 has a hard disk (H
D) 11 is built in and connected to the hard disk control unit 10.

The ROM 2 stores an IPL (Initial Program Lo
ading) (IPL program). The CPU 3 is, for example, a 166 MHz Pentium processor (Pentium 166 MHz) (trademark).
By executing the IPL program stored in the M2, the OS (Op
Each block is controlled by reading an erating system (program) via the hard disk control unit 10 and developing and executing the program in the RAM 4.
Further, under control of the OS, the CPU 3 stores an application program (computer program) (hereinafter, appropriately referred to as a development support program) for supporting development of a DSP application program stored in the hard disk 11 into a hard disk control unit. 10 and read out through the RAM 4 and executed,
Various processes for developing a DSP application program, which will be described later, are also performed.

As described above, the RAM 5 stores an OS and a development support program, as well as data (including programs) necessary for the operation of the CPU 3 as appropriate.

Here, a mouse 6 and a keyboard 7 are connected to the input control unit 5, and the input control unit 5 is configured to output operation signals corresponding to these operations to the bus 16. I have. The mouse 6 is operated, for example, when indicating a predetermined position on the display 9. The keyboard 7 is operated, for example, when inputting (a source code of) a DSP application program on a predetermined command or data, or an edit screen (FIG. 4) described later.

A display 9 is connected to the display controller 8, and the display controller 8 controls the display on the display 9 under the control of the CPU 3. The display 9 displays various kinds of information (screen) under the control of the display control unit 8.

As described above, the hard disk control unit 10 is connected to the hard disk 11, and the hard disk control unit 10 controls reading from and writing to the hard disk 11. The hard disk 11 has, for example, Windows 95
OS (trademark) and a development support program are stored (recorded). Further, the hard disk 11
Data necessary for the operation of the CPU 3 is also stored. In the present embodiment, for example, the development support program is basically described in Basic language, but only the part related to I / O is described.
It is described in C language.

The CD control unit 12 has a CD-ROM (Compac
t Disc-Read Only Memory 13 is detachable, and controls reading of data from the CD-ROM 13 set therein. CD-
In the ROM 13, for example, a development support program is recorded. That is, the development support program recorded on the CD-ROM 13 is installed in the hard disk 11 described above.

As shown by a dotted line in FIG. 1, a printer 17 is normally connected to the printer control unit 14 via a printer cable conforming to, for example, Centronics. As shown, the DSP board 21 is connected via a printer cable. The printer control unit 14 controls serial communication with the printer 17 and the DSP board 21 connected thereto. The printer 17 performs printing in accordance with data from the printer control unit 14.

The communication I / F 15 has a built-in modem, for example, and controls communication with the Internet and other communication networks. Here, in the above-described case, the development support program stored in the hard disk 11 is assumed to be installed from the CD-ROM 13. However, for example, the development support program is stored in the hard disk 11 by the communication I / O. F1
It is also possible to download the program from the Internet or the like via the Internet 5 and store it (the recording medium in this specification includes a hard disk 11 and a CD).
-In addition to the ROM 13, the magneto-optical disk, etc., the Internet, satellite lines, terrestrial waves, CATV (Cable Te
levision) transmission media such as networks).

The DSP board 21 includes a DSP (FIG. 2) for executing an application program for supporting development by the development support program, and a CPU (not shown) for controlling serial communication with the printer control unit 14. It is installed. Here, the computer 1 and the DSP
Although serial communication is performed with the board 21, parallel communication may be performed (parallel communication is preferable in terms of data transfer time, and circuit scale required for communication is reduced). From the serial communication is preferred).

In the program development support system configured as described above, the hard disk 1
1 is executed under the control of the OS stored in the hard disk 11 to execute various programs for efficiently developing the DSP application programs mounted on the DSP board 21. Is performed.

That is, for example, a main screen (edit screen) (FIG. 4) for efficiently editing (source code of) a DSP application program is as follows.
It is displayed on the display 9 (edit function). Further, for example, the CPU 3 assembles the source code of the application program input to the edit screen and converts it into executable code (machine code) executable by the DSP mounted on the DSP board 21 (assembly function). . Further, for example, the execution code is transmitted to the DSP board 2 via the printer control unit 14.
1 (a data transfer function). Further, the CPU 3 simulates the application program edited on the edit screen (virtually the same processing as when the application program is executed on the DSP mounted on the DSP board 21). The execution order of the application programs (the address indicated by the program counter) is displayed on the display 9 (address monitor function).

Next, FIG. 2 shows a schematic configuration example of a DSP mounted on the DSP board 21 of FIG.

The control unit 22 has a built-in timing generator, instruction decoder, program counter and the like (not shown), and controls the instruction address generator 23, the address generators 25 to 28, and other blocks. That is, the control unit 22 controls the instruction address generator 23 based on the count value of the program counter in synchronization with the clock output from the timing generator. The instruction address generator 23 outputs an address according to the control of the control unit 22 to the instruction ROM / RAM 24, whereby the instruction ROM / RAM 2
4, the instruction address generator 23
The one-word execution code stored at the address from
Read out in synchronization with the clock.

Here, the instruction ROM / RA
M24 has a readable / writable area (RAM area) and a readable only area (ROM area). R
In the AM area, for example, an execution code of an application program supplied from the printer control unit 14 of the computer 1 is stored. That is, the RAM area stores, for example, an application program for demonstration, an application program for verification, and the like. On the other hand, in the ROM area, for example, a commercialized application program that has been verified is written.

The execution code read from the instruction ROM / RAM 24 is supplied to the control unit 22.
The control unit 22 decodes the execution code by an instruction decoder, and controls the address generators 25 to 28 and other blocks based on the decoding result.

The control unit 22 is supplied with data from the jump set register 51 and the main bus 54, and the control unit 22 performs various operations on the basis of these data as necessary. Blocks have been made to control. In this embodiment, one word is
For example, it is 32 bits.

The address generators 25 to 28 generate an address under the control of the control unit 22, and
Output to M29 to M32 respectively.

The RAM 29 is mainly for storing filter coefficients (hereinafter referred to as data K as appropriate) when the DSP functions as a digital filter, and is called a KRAM. The KRAM 29 reads data K stored at an address from the address generator 25 and outputs the data K to the K register 36 or the main bus 54. Also, the KRAM 29
The data K output on the main bus 54 is stored in the address from the address generator 25.

The RAM 30 is mainly used as a so-called work when various operations are performed by the DSP. The data stored in the RAM 30 is called data D, and the RAM 30 is called DRAM because it stores the data D. The DRAM 30 reads data D stored at an address from the address generator 26 and outputs the data D to the D register 37 or the main bus 54. Also, the DRAM 30 stores the address from the address generator 26 on the main bus 5
4 is also stored.

The RAM 31 or 32 mainly stores the DS
When P functions as a digital filter, it is used as a work when the first or second operation for that is performed. The data stored in the RAM 31 or 32 is called data Df or Ds, respectively. Since the RAM 31 or 32 stores the data Df or Ds, the data DfR or Ds is stored in the RAM 31 or 32, respectively.
It is called AM or DsRAM. DfRAM31,
The data Df stored at the address from the address generator 27 is read and output to the R1 register 33 or the main bus 54. Also, DfR
The AM 31 also stores the data Df output on the main bus 54 at the address from the address generator 27. Similarly, the DsRAM 32 also
The data Ds stored at the address from the address generator 28 is read and output to the R2 register 34 or the main bus 54.
The data Ds output on the main bus 54 is stored at the address from. Note that DfRA
F or s in M31 or DsRAM 32 is an abbreviation of first or second, respectively, and as described above,
The DfRAM 31 or the DsRAM 32 mainly stores the D
It is used when the first or second operation for making the SP function as a digital filter is performed.

The R1 register 33 latches the data Df from the DfRAM 31 and outputs it to the adder 35. R2
The register 34 latches the data Ds from the DsRAM 32 and outputs the data Ds to the adder 35. The adder 35 adds the latch output of the R1 register 33 and the latch output of the R2 register 34, and outputs the added value to the main bus 54.

The K register 36 latches the data K from the KRAM 29 or the data on the main bus 54 and outputs it to the multiplier 38. The D register 37 stores the DRAM 30
, Or the data on the main bus 54 is latched and output to the multiplier 38. The multiplier 38 multiplies the latch output of the K register 36 by the latch output of the D register 37, and outputs the multiplied value. The shifter 39 performs a bit shift on the multiplied value output from the multiplier 38 and outputs the result. The P register 40 includes a multiplier 38
Are latched via the shifter 39 and output to the adder 41.

The adder 41 adds the latch output of the P register 40 and the output of the accumulator 44, and outputs the added value to the limiter 42, the B (Buffer) register 43, or the accumulator 44. Limiter 42
Restricts the number of bits of the addition value from the adder 41 and outputs the result to the accumulator 45 or the main bus 54.
The B register 43 temporarily holds the added value from the adder 41 and outputs it to the accumulator 44. The accumulator 44 holds the added value from the adder 41, or
The latch output of the register 43 is subjected to a predetermined operation such as addition to a value held by the register 43 as needed, newly held, and output to the adder 41.

The accumulator 45 includes a limiter 42,
The output of the AND / OR gate 47, the sequencer 48, or the barrel shifter 49 is subjected to a predetermined operation such as addition of a value held by itself, if necessary, and newly held, and the AND / OR gate is newly stored. 47 and the barrel shifter 49. A B (Buffer) register 46 latches the data output on the main bus 54 and performs an AND / O operation.
R gate 47, sequencer 48, and barrel shifter 4
9 is output.

The AND / OR gate 47 calculates the logical product or the logical sum of the outputs of the accumulator 45 and the B register 46, and outputs the result to the accumulator 45 or the limiter 50. The sequencer 48 uses the latch output of the B register 46 as an initial value,
mum-length-shift-register-sequence) and outputs it to the accumulator 45 or the limiter 50. That is, the DSP shown in FIG. 2 is, for example, for audio (for audio processing). For example, in order to output, for example, white noise, the sequencer 48 generates an M sequence. The barrel shifter 49 bit-shifts the output of the accumulator 45 or the B register 46 and outputs the result to the accumulator 45 or the limiter 50. The limiter 50 includes an AND / OR gate 47, a sequencer 48,
Alternatively, the number of bits of the output of the barrel shifter 49 is limited and output to the main bus 54.

The jump set register 51 stores the data output on the main bus 54. That is, the jump set register 51 is one of the blocks specified by a Y register described later, and stores, for example, a bit j4 described later. The AD register 52 latches external data and outputs the data to the main bus 54.
The AD register 52 is one of the blocks specified by an X register described later.

The setup register 53 here is
For example, it comprises four registers A to D (not shown) and holds information on the internal state of the DSP.

In the DSP configured as described above, processes corresponding to a plurality of instructions are performed in parallel. That is, in one clock, data multiplication, addition, transfer, address designation, data reading,
A plurality of processes such as writing, unconditional or changing the program counter corresponding to a predetermined condition (unconditional or conditional branching), and others can be simultaneously performed.

Next, FIG. 3 shows a format of a DSP execution code (machine code) stored in the instruction ROM / RAM 24 of FIG.

As described above, the execution code is composed of 32 bits as one word, and as shown in FIG. 3, one word LSB (Least Significant Bit).
Is the 0th bit, the second bit from the LSB is the first bit, and so on.
If t) is the 31st bit, the 18th bit from the 0th to the 17th bit is called a lower code.

The 0th to 17th bits include, for example, an address of the RAM 29 to 32 in which data to be processed (for example, a target of multiplication or addition) is stored, and a flag indicating a method of designating the address. Is arranged. Here, there are two types of address specification methods: absolute specification and relative specification. In the absolute specification, the address at which the data to be processed is stored is specified. In the relative specification, the offset value of the address at which the data to be processed is stored with respect to the address currently output by the address generators 25 to 28. Is specified.

In the 0th to 17th bits, for example, information designating an X register or a Y register is also arranged. Here, the X register is a virtual register and refers to any of the blocks that output data on the main bus 54. That is, in the embodiment of FIG.
As a block for outputting data, for example, a RAM
29 to 32, adder 35, limiters 42, 50, AD
Although there is a register 52 or the like, the X register indicates any of these. Specifically, a unique number is assigned to a block that outputs data to the main bus 54, and a block serving as an X register is designated by that number. The Y register is also a virtual register and indicates one of the blocks that receives data on the main bus 54. That is, in the embodiment of FIG. 2, for example, a block for receiving data on the main bus 54 includes, for example,
RAMs 29 to 32, R1 register 33, R2 register 34, K register 35, D register 36, B register 4
6, the jump set register 51, etc., and the Y register indicates any of these. In particular,
A unique number is also assigned to a block that receives data on the main bus 54, and a block to be a Y register is designated by that number.

Further, the 0th to 17th bits include a jump instruction or a subroutine call instruction which is an instruction which may change the execution order of the application program (an instruction which may not change the program counter sequentially). , A return instruction for instructing the end of a subroutine, a loop start instruction for instructing the start of loop processing, a loop jump instruction for instructing a jump to return to the first processing of loop processing, and other similar instructions (such instructions Preliminarily defined instructions (collectively, hereinafter, referred to as jump / call instructions) are also arranged (hereinafter, such instructions are collectively referred to as special jump / call instructions, as appropriate).

In the 0th to 17th bits, an instruction instructing a process related to multiplication (such an instruction is collectively referred to as a multiplication instruction as appropriate hereinafter), and an instruction instructing a process related to data transfer (hereinafter referred to as a multiplication instruction). Collectively, such instructions
In the following, transfer instructions are appropriately arranged).

As described above, the 0th to 17th bits, that is, the lower code, basically include information related to multiplication instructions, transfer instructions, and special jump / call instructions (objects to be multiplied or transferred). (Including an address at which such data is stored).

The eighteenth and nineteenth bits include, for example, three instructions of a jump / call type instruction, such as a return instruction, a loop start instruction, and a loop jump instruction (these instructions will be collectively referred to as , Return-related instructions).

In the 20th bit, a read / write instruction for the B register 43 is arranged. For example, when the 20th bit indicates read, the latch output of the B register 43 is read, supplied to the accumulator 44, and stored. Further, the value stored in the accumulator 44 is supplied to the adder 41. When the twentieth bit indicates a write, the output of the adder 41 is written to the B register 43.

The adders 41 are added to the 21st to 24th bits.
(Hereinafter, such instructions will be referred to as addition instructions as appropriate).

T is placed in the 25th to 30th bits. That is, here, among combinations of instructions such as a multiplication instruction, a transfer instruction, and a special jump / call instruction corresponding to a plurality of processes that can be performed simultaneously (in parallel) in the DSP of FIG. Sixty-four combinations that are expected to be used frequently are defined, and each combination is given a unique number. The twenty-first to twenty-fourth bits are 6-bits assigned to a combination of a multiplication instruction, a transfer instruction, and a special jump / call instruction corresponding to a plurality of processes simultaneously performed according to the one-word execution code. A number (hereinafter, appropriately referred to as a combination number) T is arranged. Therefore, T is a multiplication instruction, a transfer instruction, a special jump /
It is uniquely determined according to the combination of the call instructions. Here, T takes, for example, any one of 64 values from 00H to 3FH (H indicates that the preceding digit is a hexadecimal number).

In the 31st bit, the sign of the data latched by P register 40 is arranged.

Here, in the DSP of FIG. 2, instructions executable by one clock are expanded to a large number that cannot be represented by 32 bits. That is, in the present embodiment, for example, as a special jump / call type instruction, 3
Two instructions (instructions) are prepared, and therefore, 5 (= log ₂ 32) bits are required to specify the 32 instructions. further,
In the present embodiment, when a special jump / call type instruction is arranged in a lower code, data to be arranged in the 0th to 15th bits has already been allocated. Therefore, when the special jump / call type instruction is arranged in the lower code, only the 16th and 17th bits are vacant in the lower code. Therefore, for the special jump / call type instruction, the lower code is originally extended to the 18th and 19th bits in which the return type instruction is arranged, and 2 bits of the 0th to 19th bits are used.
The 0 bit is set as a lower code.

However, since the data to be allocated to the 0th to 15th bits in the lower code has already been allocated, an empty portion of the lower code composed of 20 bits from the 0th to 19th bits has been allocated. There are only 4 bits of the 16th to 19th bits,
To place a special jump / call type instruction represented by 5 bits, 1 bit is insufficient.

Therefore, each bit of the special jump / call type instruction represented by 5 bits is converted from its MSB into
In this embodiment, when sequentially expressed as j4, j3, j2, j1, and j0, bits j0 to j3 are respectively arranged in the 16th to 19th bits of the execution code, and the bit j
4 is arranged in the jump set register 51. Therefore, the control unit 22 decodes the execution code including the special jump / call type instruction by referring to the stored value of the jump set register 51 in addition to the execution code.

Hereafter, when the lower code is referred to, the 0th to 17th bits of the execution code of the execution code which does not include the special jump / call instruction are replaced with the special jump / call instruction unless otherwise specified. , The 0th to 19th bits mean the respective execution codes.

Next, various processes performed in the program development support system of FIG. 1 will be further described.

When the development support program stored in the hard disk 11 is started, a window is opened on the display 9 and a main screen (edit screen) as shown in FIG. 4, for example, is displayed in the window. Is done.

The main screen includes a menu bar 61, an input field 62, a scroll bar 63, a block switching unit 64, a status display unit 65, an execution code display unit 66, and a file display unit 6.
7 and the like, from which all functions necessary for programming of the application program (all functions provided by the development support program in the present embodiment) can be called.

The menu bar 61 is a menu bar, etc.
Button 61A, print button 61B, block button 61C, quit button 61D, guide button 61E, transformer
ns) button 61F, file buttons 61G, K
Edit (K_edit) button 61H, D edit (D_edi)
t) button 61I, Df edit (Df_edit) button 61
J, Ds edit (Ds_edit) button 61K, S edit (S_edit) button 61L, address monitor (Amon
itor) button 61M and help button 61
N.

The etseter button 61A is used to transfer the application program or data displayed in the input field 62 to C
This operation is performed when the etheter menu screen for saving in a language, an assembler (machine language), a format for writing to the ROM (PRM format), or the like is displayed (clicked with the mouse 6).

The print button 61B is operated to display a print menu screen for causing the printer 17 to print the application program or data displayed in the input field 62 in a predetermined format.

The block button 61C is operated to display a block menu screen for copying an application program, data, and other editing work between blocks described later.

The quit button 61D is operated when displaying an end menu screen for ending the development support program.

The guide button 61E is operated to display a guide screen (FIG. 7) described later for supporting the programming of the application program.

The trans button 61F is used to transfer the execution code of the application program and the like to the printer
4, that is, for transmitting data to the DSP board 21 using a part of bits of the printer interface, and for receiving data from the DSP board 21 in the same manner,
It is operated when displaying a transformer screen (FIG. 13) described later.

The file button 61G is used to store the application program input in the input field 62 and the setting environment on the main screen on the hard disk 11, and to read out the information stored on the hard disk 11 in this manner. Operated when displaying the file menu screen.

The K edit button 61H, D edit button 61I, Df edit button 61J, and Ds edit button 61K are used to create and edit data K, D, Df, and Ds to be stored in the RAMs 29 to 32 of the DSP of FIG. It is operated when the data edit screen is displayed.

The S edit button 61L is connected to the DS edit button shown in FIG.
It is operated when a setting screen for setting the stored values of the four A to D plane registers constituting the P setup register 53 is displayed.

The address monitor button 61M is the D button in FIG.
The address output by the SP instruction address generator 23, the address generators 25 to 2
It is operated to display a screen (FIGS. 17 to 19), which will be described later, for monitoring a change in the address output by the address 8.

The help button 61N is operated to display a help menu screen for explaining the development support program.

The input field 62 is for inputting and editing application programs and the like (input screen).
Each line is divided into a plurality of columns for inputting different types of instructions. Here, the input field 62 is filled with predetermined default data when the development support program is started. In addition, the input field 62 is, for example, the 10th of the 000H to 3rd FFH rows.
There are 24 lines, and when the development support program is started, 28 lines from the 000H to the 01BH lines are displayed by default. The number of display lines at the time of starting the development support program can be set to a number other than 28. Also, the lines not currently displayed in the input field 62 can be displayed by scrolling the screen by dragging the scroll bar 63 with the mouse 6 and moving.

The block switching section 64 is operated when switching blocks. That is, display contents in the input field 62, the status display section 65, the execution code display section 66, and the file display section 67 are developed (stored) in a storage area secured in advance in the RAM 4.
Here, this one storage area is called a block. In the present embodiment, for example, the 00th
The 16th block from the Hth to the 0th FH is secured, and when the display part of the number corresponding to the desired block in the block switching unit 64 is clicked with the mouse 6, the display content of the main screen is changed to that. It is adapted to be changed to the one corresponding to the block.

The status display section 65 displays the values stored in the registers A to D in the setup register 53 (DSP).
) Is displayed in hexadecimal.

An execution code is displayed on the execution code display section 66. That is, although the cursor 69 is displayed in the input field 62, the line where the cursor 69 is located is set as the line of interest and the cursor 6 is displayed.
9 is moved by operating the mouse 6 or the keyboard 7, whereby the line of interest moves,
The source code of the application program input to the line of interest, that is, the line where the cursor 69 is located, is line-assembled (assembled for one line), and the resulting as shown in FIG. The 32-bit execution code (machine code) is displayed in the execution code display unit 6
At 6, it is displayed in hexadecimal.

The file name is displayed on the file display section 67 when the application program stored in the hard disk 11 and the setting environment on the main screen are read. Here, in the present embodiment, for example, A24, I24, K24, D24,
Df24, Ds24, S24, B24, etc. are prepared. Extension A2
4 is added to the file when all the contents of the block selected by operating the block switching unit 64 are saved. The extension I24 is added to the file when only instructions (instructions) are saved.
Extensions K24, D24, Df24, and Ds24 are data K, D, Df,
It is added to each file when only Ds is saved. The extension S24 is added to the file when only the stored value of the setup register 53 is saved. Extension B2
4 is the environment of the block selected by operating the block switching unit 64 (for example, the file display unit 6).
7) is added to the file when only the file was saved.

FIG. 5 shows an example of the configuration of the input field 62 on the main screen of FIG.

As described above, in the input column 62, each line is
It is divided into a plurality of fields for inputting different types of instructions.

That is, each line in the input column 62 is, from the top, a line number (NO) column 71, a sign (+) column 72, a multiplication (mpy) column 73, an addition (add) column 74, and a read / write (m).
r) column 75, transfer column (move) 76, jump (jump) column 77, data (k, d, df, ds, x, y) column 78, end (ed)
A column 79 and a comment column 80 are sequentially arranged.

In the line number column 71, line numbers are arranged in series from 000H from the first line to the last line.

In the sign field 72, + or-is input as a sign of the multiplication result when the multiplication result of the multiplier 38 is stored in the P register 40 via the shifter 39. In the present embodiment, + is displayed by default.

The multiplication column 73 receives a multiplication command. In this embodiment, by default, _ * _ (this is
In the multiplier 38, the execution of k * d (meaning that the current contents of the K register 36 and the contents of the D register 37 are multiplied to make the output unchanged) is displayed.

An addition command is input to the addition field 74. In the present embodiment, by default, _ + ___ (this means that zero is added in the adder 41) is displayed.

The read / write command 75 is input to the read / write field 75. In the present embodiment, by default, __ (this means a read mode for reading data from the B register 43) is displayed.

A transfer command is input to the transfer column 76. In this embodiment, by default, _> __ (this is
(Meaning that data transfer is not performed) is displayed.

The jump column 77 is used to input a jump / call command. In the present embodiment, by default,... (This means that no jump is performed) is displayed.

The data column 78 contains data K, D, Df, D
s fields 78K, 78D, 7 for inputting respective addresses
8Df, 78Ds, a field 78X or 78Y for inputting information for designating an X register or a Y register, respectively.
Are sequentially arranged.

[0093] In the end column 79, an end command ed for instructing the end of the application program is input.

The comment field 80 is used to enter a necessary comment. The comment entered in the comment field 80 is mainly for helping the viewer of the application program to understand it, and is ignored during assembly.

As described above, the DSP of FIG. 2 has an architecture in which processing corresponding to a plurality of instructions (instructions) can be performed in parallel (simultaneously) with one clock. In the input column 62, each line is correspondingly divided into a plurality of columns for inputting different types of instructions. That is, in the input field 62, a plurality of instructions corresponding to a plurality of processes that can be performed simultaneously by the DSP can be described in one line. Therefore, (the source code of the application program)
Can be described efficiently.

Next, FIG. 6 shows an example of description of an application program in the input field 62. In FIG. 6, the illustration of the comment column 80 is omitted.

"_ *" In the multiplication column 73 in the 000H line
x ”is the value of X in the data column 78 in the multiplier 38.
This means that the stored value of the register corresponding to AD specified in the register column 78X is stored in the P register without multiplication. Here, the AD specified in the X register column 78X represents, for example, the AD register 52 in FIG. 2 in the present embodiment. Therefore, the stored value of the AD register 52 is the K register or the D register. 37, the signal is input to a multiplier 38, and no processing is performed.
The data is supplied to the register 40 and stored. Also, 000
“+” In the sign column 72 in the H-th row means that the sign of the storage value of the P register 40 is positive, and therefore,
As described above, A stored in the P register 40
The sign bit of the value stored in the D register 52 is set positive.

"M + _0" in the addition column 74 in the 000H line
"0" means that the stored value m of the accumulator 44 is supplied to the adder 41, and the adder 41 adds the stored value m and 0.

Read / write column 75 in line 000H
“Rd” reads the latch output of the B register 43,
This means that the data is supplied to the accumulator 44 and stored.

"X>" in the transfer column 76 in the 000H line
s "indicates that the set value of the X register is Ds
This means that the data is transferred to the sRAM 32 via the main bus 54.

“D31” in the column 78Ds of the data Ds in the data column 78 in the 000H line means that the address output from the address generator 28 to the DsRAM 32 is 31H. here,
“D” in “d31” means the absolute designation of the address. Thereby, by the instruction “x> s” in the transfer field 76,
The set value transferred from the X register is the DsRAM3
2 is stored at address 31H.

"AD" in the column 78X of the X register in the data column 78 on the 000H line means that the AD register 52 is an X register.

“J4 = 0” in the column 78Y of the Y register in the data column 78 in the 000H line means that the bit j4 in the jump set register 51 is set to 0.

In line 000H, the above processing is
Done at the same time.

The code column 72, the addition column 74, and the read / write column 75 in the 001H line indicate the same processing as in the 000H line.

In the multiplication column 73 in the 001H line, “0 *
"0" means that the multiplier 38 calculates 0x0 and supplies the calculation result to the P register 40 via the shifter 39 and stores the result. That is, this causes the P register 40 to be cleared to zero.

“D3d” in the column 78Df of the data Df in the data column 78 in the 001H line means that the address output from the address generator 27 to the DfRAM 31 is 3DH.

"R00" in the data Ds column 78Ds in the data column 78 in the 001H line indicates the address output from the address generator 28 to the DsRAM 32 by incrementing the address currently output by 00H. It means to let. Here, “r” of “r00” means relative designation of an address. Therefore, in this case, the address output from the address generator 28 does not change.

In the line 001H, the above processing is performed.

The code column 72 and the read / write column 75 in the 002H line mean the same processing as in the 000H line.

In the multiplication column 73 of the 002H-th line, “k *
"a" indicates that the multiplier 38 multiplies the data K stored in the KRAM 29 by the addition result a in the adder 35, and supplies the multiplication result to the P register 40 via the shifter 39 for storage. It means to let. That is, the data K is read from the address of the KRAM 29 specified in the data K column 78K in the data column 78 and latched in the K register 36. In the adder 35, the stored value of the R1 register 33 and the stored value of the R2 register 34 are added, and the addition result a is supplied to the D register 37 via the main bus 54 and latched. . Then, the multiplier 38 multiplies the value stored in the K register 36 by the value stored in the D register 37. The R1 register 33 or the R2 register 34
The data Df or Ds stored at the address of the DfRAM 31 or the DsRAM 32 output from the address generator 27 or 28 is latched, respectively, and the adder 35 adds the latched outputs.

"Z + 2" in the addition column 74 in the line 002H
"p" means that the storage value p of the P register 40 is doubled, and 0 (z means 0) is added thereto in the adder 41, and the addition result is stored in the accumulator 44. doing. That is, in this case, the result of the multiplication by the multiplier 38 is stored in the P register 40 via the shifter 39. When the result of the multiplication by the multiplier 38 is shifted through the shifter 39 by one bit to the left. The shift is doubled. The result of doubling the result of the multiplication by the multiplier 38 is supplied to an adder 41 via a P register 40, where it is added to 0 and stored in an accumulator 44.

"R02" in the column 78K of the data K in the data column 78 in the 002H-th row indicates the address output from the address generator 25 to the KRAM 29 by the address which is incremented by 02H from the address currently output. ("R02" in "r02" means relative address designation, as described above).

"51f" in the column 78Df of the data Df in the data column 78 in the 002H-th line is the address which the address generator 27 outputs to the DfRAM 31 as the address which is incremented by 1fH from the address currently output. It means to let. Here, if the third digit of the value in the data column 78 is neither “d” indicating the absolute designation of the address nor “r” indicating the relative designation of the address, the value is represented as:
It is used to specify the relative address. In addition,
The third digit indicates the number of bits of the value that follows. Therefore, “51f” indicates that the address generator 27
This means that the address to be output to M31 is an address that is incremented by 1fH, which is a 5-bit value, from the address currently being output.

"401" in the data Ds column 78Ds in the data column 78 in the 002H-th row is the address which the address generator 28 outputs to the DsRAM 32, which is an address which is incremented by 01H from the address currently output. It means to let. Since the third digit “4” of “401” is neither “d” nor “r”, as described above, the subsequent value “01”
Is a 4-bit value.

In the line 002H, the above processing is performed.

The code column 72 and the read / write column 75 in the 003H line mean the same processing as in the 000H line. The addition column 74 in the 003H-th line indicates the same processing as that in the 001H-th line.

In the multiplication column 73 on line 003H, “k *
"d" is obtained by multiplying the data K stored in the KRAM 29 and the data D stored in the DRAM 30 by the multiplier 38, and outputting the multiplication result via the shifter 39 to P
This means that the data is supplied to the register 40 and stored. That is, the data K is read from the address of the KRAM 29 specified in the data K column 78K in the data column 78 and latched by the K register 36, and at the same time, the data D in the data column 78 is read. The data D is read from the address of the DRAM 30 specified in the column 78D and latched in the D register 37. Then, in the multiplier 38, the value stored in the K register 36 and
The result is multiplied by the value stored in the D register 37, and the multiplication result is supplied to the P register 40 via the shifter 39 and stored. This multiplication is performed with a delay of one clock.

"J13s07a" in the jump column 77 in the 003H-th line indicates that when the 13th bit of the register on the A-side constituting the setup register 53 is 1, the jump is to the 07th Hth line. . In addition,
"13" between "j" and "s" in "j13s07a" is
Means the 13th bit of the register on the A side, and "s"
“07a” after the address means the jump destination address (instruction address) 07aH.

"300" in the data K column 78K or the data D column 78 in the data column 78 on line 003H.
"400" of D is the address generator 25 or 26
Changes the address to be output to the KRAM 29 or the DRAM 30 from the address currently being output by three bits of 0s.
This means that the address is incremented by 0H or 4-bit 00H.

In line 003H, the above processing is performed. However, in the DSP of FIG. 2, when a so-called jump is performed by a jump / call type instruction (when the value of the program counter changes), the jump is performed with a delay of two clocks (see FIG. 2). DSP 2 has such an architecture). That is, for example, in the 003H-th row shown in FIG. 6, the 07th bit performed when the 13th bit of the register on the A-side constituting the setup register 53 is 1
The jump to the H-row is performed at the timing at which the 005th row (not shown) executed two clocks after that is executed.

As described above, in response to the fact that the DSP of FIG. 2 can simultaneously process a plurality of instructions in one clock, each row of the input column 62
To be able to enter multiple such instructions,
Since it is divided into a plurality of columns, a plurality of instructions corresponding to a plurality of processes that can be performed simultaneously by the DSP can be described in one line, and an application program can be described efficiently.

By the way, when an application program is input (described) on the above-mentioned main screen (FIG. 4), for example, a user (programmer) who is not accustomed to programming may input a plurality of instructions of any combination into one.
Sometimes I don't know what can be written on a line.

Therefore, in the development support program, a guide screen for guiding an instruction that can be described in one line (an instruction that can be input in a column where no instruction is input) is prepared.

That is, FIG. 7 shows a guide screen.

As described above, the window of the guide screen is opened by operating (clicking) the guide button 61E (FIG. 4) or by double-clicking an arbitrary position in the input field 62. It has been made.

As shown in FIG. 7, the guide screen includes a guide line section 91, an instruction selection section 92, an enter button 101, an undo (UNDO) button 102,
It comprises a reset button 103, a close button 104 and the like.

The guide target line column 91 is configured in the same manner as each line constituting the input column 62, and displays a guide target line (hereinafter, appropriately referred to as a guide target line). That is, for example, when the guide screen is displayed by clicking the guide button 61E, when the guide button 61E is clicked, the cursor 6
The line in the input column 62 where 9 is located is displayed in the guide target line column 91 as a guide target line. Further, for example, when the guide screen is displayed by double-clicking a predetermined line in the input column 62, the double-clicked line is displayed in the guide target line column 91 as a guide target line. You.

The instruction selection field 92 includes a code selection field 93, a multiplication selection field 94, an addition selection field 95, a read / write selection field 96, a transfer selection field 97, and a jump selection field 9.
8, a data selection column 99, and an end selection column 100. These code selection field 93 and multiplication selection field 9
4, an addition selection field 95, a read / write selection field 96, a transfer selection field 97, a jump selection field 98, a data selection field 99, or an end selection field 100 include a code field 72, a multiplication field 73, and an addition in each row of the main screen. Column 74, read / write column 75, transfer column 76, jump column 77, data column 78,
Alternatively, a group of instructions that can be input is displayed in the end column 79.

Here, the instruction displayed in the instruction selection field 92 can be selected by clicking with the mouse 6. When an instruction is selected, a symbol is displayed in a circle displayed on the left side of the selected instruction, and the selected instruction is displayed in a corresponding column of the guide target line column 91. (Input). The instruction can be deselected by clicking on the instruction again.

[0131] The confirm button 101 is operated when the display of the guide target line column 91 is decided. When the confirm button 101 is operated, the display contents of the guide target line column 91 are also assembled.

The undo button 102 is operated to cancel the operation performed immediately before and return the state of the guide screen to the state before the operation immediately before the operation. The reset button 103 is operated to return the state of the guide screen to an initial state in which nothing has been input. The close button 104 is operated when closing the guide screen (the window in which is displayed).

On the guide screen configured as described above,
As described above, a command displayed in the instruction selection field 92 can be selected and input by clicking with the mouse 6. That is, the application program can be described without operating the keyboard 7. Therefore, according to the guide screen, a comfortable environment (a user interface (GUI (Graph
hical User Interface))).

Further, on the guide screen, when a certain type of instruction is selected in the instruction selection field 92, the other types of instruction group can be described together with the selected instruction in a single line (the DSP shown in FIG. 2). But,
An instruction that can be processed simultaneously with the selected instruction) is recognized so that only such an instruction can be selected. Therefore, the user can easily recognize a command that can be described in one line.

Next, referring to the flowchart of FIG.
Performed in the program development support system of FIG.
The editing process of the application program will be described.

When the development support program is started, first, in step S1, the main screen (edit screen) shown in FIG. 4 is displayed. Then, the process proceeds to step S2, where it is determined whether or not the line in which the cursor 69 is located in the input field 62 has changed. If it is determined in step S2 that the line on which the cursor 69 is located has not changed, the process proceeds to step S3, and FIG.
It is determined whether or not an operation has been performed so as to display the guide screen shown in FIG. If it is determined in step S3 that an operation has not been performed to display the guide screen, step S4 is skipped and step S2 is performed.
Return to If a command is input to the input field 62 while steps S2 and S3 are repeatedly performed, the input command is displayed in the input field 62.

When it is determined in step S3 that an operation has been performed to display a guide screen,
Proceeding to step S4, guide processing is performed, and step S4 is performed.
Return to 2. The details of the guide processing in step S4 will be described later.

On the other hand, in step S2, the cursor 6
If it is determined that the line in which the line 9 is located has changed, that is, if the cursor 6 or the return key of the mouse 6 or the keyboard 7 is operated and the cursor 69 is moved to a different line, the process proceeds to step S5. Then, the assembling process is performed on the original line where the cursor 69 was located. That is, here, when the line on which the cursor 69 is located is moved, the cursor 69 is located before the movement.
Line assembling (line assembling) is performed. The details of the assembling process in step S5 will be described later.

After the assembling process, the process proceeds to step S6, and it is determined whether an error has occurred during the assembling process. If it is determined in step S6 that an error has occurred, the cursor 69 is moved to the original line,
It returns to step S2.

When it is determined in step S6 that no error has occurred, the process proceeds to step S7, where the execution code (machine code) obtained as a result of the assembling process in step S5 is stored in the RAM 4, and the process proceeds to step S8. move on. In step S8, it is determined whether or not an operation has been performed so as to end the editing process. If it is determined in step S8 that no operation has been performed to end the editing process, the process returns to step S2. If it is determined in step S8 that an operation has been performed to end the editing process, the editing process ends (the main screen is closed).

Next, referring to the flowchart of FIG.
The assembling process in step 5 of FIG. 8 will be described.

In the assembling process, first, in step S11, a basic check is performed on one line to be assembled (a line to be assembled). Specifically, for example, a character string described in an assembly target line is searched from left to right to check whether there is a grammatical error (syntax error).

After completion of the basic check, the process proceeds to step S12.
And in the basic check, it is determined whether or not there is an error (here, a syntax error). If it is determined in step S12 that there is an error, the process returns. In this case, in the flowchart of FIG. 8, the process returns from step S6 to step S2. At that time, the cursor 69 is moved to, for example, a position where a syntax error has occurred in the assembling target line. Thus, the user can easily recognize the position where the error has occurred.

On the other hand, if it is determined in step S12 that there is no error, the flow advances to step S13 to check the lower code of the 0th to 17th bits. That is, in step S12, first, the lower code of the line to be assembled is obtained (the lower code is assembled). Then, whether the lower code corresponds to any of the combinations of the 64 instructions represented by the above-described combination numbers T (= 00H to 3FH), that is, in the DSP of FIG. It is checked whether the described instructions can be executed simultaneously.

After checking the lower code, the flow advances to step S14 to determine whether or not an error has occurred as a result of the check. If it is determined in step S14 that an error has occurred, that is, if the lower code of the assembling target line does not correspond to any of the combinations of the 64 instructions represented by the combination number T, the process returns. In this case, in the flowchart of FIG.
The process returns from step S6 to step S2. At this time, the cursor 69 is moved to the original line (the line to be assembled) as described above.

On the other hand, when it is determined in step S14 that no error has occurred, that is, when the lower code of the assembling target line corresponds to any one of the combinations of 64 instructions represented by combination number T , The process proceeds to step S15, and assembling is performed on bits higher than the lower code. That is, in step S15, as described above, the number of bits of the lower code differs depending on whether or not the assembling target line includes the special jump / call system instruction. Are included, and the assembling of bits higher than the lower code is performed depending on the case where they are not included.

Then, the process proceeds to a step S16, where it is determined whether or not an error has occurred in assembling the upper bits. In step S16, when it is determined that an error has occurred, that is, for example, when the combination of the lower code and the assembling result of the higher-order bit is inappropriate (for example, the special jump / call type instruction When the 0th to 19th bits of the execution code are described as lower codes, the return-related instructions arranged in the 18th and 19th bits are also described in the assembling target line. To return. In this case as well, in the flowchart of FIG. 8, the process returns from step S6 to step S2. At this time, as described above, the cursor 69
It is moved to the original line (the line to be assembled).

On the other hand, if it is determined in step S16 that no error has occurred, the flow advances to step S17 to convert the binary execution code as a line assembly result of the line to be assembled into a hexadecimal code.
Proceed to step S18. In step S18, the execution code converted to hexadecimal is displayed on the execution code display section 66 of the main screen (FIG. 4), and the process returns.

As described above, when the cursor 69 moves a line, the line before the movement is assembled. Then, when an assembly error occurs, the cursor 69 is moved to the original line. Therefore, if the application programs are sequentially described on the main screen, a program without logical errors (and its execution code) can be finally obtained. That is, assembling is
Since the movement is performed with the movement of the cursor 69 as a trigger, the user does not need to assemble the program after writing the program. Further, when an assembling error occurs, the movement of the line is restricted, so that the user can immediately correct the line having the program error.

In the above case, the cursor 6
9 assembles the row before the movement when moving the row, but the assembling may be performed on the row after the movement. However, when the present inventor actually assembles the line after the movement, the scroll bar 63 is operated.
When the input field 62 is scrolled, the timing of the scrolling process and the timing of the assembling process are batted, and the assembling may not be performed. Therefore, it is desirable that the assembling process be performed on the line before the movement of the cursor 69.

The above-described assembling process is performed when the cursor 69 has moved a line. Therefore, for example, the scroll bar 63 is operated and the input field 6 is entered.
The assembling process is not performed only by scrolling 2.

Further, in the above case, when an assembling error occurs, the cursor 69 is moved to the original line. In addition to this, the line (the line where the error occurred) is guided. It is also possible to open the guide screen (FIG. 7) as a line (perform the guide processing according to the flowchart of FIG. 10 described below) to prompt the user for an appropriate input.

Next, the guide processing in step S4 in FIG. 8 will be described with reference to the flowchart in FIG.

In the guide processing, first, in step S21, the guide screen shown in FIG. 7 is displayed. In this case, for example, the line where the cursor 59 is located on the main screen is displayed as a guide target line in the guide target line column 91. Then, the process proceeds to step S22, and it is determined whether any of the instructions in the instruction selection field 92 is selected by clicking the mouse 6 or the like. Step S22
If it is determined that any of the instructions in the instruction selection field 92 has been selected,
Proceeding to 23, the selected command is displayed at the corresponding position in the guide target line column 91. Further, in step S23, a mark is displayed in the circle displayed on the left side of the selected command on the guide screen (FIG. 7).

Then, the flow advances to step S24 to perform a narrowing-down process, which will be described later. This limits the selectable commands in the instruction selection field 92, and then returns to step S22.

On the other hand, if it is determined in step S22 that none of the instructions in the instruction selection field 92 has been selected, the flow advances to step S25 to determine whether or not the confirm button 101 has been operated. If it is determined in step S25 that the confirm button 25 has been operated, the process proceeds to step S26, and the assembling process described with reference to FIG. 9 is performed. Then, the assembling result and the display content in the guide target line column 91 are reflected on the main screen, the process proceeds to step S27, the guide screen is closed, and the process returns.

If it is determined in step S25 that the enter button 101 has not been operated, the flow advances to step S28 to determine whether the undo button 102 has been operated. If it is determined in step S28 that the undo button 102 has been operated, the process proceeds to step S29, where undo processing is performed, that is, the state of the guide screen is returned to the state before the immediately preceding operation was performed, and step S22 is performed. Return to

On the other hand, if it is determined in step S28 that the undo button 102 has not been operated, the flow advances to step S30 to determine whether the reset button 103 has been operated. If it is determined in step S30 that the reset button 103 has been operated, the process proceeds to step S31, where a reset process is performed, that is, a state in which nothing has been input on the guide screen (a state in which a default value has been input). And the process returns to step S22.

If it is determined in step S30 that the reset button 103 has not been operated, the flow advances to step S32 to determine whether the close button 104 has been operated. If it is determined in step S32 that the close button 104 has not been operated,
It returns to step S22. If it is determined in step S32 that the close button 104 has been operated, the process proceeds to step S27, where the guide screen is closed, and the process returns.

In the embodiment of FIG. 10, for convenience of explanation, steps S22, S25, S28, S30, S3
In the order of 2, it is determined whether or not various buttons have been operated sequentially, and when the buttons have been operated, processing corresponding to the operation is performed. It is determined in parallel whether or not the operation has been performed. That is, when an event that any one of the buttons is operated occurs, a process (event process) corresponding to the event is performed.

Next, the narrowing-down process in step S24 in FIG. 10 will be described with reference to the flowchart in FIG.

In the narrowing-down process, first, in step S41, an instruction determined to be selected in step S22 of FIG. 10 (hereinafter, appropriately referred to as a selection instruction) is:
It is determined whether the instruction is one of a multiplication instruction, a transfer instruction, and a jump / call instruction. When it is determined in step S41 that the selected instruction is not any of the multiplication instruction, the transfer instruction, and the jump / call instruction, the process skips steps S42 and S43 and proceeds to step S44.

If it is determined in step S41 that the selected instruction is one of a multiplication instruction, a transfer instruction, and a jump / call instruction, the flow advances to step S42 to affect the selected instruction. Commands to be executed are narrowed down. That is, in step S42, out of all the instructions, the DSP of FIG.
With the select instruction, only those that can be executed simultaneously are recognized, which is the result of narrowing down the instructions affected by the select instruction.

Then, the flow advances to step S43 to combine the immediately preceding narrowing result (the instruction that could be selected before the selection instruction was selected) with the narrowing result in step S42, for example, an instruction common to both. Is the result of the narrowing down of the current instruction. Further, in step S42, in the instruction selection field 92, it is made impossible to select an instruction other than the result of narrowing down the current instruction (disabled selection).

Here, the instruction which is made unselectable is, for example, as shown in FIG.
2 (or displayed dimmed (low brightness) compared to selectable instructions) and only selectable instructions are displayed.

Thereafter, the flow advances to step S44 to determine whether the guide target line is the normal type or the special jump / call type.

Here, as described above, in this embodiment, since there is a special jump / call type instruction, in the execution code, the 0th to 17th bits are set to the lower code, The 19th to 19th bits may be a lower code, but the guide target line is a normal system or a special jump / call system when the 0th to 17th bits or the 0th to 19th bits of the execution code are used. Means the lower code.

In step S44, when it is determined that the line to be guided is a special jump / call system,
Proceeding to step S45, it is determined that an instruction that can be selected only when the guide target line is the normal system cannot be selected.
Go to 47. If it is determined that the guide target line is of the normal type, the process proceeds to step S46, where the selectable command is disabled only when the guide target line is of the jump / call type, and the process proceeds to step S47.

On the other hand, if it is determined in step S46 whether the guide target line is the normal system or the special jump / call system, it cannot be determined only by the currently selected instruction. , Step S
Skipping to steps S45 and S46, the process proceeds to step S47, where instructions are narrowed down based on the combination number T.

That is, in step S47, when the instruction is combined with the instruction selected so far, the lower code is selected from among 64 instruction combinations represented by the combination number T (= 00H to 3FH). An instruction that does not correspond to any of them is made unselectable. As a result of the narrowing down in step S47, selectable instructions are narrowed down particularly in the data selection column 99 and the end selection column 100.

Then, the process proceeds to a step S48, where it is determined whether or not there is a single selectable instruction among the selection columns constituting the instruction selection column 92, and when it is determined that there is no selectable instruction, a step S49 is performed. Skip to step S50. If it is determined in step S48 that there is a selection column in which the number of selectable instructions is one, the process proceeds to step S49, where only the selectable instruction is selected in the selection column, and the process proceeds to step S50. . In step S49, the selected command is displayed at a corresponding position in the guide target line column 91.

In step S50, among the selection fields constituting the instruction selection field 92, any command other than the selected command in the selection field to which the selected command belongs is made unselectable, and the flow advances to step S51. In step S51, of the selection fields constituting the instruction selection field 92,
A selection column in which no instruction has been selected is detected, the display of the guide target line column 91 corresponding to that column is set to the default display, and the routine returns.

As described above, according to the narrowing-down process, the commands are narrowed down to selectable ones in each of the selection columns constituting the instruction selection column 92, so that even a novice user has no mistake. Efficient programming becomes possible.

Further, every time an instruction is selected, a narrowing-down process is performed, and the selectable instructions change, so that the user can perform, so to speak, interactive programming.

Furthermore, there are cases where an instruction to be described in a line to be executed later than the line to be guided is executable in the line to be guided. That is, for example, in the case of a row that is now a guide target row, only addition is required, and in a row that is executed later, multiplication is required. In the DSP of FIG. , Can be performed simultaneously with addition. In this case, on the guide screen, only instructions that can be executed simultaneously can be selected in the guide target row, so that multiplication that needs to be performed later may be selectable with addition selected. . Therefore, the user can recognize that the multiplication to be described later can be described now, and by describing the multiplication on the guide target line, it is not necessary to describe the multiplication later. As a result, for example, programming with a small number of rows becomes possible.

It should be noted that all instructions that can be executed by the DSP of FIG. 2 are displayed in the instruction selection field 92 on the guide screen, so that a certain size is required for the display area. On the other hand, the guide screen is preferably displayed together with the main screen in view of ease of programming work. However, depending on the size of the display screen of the display 9, it may be difficult to display the entire main screen together with the guide screen.

Therefore, in the present embodiment, the computer 1 generally has, for example, 800 × 600 dots (horizontal ×
Considering the case of a so-called notebook-type screen in which the screen is configured with a resolution of about (vertical), at least the third line from the top of the input column 62 on the main screen is displayed at least, for example. A guide screen is opened. That is, the guide screen is displayed so as to overlap the fourth and subsequent lines from the top of the input field 62 on the main screen.

However, this is the default setting,
The display position when the guide screen is opened can be arbitrarily set. That is, the etsetra menu screen displayed by clicking the etcetera button 61A on the main screen includes:
There is an item of "cursor fixed position", in which the display position when the guide screen is opened can be set, and thereby, the position of the main screen when the guide screen is opened can be set. The degree of overlap can be changed.
For example, when the computer 1 is of a so-called desktop type, the resolution of the display screen is generally high. Therefore, by reducing the degree of overlap with the main screen when the guide screen is opened. ,
The main screen can be easily viewed.

Since only the combinations of instructions that can be described on one line are input to the line created on the guide screen by the narrowing-down process, the assembling error in the assembling process in step S26 of the guiding process shown in FIG. Basically does not occur.

Next, after the application program is created using the main screen and, if necessary, the guide screen as described above, the application program (executable code) is transferred from the computer 1 to the DSP. The data can be transferred to the board 21 and executed by the DSP (FIG. 2).

When the application program is transferred from the computer 1 to the DSP board 21, the user operates the trans button 61F on the main screen (FIG. 4). In this case, for example, as shown in FIG.
A transformer screen for performing data transfer with the SP board 21 is displayed.

In the transformer screen, the first selection column 111
Data from the computer 1 to the DSP board 21
, Or from the DSP board 21 to the computer 1 is input. That is, the data
When transferring from the computer 1 to the DSP board 21,
Alternatively, when transferring from the DSP board 21 to the computer 1, “Transmit” or “Receive” in the first selection field 111 is selected, respectively.

In the second selection field 112, the type of data to be transferred is input. That is, when transferring all data (including an application program) for a certain block, “one block” is used, when transferring only an application program, “instruction” is used when transferring only data K. Contains the "coefficient"
However, when only the data D is transferred, “data (D)” is selected, and when only the stored value of the setup register is transferred, “setup” is selected.

The next button 113 is operated to display a screen for selecting other items to be selected. The close button 114 is operated when closing (erasing) the transformer screen.

In the mode setting field 115, a transfer mode is input. When the block (current block) to be displayed in the input column 62 is changed by operating the block switching unit 64 of the main screen (FIG. 4), the changed block is displayed in the transformer column 116 when the block is changed. Immediately (even if the user does not instruct the data transfer)
Whether to transfer to P board 21 is input. In the post-transform verification field 117, whether or not to verify the data is set for each data transfer. The enter button 118 is operated when finalizing the setting items on the transformer screen.

Next, with reference to the flowchart of FIG. 14, the transfer processing performed by the computer 1 when data transfer is instructed will be described.

In the transfer process, first, in step S6
In 1, it is determined from the computer 1 side whether to transmit or receive data. This determination is made with reference to the settings in the first selection field 111 of the transformer screen (FIG. 13).

If the data is to be transmitted, the process proceeds from step S61 to S62, where the data to be transferred is subjected to the same assembling processing as in FIG.
Go to 63. The assembling is performed for data set to be transferred on the transformer screen.

In step S63, it is determined whether or not an assembling error has occurred as a result of the assembling process in step S62. If it is determined that an assembling error has occurred, steps S64 to S67 are skipped, and the transfer process ends. That is, if there is an assembly error in the data to be transferred, the transfer is not performed.

Here, when data is transferred from the computer 1 to the DSP board 21, the assembling is performed for the following reason. That is, for example, the application program to be transferred is
As described above, no error occurs as long as it is created on the main screen (guide screen, if necessary).
However, when an application program created by another editor or the like is read on the main screen and transferred, there may be a mistake in the program. If a program having such a mistake is transferred to the DSP board 21 and the DSP is operated, a runaway may occur. Therefore, when transferring data from the computer 1 to the DSP board 21,
In order to prevent the transfer of the application program having such a mistake, the assembly is performed.

In step S63, step S62
As a result of the assembling process, if it is determined that no assembling error has occurred, the process proceeds to step S64, and data to be transmitted (for example, one block of data or the stored contents of the setup register, etc.) is specified according to the setting on the transformer screen. The designated data is transferred from the computer 1 to the DSP board 21, for example, word by word. Then, when the transfer of the specified data is completed, the process proceeds to step S65, where it is determined whether or not the verification is specified on the transformer screen. If it is determined that the verification is not specified, steps S66 and S67 are performed. Skip and end the transfer process.

If it is determined in step S65 that the verification is specified, the flow advances to step S66 to verify the transmitted data. That is, in step S66, the data transmitted to the DSP board 21 in step S64 is read (transferred) from the DSP board 21 and received by the computer 1. Then, the received data is compared with the data transmitted to the DSP board 21 in step S64.

When the verification is completed, step S67
To determine whether an error has occurred in the verification. If it is determined in step S67 that an error has occurred, that is, if the received data and the DSP
If the data does not match the data transmitted to the board 21, the process returns to step S64, and the data is retransmitted to the DSP board 21.

If it is determined in step S67 that no error has occurred, that is, if the above-described received data and the data transmitted to the DSP board 21 match, the transfer process ends.

On the other hand, when data is received as viewed from the computer 1, the process proceeds from step S61 to S68, where D
Data to be received from the SP board 21 is specified, and the specified data is transferred from the DSP board 21 to the computer 1 for each word, for example. When the transfer of the designated data is completed, the process proceeds to step S69, and the data, that is, the execution code transmitted from the DSP board 21 is disassembled, and the process proceeds to step S69.
Go to 70. In step S70, it is determined whether there is an error in the disassembly result. If it is determined that there is an error, the process returns to step S68.

On the other hand, if it is determined in step S70 that there is no error, the disassembly result in step S69 is displayed on, for example, the main screen (input box 62), and the transfer process ends.

In the transformer screen, when the block to be displayed in the input field 62 is changed by operating the block switching section 64 of the main screen, it is set that the changed block is transferred to the DSP board 21. If the block is changed, the processing after step S62 is automatically started when the block is changed.
In this case, by simply operating the block switching unit 64 on the main screen and changing the block, the changed application program is transferred to the DSP board 21. For example, various demonstrations of the DSP can be performed immediately. Can be performed.

Next, in this embodiment, a hidden screen is prepared as a programming support tool. The hidden screen is displayed, for example, at the lower right of the main screen as shown in FIG. 15 when the user clicks on the line number column 71 on the main screen.

In the line number input field 121S or 121E, the line number of the line to start copying or the line to end is input, respectively. The copy button 121 is operated when copying from the line with the line number input to the line number input column 121S to the line with the line number input to the line number line input column 121E.

[0200] The row number of the row to start deletion or the row to end is input to the row number input field 122S or 122E. The cut button 122 is moved from the line with the line number input to the line number input column 122S to the line number line input column 1
It is operated when deleting (cutting) up to the line with the line number input to 22E.

The line number of the line into which the copied or cut line is to be inserted is input to the line number input field 123A. Paste button 123 is operated to insert (paste) the copied or cut line into the line input in line number input field 123A.

The cursor 69 is displayed in the line number input field 124A.
Is entered. The long jump button 124 moves the cursor 69 to the line number input field 1
This is operated when jumping to the line of the line number input to 24.

The one-row insertion button 125 or the one-row deletion button 126 is operated when, for example, inserting one row before the row where the cursor 69 is positioned or deleting the row.

The error search & assemble button 127 or 128 is operated when assembling is performed on all the lines above or below the line where the cursor 69 is located.

The close button 129 is operated when closing the hidden screen.

Here, the error search & assemble buttons 127 and 128 are provided on the hidden screen, and when these are operated, the assembling is performed for the following reason.

That is, as described above, since the application program described on the main screen is assembled with the movement of the cursor 69, an application program free from mistakes is created at the end of programming. Will be. However, for example, when an externally created application program is read on the main screen, or finally, the instruction R of the DSP (FIG. 2) is executed.
For example, when obtaining a code for printing on the OM / RAM 24, it may be necessary to check whether or not an assembly error occurs. In order to cope with such a case, an error search & assemble button 127 or 128 for assembling on a hidden screen is used.
Is provided.

Here, the case where assembling is performed in the present embodiment is summarized as shown in FIG.

That is, the assembling is performed when the hidden screen is called from the main screen and the error search & assemble buttons 127 and 128 are operated, and also the guide screen is called from the main screen.
This is performed when 1 is operated. Also, assembling is
This is also performed when a transformer screen (trans menu screen) is called from the main screen and transmission of data to the DSP board 21 is instructed. Further, assembling is also performed when the cursor 69 moves on a line on the main screen. In addition, assembling is also performed when a file menu or an ethosetra menu is called from the main screen, and a file save is designated there.

Next, as described above, by performing programming on the main screen and, if necessary, the guide screen, the application program can be described efficiently and without errors. When the DSP of FIG. 2 executes the application program, the number of processing steps is often limited.

That is, as described above, the DSP of FIG.
It is for audio, but in such a DSP, when performing digital signal processing of audio,
Normally, it is necessary to perform a certain process between the input of a sample value of a certain sound and the input of the next sample value, that is, during one cycle of the sampling clock. In the present embodiment, the number of processing steps that can be executed during one cycle of the sampling clock is limited to, for example, 512 steps due to the relationship between the DSP clock and the sampling clock in FIG.

Therefore, even if it is possible to create an error-free application program, if the number of processing steps exceeds the number of processing steps that can be executed during one cycle of the sampling clock, the application program is executed by the DSP. Will not perform normal processing.

Therefore, it is necessary to check the number of processing steps of the application program. However, if the application program does not include an instruction that may change the execution order, that is, if the application program has a program counter Can be easily confirmed simply by counting the number of lines of the application program.

However, there is almost no case where the application program does not include an instruction that may change the execution order. That is, as instructions that the application program may change the execution order, the above-mentioned jump instruction (including both unconditional branch instructions and conditional branch instructions), a call instruction, a return instruction, a loop start instruction, A jump / call type command such as a loop jump command (in the present embodiment, a command input to the jump field 77 of the main screen, specifically,
There is a command displayed in the jump selection field 98 of the guide screen), but it is difficult to perform programming without using any jump / call commands.

Therefore, with respect to an application program including such a jump / call type instruction, a change in the execution order due to the jump / call type instruction is taken into consideration.
It is necessary to confirm the number of processing steps.

However, it is inefficient to perform this visually, and if the application program becomes complicated, the amount of work becomes enormous.

Therefore, in the development support program, all the jump / call instructions included in the application program are searched, and for all cases where the execution order is changed by the jump / call instructions,
There is a method of performing a simulation (software simulation) of the number of processing steps (virtually executing an application program) and obtaining the maximum value of the number of processing steps.

However, the number of simulations is enormous even if only branching / not branching of jump / call type instructions is considered. That is, if there are 10 jump / call instructions, for example,
The number of simulations is simply 1024 (= 2
¹⁰ ) times, and thus the time required for the simulation is enormous.

Furthermore, in reality, some jump / call instructions branch based on the stored value of the setup register 53 of the DSP, and such a setup that changes every processing step. It is necessary to grasp the register 53 and other stored values to determine whether to branch or not, which is troublesome.

Also, some jump / call instructions include
When there is an input from the user, there is a branch depending on the input, and it is difficult to determine whether such an instruction branches or not in a software (simulator) for performing simulation. .

Further, if the simulation is performed strictly for all functions that can be executed by the DSP, a model for performing the simulation must be constructed for all the functions.
It is a huge amount.

On the other hand, in order to eliminate errors (execution errors) at the time of execution, addresses output by the address generators 25 to 28 and RAMs 29 to 32 are used.
In some cases, it may be necessary to monitor data stored at the address. Furthermore, in the present embodiment, as described above,
There are an absolute specification and a relative specification, and in the case of a relative specification, there is a notation method such as n bits, so that it is convenient to monitor addresses and data. However, in the case where an enormous number of simulations are performed as described above, holding an address and data for each simulation requires an enormous storage area.

Therefore, in the present embodiment, the user is allowed to specify whether to jump or not, and how many times the loop jump is to be performed for the jump / call system instruction included in the application program. ,
A simulation is performed to display the execution order of application programs, addresses, data monitoring results, and the like. This process is called an address monitor process.

The address monitor process is performed when the address monitor button 61M (FIG. 4) is operated in a state where an application program to be subjected to the address monitor process is displayed in the input field 62 on the main screen. .

That is, in this case, for example, a first screen as shown in FIG. 17 is displayed.

In the first screen, the start address (St
The line number of the application program for starting the simulation is input to the art address column 131. Here, 000H is set as a default value. The execute button 132 is operated (clicked) to start searching for a jump / call-related instruction included in the application program. The close button 133 is operated when closing the first screen.

In the state where the first screen as described above is displayed, an address for starting the simulation (hereinafter, appropriately referred to as a start address) is input to the start address column 131, and the execution button 132 is operated. Is searched for a jump / call instruction from the line after the start address. And
When the search ends, for example, a second screen as shown in FIG. 18 is displayed.

In the second screen, the condition load button 14
1 is operated when the previously set conditions are loaded from a file on the second screen. The condition save button 142 is operated when the conditions set on the second screen are saved in a file. The jump / call-related instruction (conditional branch instruction) display field 143 displays the number of jump / call-related instructions as a search result of the jump / call-related instruction.

Next page button 144 or previous page button 145
Is operated to display the second screen of the next page or the previous page. That is, in this embodiment, the number of lines of one block of the application program is 1024 at the maximum, and the number of processing steps that can be executed during one cycle of the sampling clock is, as described above, 512
Has become a step. Therefore, taking these factors into consideration, the maximum search number of jump / call type instructions is set to, for example,
Limited to On the other hand, on the second screen,
At most, for example, search results of 20 jump / call-related instructions are displayed. In order to display all the jump / call-related commands when the maximum number of search commands is 100, the second screen is displayed as follows.
5 (= 100/20) pages are prepared. It should be noted that the maximum search number of jump / call type instructions is not limited to 100.

As described above, the second page prepared for only five pages
When changing the page to be displayed on the screen, the next page button 144 and the previous page button 145 are operated.

The close button 146 is operated when closing the second screen. The execute button 147 simulates (starts) the application program according to the conditions set on the second screen.
Sometimes operated.

In the search result display column 148, the search results of jump / call type instructions are displayed in units of 20 (20 lines), and whether to branch or not, and how many times the loop jump is performed. A field for allowing the user to specify conditions is displayed.

That is, in the search result display column 148,
In the leftmost column, a sequential number assigned to a search result of a jump / call type instruction is displayed.
Further, in the second and third columns from the left, the line number in which the searched jump / call instruction is described and the jump / call instruction are displayed.

Then, at the fourth position from the left, branch or
A column ("branch yes no") for designating whether to perform the loop jump is displayed, and a column ("number of loops") for designating the number of loop jumps is displayed on the rightmost side.

In the state where the second screen is displayed, the user designates, for each jump / call-related instruction, conditions such as whether or not to branch and how many times the loop jump is performed, as required.

Here, conditions are set automatically for jump / call-related instructions that can be dealt with without any designation from the user. That is, for example,
For a return instruction or an unconditional branch instruction, a setting for branching is automatically made, so that the user does not need to specify a condition for such a jump / call instruction. It is done.

Also, the specified condition is, as described above,
By operating the condition save button 142, the conditions are saved in a file. Further, by operating the condition load button 141, the saved conditions can be loaded into the search result display field 148. Thus, the condition specified in the past does not have to be specified again. When a designated condition is saved in a file, its extension is set to, for example, m24 in order to distinguish it from the above-mentioned file.

In the search result display field 148, when the execute button 147 is operated after the necessary conditions are specified, based on the specification (in accordance with the specification of whether to branch or not, and the number of loop jumps), A simulation of the application program is performed.

Then, when the simulation is completed, for example, a third screen as shown in FIG. 19 is displayed.

On the third screen, the monitor result print button 151 is operated when printing the simulation result in the simulation result display field 153.
The close button 152 is operated when closing the third screen. In the simulation result display column 153,
The result of the simulation performed as specified on the second screen is displayed.

That is, in the leftmost column (“step”),
The number of processing steps is displayed. The second column from the left ("Ia
dd ") indicates the line number in which the instruction executed in each step is described. The third to sixth columns from the left ("Kadd", "Dadd", "DFadd", "DSadd")
In each step, the address generators 25 to 2
8 are KRAM 29, DRAM 30, DfRAM 31,
Address output to DsRAM 32 (absolute address)
Are displayed respectively. At this time, it is also possible to display the data stored at each address.

In the leftmost column (“comment”), the comment entered in the comment column 80 of the input screen is displayed in each step.

In FIG. 20, by setting conditions as shown in the second screen of FIG. 18 and performing a simulation, an application which can obtain a simulation result as shown in the third screen of FIG. Here is a part of (the source code of) the program.

In the embodiment shown in FIG. 20, for example,
On line 013, there is a call instruction “call05d” which is one of the jump / call instructions. This call instruction "c
The lower three digits of "all05d" represent the program address (line number) of the jump (call) destination (not only call instructions, but all jump / call-related instructions that specify the program address of the jump destination are the same) Therefore, according to the call instruction “call05d”, the program address 05d
A branch (jump) to H is performed.

Here, in the embodiment of FIG. 19, the program address is not the next step of the 013H line where the call instruction “call05d” is described, but is the next step. 05dH
, Which is, as described above, the D in FIG.
This is because SP has an architecture in which a jump by a jump / call type instruction is performed with a delay of two clocks.

In the embodiments of FIGS. 17 to 19, the first to third screens are shown one by one. However, the first to third screens are actually, for example, as shown in FIG. , Are overlapped with the main screen and displayed on one screen. That is, the first to third screens are, for example,
If the display 9 has a resolution of about 800 × 600 dots, it is configured to have a size that can be displayed on one screen.

Next, the address monitoring process will be further described with reference to the flowchart of FIG.

On the main screen, while the application program to be subjected to the address monitor processing is displayed in the input column 62, the address monitor button 61 is displayed.
When M is operated, an address monitor process is performed.

That is, first, in step S71, the first screen shown in FIG. 17 is displayed. Then, the process proceeds to step S72, where it is determined whether or not the execution button 132 has been operated, and if it is determined that the execution button 132 has not been operated,
Proceeding to step S73, it is determined whether the close button 133 has been operated. If it is determined in step S73 that the close button 133 has been operated, the process proceeds to step S74, where the first screen is closed, and the address monitoring process ends.

If it is determined in step S73 that the close button 133 has not been operated, the process returns to step S72. Then, in step S72,
If it is determined that the execute button 132 has been operated, the process proceeds to step S75, where a jump / call-related command in the application program is searched for, and the process proceeds to step S7.
Proceed to 6.

In step S76, the second screen (FIG. 18) in which the search result of the jump / call type command in step S75 is arranged in the search result display column 148 is displayed.

The flow advances to step S77 to determine whether the condition load button 141 has been operated. If it is determined in step S77 that the condition load button 141 has been operated, the process proceeds to step S78, in which a condition saved in the past is read, and a condition load process for reflecting the condition in the search result display column 148 is performed. Then, the process returns to step S77. If it is determined in step S77 that the condition load button 141 has not been operated, the process proceeds to step S79, and it is determined whether the condition save button 142 has been operated. If it is determined in step S79 that the condition save button 142 has been operated, the process proceeds to step S80, in which the conditions input in the search result display field 148 are saved in a file, and the process returns to step S77. If it is determined in step S79 that the condition save button 142 has not been operated, the process proceeds to step S81, and the next page button 14
It is determined whether 4 or the previous page button 145 has been operated.

In step S81, the next page button 14
If it is determined that the 4 or previous page button 145 has been operated, the process proceeds to step S82, and the page of the second screen to be displayed is changed in accordance with the operation (instead of the second screen of the currently displayed page). Then, the second screen of the next page or the previous page is displayed), and the process returns to step S77. Step S8
1, the next page button 144 and the previous page button 145
If it is determined that none of the above has been operated, the process proceeds to step S83, and it is determined whether or not the close button 146 has been operated. If it is determined in step S83 that the close button 146 has been operated, step S8
Proceeding to step S4, the second screen is closed, and the process returns to step S72.

If it is determined in step S83 that the close button 146 has not been operated, the flow advances to step S85 to determine whether the execute button 147 has been operated. If it is determined in step S85 that the execute button 147 has not been operated, the process returns to step S77. If it is determined in step S85 that the execution button 147 has been operated, that is, if a condition has been entered in the search result display field 148 and the execution button 147 has been operated, the process proceeds to step S86, where the application program Simulation is the first
The search is performed from the start address input in the start address column 131 of the screen according to the conditions input in the search result display column 148 of the second screen.

Then, when the simulation is completed, the flow advances to step S87, and the simulation result is displayed in the third result displayed in the simulation result display column 153.
A screen (FIG. 19) is displayed.

After the third screen is displayed, step S8
Proceeding to 8, it is determined whether the monitor result print button 151 has been operated. If it is determined in step S88 that the monitor result print button 151 has been operated, the process proceeds to step S89, in which the simulation result displayed in the simulation result display column 153 is printed, and the process returns to step S88. Step S8
In step S8, when it is determined that the monitor result print button 151 has not been operated, the process proceeds to step S90, and it is determined whether the close button 152 has been operated. If it is determined in step S90 that the close button 152 has not been operated, the process returns to step S88.

If it is determined in step S90 that the close button 152 has been operated, the process proceeds to step S90.
Proceeding to 91, the third screen is closed, step S77
Return to

It should be noted that whether or not various buttons provided on each of the first to third screens has been operated is actually determined in parallel as in the case of the embodiment shown in FIG. It has been made.

Here, in the present embodiment, as described above, the number of lines of an application program in one block is limited to a maximum of 1024 lines, but the number of main routines and subroutines in one block is particularly limited. Not done. However, in the present embodiment, as described above, an application program having a processing step number exceeding 512 cannot be executed on an actual DSP.
If the value exceeds 512, for example, 1024, the address monitor process is forcibly terminated. Basically, the end instruction ("ed")
Is executed, the process ends normally.

As described above, for the jump / call type instruction, the user is allowed to specify whether or not to branch and the number of loops, and the simulation is performed according to the specification. Can be terminated.

Further, the number of processing steps and the address of the application program can be easily confirmed. Further, it is possible to realize a simple debugging function and a tracing function focusing on a change in address. And
As a result, it is possible to improve the design efficiency of the application program.

In the present embodiment, the DSP is
Although the thing for audio was used, the present invention
The present invention is also applicable to a DSP used for image processing and the like. Further, the present invention can be applied to a CPU and other processors that perform processes corresponding to a plurality of instructions in parallel, in addition to the DSP.

[0263]

According to the information processing apparatus according to the first aspect and the information processing method according to the fourth aspect, a processor program, which is a program to be executed by a processor, comprises:
Instructions that may change the execution order are searched. Then, when the instruction specifies whether to change the execution order of the processor program, the processor program is virtually executed based on the specification, and the execution order is displayed. The recording medium according to claim 5 includes:
The processor program, which is a program to be executed by the processor, is searched for an instruction that may change the execution order, and when the instruction specifies whether to change the execution order of the processor program, the search is performed. A computer program for causing a computer to virtually execute a processor program based on the designation and display the execution order is recorded. Therefore, it is possible to easily know the execution order of the program and the like.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of an embodiment of a program development support system to which the present invention has been applied.

FIG. 2 shows a DS mounted on the DSP board 21 of FIG.
FIG. 4 is a block diagram illustrating a configuration example of P.

FIG. 3 is a diagram showing a format of a machine code executed by the DSP of FIG. 2;

FIG. 4 is a diagram showing a main screen.

FIG. 5 is a diagram showing an input field 62 on the main screen.

FIG. 6 is a diagram showing an example of input to an input field 62;

FIG. 7 is a diagram showing a guide screen.

FIG. 8 is a flowchart illustrating an edit process.

FIG. 9 is a flowchart illustrating details of an assembling process in step S5 of FIG. 8;

FIG. 10 is a flowchart illustrating details of a guide process in step S4 of FIG. 8;

FIG. 11 is a flowchart illustrating details of a narrowing-down process in step S24 of FIG. 10;

FIG. 12 is a diagram showing a display example of a guide screen.

FIG. 13 is a diagram showing a transformer screen.

FIG. 14 is a flowchart illustrating a transfer process.

FIG. 15 is a diagram showing a hidden screen.

FIG. 16 is a diagram for explaining a case where assembling is performed.

FIG. 17 is a diagram showing a first screen.

FIG. 18 is a diagram showing a second screen.

FIG. 19 is a diagram showing a third screen.

FIG. 20 is a diagram showing source codes of an application program.

FIG. 21 is a diagram showing a display example of first to third screens.

FIG. 22 is a flowchart illustrating an address monitor process.

[Explanation of symbols]

1 computer, 2 ROM, 3 CPU, 4
RAM, 5 input control unit, 6 mouse, 7 keyboard, 8 display control unit, 9 display,
10 hard disk control unit, 11 hard disk, 12 CD control unit, 13 CD-ROM, 1
4 printer control unit, 15 communication unit, 16 bus,
17 printer, 21 DSP board, 22 control unit, 23 instruction address generator, 24 instruction ROM / RAM, 2
5 to 28 address generator, 29 to 32
RAM, 33R1 register, 34R2 register, 35 adder, 36K register, 37D register, 38 multiplier, 39 shifter, 40P register, 41 adder, 42 limiter, 43
B register, 44, 45 Accumulator, 46
B register, 47 AND / OR gate, 48
Sequencer, 49 barrel shifter, 50 limiter, 51 jump set register, 52 AD register, 53 setup register, 54 main bus

Claims (5)

[Claims] 1. An information processing apparatus that performs virtually the same processing as a predetermined processor, and retrieves, from a processor program that is a program executed by the processor, instructions that may change the execution order. Searching means; specifying means for specifying whether to change the execution order of the processor program according to the instructions searched by the searching means; and the processor program based on the specification performed by the specifying means. An information processing apparatus, comprising: an execution unit that virtually executes the processing; and a display unit that displays an execution order of the processor program by the execution unit. 2. An instruction relating to a conditional branch among instructions retrieved by the retrieval unit, wherein the designation unit can designate whether to branch or not. An information processing apparatus according to claim 1. 3. An instruction relating to a loop among instructions retrieved by said retrieval unit, wherein the designation unit can designate the number of loops.
An information processing apparatus according to claim 1. 4. An information processing method for an information processing apparatus that performs virtually the same processing as a predetermined processor, wherein the execution order may be changed from a processor program that is a program executed by the processor. When an instruction is searched and an instruction to change the execution order of the processor program is given by the instruction, the processor program is virtually executed based on the designation, and the execution order is displayed. An information processing method comprising: 5. A computer program for causing a computer to execute virtually the same processing as a predetermined processor on a recording medium on which a computer program which is a program to be executed by a computer is recorded. A search is made for instructions that may change the execution order from a processor program that is a program to be executed, and if the instructions specify whether to change the execution order of the processor program, A computer-readable storage medium storing a computer program for virtually executing the processor program based on the computer program and performing a process of displaying the execution order.