JPH1110841A - Recorder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a recorder for conducting a bidirectional H/V conversion (for realigning recorded data input to match a constitution of a recording head) by using one buffer. SOLUTION: In the case of recording image data of H pixel × N line on a recording medium in the case of both moving a recording head in a forward route and moving the head in a return route by using a data buffer for storing the data, at the time of recording via the moving along the forward route of a mode B, the data is read by each N pixels for a predetermined number of pixels from the buffer, and the data is stored by each predetermined number of pixels in the buffer for the N lines. Meanwhile, at the time of recording via the moving along the return route of a mode A, the data is read at an interval of predetermined number of pixels from the buffer, and the data is stored in the buffer for the one line to record via next forward route of the head. Inputting and outputting of the data of the first and second modes are switched at each time of switching the forward and return route movings.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a recording apparatus, and more particularly to a recording apparatus which performs recording on both the forward path and the return path of a reciprocating movement of a recording head.

[0002]

2. Description of the Related Art A conventional serial printer has attempted to improve throughput by increasing the number of dots that can be recorded at one time. For example, in a printer using a recording head that performs recording according to an ink jet system, a direction (sub-scanning direction) perpendicular to the scanning direction (main scanning direction) of the recording head.
In order to improve the throughput, a plurality of lines are printed by arranging nozzles for ejecting ink in one scan of the print head. Further, in order to further improve the throughput, some printers are capable of performing bidirectional printing in which a printing operation is performed in both the forward and backward paths of the reciprocating movement of the print head.

On the other hand, since image data in which pixels are arranged in the main scanning direction are sequentially input line by line from a host computer (hereinafter, referred to as a host), a printer head capable of bidirectional printing has a recording head configuration. Therefore, an operation (hereinafter, referred to as bidirectional HV conversion) for rearranging the arrangement of the input recording data in accordance with is required.

Now, one of the typical bidirectional HV conversions is:
There is a double-buffer system in which buffers for writing and reading image data are separately provided, and the buffers for writing and reading are switched when the writing and reading operations of the image data are completed.

FIG. 11 is a diagram showing the concept of bidirectional HV conversion performed using the double buffer system.

First, as shown in FIG. 11A, image data transferred from the host to the buffer # and arranged in the main scanning direction of the recording head is written for each line. When image data for a predetermined number of lines (the number of nozzles) is written to the buffer #, as shown in FIG.
The image data is written line by line, while the image data from the buffer # is arranged in columns in the sub-scanning direction in the sub-scanning direction (in the direction of the nozzle arrangement) according to the forward scan of the recording head (FIG. 11B () Arrow direction).

Further, when the reading of the image data stored in the buffer # is completed and the image data of a predetermined number of lines (the number of nozzles) is written in the buffer B, FIG.
As shown in (c), image data transferred from the host and arranged in the main scanning direction of the print head is written line by line into the buffer #, while image data from the buffer B is arranged in the sub-scanning direction. , The image data is sequentially read for each column according to the backward scanning of the recording head (in the direction of the arrow in FIG. 11C).

Subsequently, when the reading of the image data stored in the buffer B has been completed and the image data of a predetermined number of lines (the number of nozzles) has been written into the buffer #, FIG. As shown in the figure, the image data is written again to the buffer B, and the image data is sequentially read from the buffer A again in the forward scan of the print head (in the direction of the arrow in FIG. 11D). When the reading of the image data stored in the buffer A is completed and the image data of a predetermined number of lines (the number of nozzles) is written to the buffer B,
As shown in FIG. 11E, the image data is written into the buffer A, and the image data is sequentially read from the buffer B according to the backward scanning of the recording head (in the direction of the arrow in FIG. 11E).

Hereinafter, the operation shown in FIGS. 11B to 10E is repeated until all the image data is recorded on a recording medium such as recording paper.

FIG. 12 is a block diagram showing a configuration of a bidirectional HV conversion circuit for performing bidirectional HV conversion using a conventional double buffer system. In this example, the circuit is configured to execute bidirectional HV conversion using one RAM. That is, the buffer A and the buffer B described in FIG. 11 are secured in one RAM.

According to the circuit shown in FIG. 12, when the interface (I / F) circuit 103 receives image data from the input terminal 101, it outputs a request signal (Req) to the controller 104. The controller 104 receives the request signal and outputs an acknowledgment signal (Ack) to the interface circuit 103 if data can be stored in the RAM 109.
The selector 107 is operated so as to be output to the address bus 9 and the RAM 109 is set to the write mode.

The interface circuit 103 receives the acknowledge signal, outputs image data to the data bus 201, and stops outputting the request signal. The controller 104 confirms that the request signal is no longer output, ends the data storage in the RAM 109, and increments the count value of the counter 105. The selector 106 receives the mode signal (M
ODE), when writing image data to the buffer # (buffer A mode), the start address
When the image data is written into the buffer 105 (buffer B mode), the head address B is output to the counter 105. Counter 1
Reference numeral 05 loads the head address output from the selector 106 in response to a load signal (Load) from the controller 104 when switching the buffer for writing image data. Therefore, when writing the image data into the buffer #, the image data is stored from the head address # and the buffer B
When the image data is written in the image data, the image data is stored from the head address B.

On the other hand, when a read pulse is input from the input terminal 102, the controller 104 selects the selector 1 so that the value of the address generation circuit 108 is output to the address of the RAM 109 unless the RAM 109 is in the write mode.
07, the data stored in the RAM 109 is read, the read data is stored in the bit plane read circuit 111 via the data bus 201, and the count value of the counter 112 is incremented. When the count value is incremented N times, the counter 112
It is configured to output a carry signal (Carry).
When the read pulse is input and the RAM 109 is in the write mode, the above operation is executed after the writing to the RAM 109 is completed. The bit plane reading circuit 111 includes two buffers each having a capacity of the number of nozzles (N) of the recording head × the word length of one line (H: the number of dots of one line divided by the word length of the RAM 109) ( (Double buffer), HV conversion in a word is executed, and at the same time, control is performed so that data is output from the output terminal 113 in synchronization with a clock.

Further, when the counter 112 switches between the buffer mode and the buffer B mode, the counter 112 outputs a load (reset) signal (Load (R)
reset). Counter 112
Is an enable signal (EN) from the controller 104
Count from “0” to “N−1” (ie, N
The carry signal is output to the up / down (U / D) counter 110 and the up / down counter 110 is counted up or down. Count down.

That is, an up / down (U / D) counter 1
10 is "0" in the buffer A mode,
In the mode, “(H / N) −1” is loaded by the load (reset) signal of the controller 104 when each mode is switched. Thereafter, in the buffer A mode, the counter counts up, and in the buffer B mode, counts down in accordance with the carry signal of the counter 112.

An address generation circuit 108 accesses an address (A) to the RAM 109 based on the count values of an up / down (U / D) counter 110 and a counter 112.
dr) is generated and output to the selector 107. For example,
The count value of the up / down (U / D) counter 110 is “x”, the count value of the counter 112 is “y”, the number of words in one line is “H”, the head address of the buffer A is “A0”, Assuming that the start address is "B0", the address (@dr) of the RAM 109 is as follows.

Adr = x + Hy + A0 (buffer A mode) Adr = x + Hy + B0 (buffer B mode) The address generation circuit 108 obtains x obtained from the up / down (U / D) counter 110 and the counter 112 according to the above equation. , Y, and Adr is calculated, and selector 10
7 is output.

The controller 104 has a counter 105
And the output from the address generation circuit 108 are connected, and by comparing with a predetermined address, the processing state of each buffer is detected. When the processing in both buffers is completed, writing and reading are performed. The buffer to be switched is switched. That is, assuming that the image data is written to the buffer Α and the image data is read from the buffer B, when all the buffers have accessed the last data address, the next write operation is performed to the buffer B. On the other hand, the next read operation is performed in the buffer A.

As described above, by alternately using the two buffers for the writing and reading operations and parallelizing the input / output processing of the image data, the data can be processed smoothly without interruption.

[0020]

However, in the above conventional example, since two buffers for writing and reading image data are required, at least one recording head is required.
A memory capacity twice as large as the image data capacity required when performing a recording operation by performing multiple scans is required, and there has been a problem that a circuit size is increased and a cost is increased.

The present invention has been made in view of the above problems, and has as its object to provide a recording apparatus capable of performing bidirectional HV conversion using one buffer.

[0022]

To achieve the above object, a recording apparatus according to the present invention comprises the following steps.

That is, a data buffer having a length of H pixels in the first direction and L lines in the second direction and storing image data for H pixels × L lines is used. A recording apparatus that performs recording on a recording medium during both a forward movement and a backward movement of the reciprocating movement while reciprocating a recording head in which a plurality of recording elements are arranged in the first direction. Input means for inputting image data in which pixels are arranged in a first direction, initial writing means for storing L lines of image data in the data buffer for each of H pixels along the first direction; A first reading unit that reads out the image data by a predetermined number of pixels in the first direction from the data buffer in the second direction during the recording operation by moving the head in the first direction; By reading means In the area of the data buffer read and read, for the recording operation by the return movement of the recording head, image data for the predetermined number of pixels is written in the data buffer by L lines along the first direction. First writing means for storing, and second reading means for reading out the image data from the data buffer at the predetermined number of pixels along the first direction during a printing operation by the backward movement of the printing head; A second writing unit for storing image data in the data buffer by one line in the first direction for the next forward movement of the recording head for the recording operation; Switching means for switching between a first mode for operating the writing means and a second mode for operating the second reading and writing means; and switching between forward movement and backward movement of the recording head. Every time it changes,
And a switching control unit for controlling the switching unit so as to switch between the first mode and the second mode.

Further, in the first mode, the operation by the first reading and writing means is continued until the reading operation by the first reading means and the writing operation by the first writing means are completed with respect to the entire area of the data buffer. First control means for controlling the first read and write means so as to be repeated, and, in the second mode, a read operation by the second read means and a write operation by the second write means for all areas of the data buffer. And a second control means for controlling the second reading and writing means so as to repeat the operation by the second reading and writing means until the operation is completed.

Further, the apparatus may further include a conveying means for conveying the recording medium in the second direction.

Further, the operation of the first reading and writing means and its repetition control, and the operation of the second reading and writing means and its repetition control until the input / output processing of the predetermined amount of image data is completed. May be controlled to be repeated.

Further, a plurality of counters may be used for determining an address for accessing the data buffer in the first read / write means and the second read / write means.

Further, the write address of the current image data is generated from the difference between the write address of the previous and current image data, and the read address of the current image data is calculated from the difference between the read address of the previous and current image data. May be generated.

Further, the first and second reading means and the first
The second writing means may use a counter for counting up or counting down the number of pixels for reading / writing image data.

Here, the recording head may be an ink jet recording head that performs recording by discharging ink,
Alternatively, a recording head that ejects ink by using thermal energy may include a thermal energy converter for generating thermal energy to be applied to the ink.

With the above configuration, the present invention operates as follows.

That is, a data buffer having a length of H pixels in the first direction and L lines in the second direction and storing image data for H pixels × L lines is used, and L pixels in the second direction are used. When performing recording on the recording medium during both the forward movement and the backward movement while reciprocating the recording head in which the recording elements are arranged in the first direction, first, H is set along the first direction. The image data for each line is stored in the data buffer for L lines, and the image data is stored in the data buffer in the first direction by L pixels in the second direction during the recording operation by the forward movement of the recording head in the first mode. A predetermined number of pixels are read out in the direction, and in the read data buffer area, the image data is shifted by a predetermined number of pixels along the first direction into the L direction for the printing operation by the return movement of the print head. Line minutes It is stored in the buffer. On the other hand, at the time of the recording operation by the return movement of the recording head in the second mode, the image data is read out from the data buffer at a predetermined number of pixels along the first direction, and the recording operation by the next forward movement of the recording head is performed. For this purpose, the image data is stored in the data buffer one line at a time along the first direction. The writing and reading operations of the image data in the first mode and the writing and reading operations of the image data in the second mode are performed every time the recording head switches between the forward movement and the backward movement. It is controlled to switch.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

<Schematic Description of Apparatus Main Body> FIG. 1 is an external perspective view showing an outline of a configuration of an ink jet printer (hereinafter, referred to as a printer) IJRA which is a typical embodiment of the present invention. In FIG. 1, a spiral groove 50 of a lead screw 5005 that rotates via driving force transmission gears 5009 to 5011 in conjunction with forward / reverse rotation of a drive motor 5013.
The carriage HC that engages with the pin 04 is a pin (not shown).
And supported by the guide rail 5003 and arrows a and b
Reciprocate in the direction. On the carriage HC, an integrated type ink jet cartridge IJC containing a recording head IJH and an ink tank IT is mounted. 5002
Denotes a paper pressing plate, which presses the recording paper P against the platen 5000 in the moving direction of the carriage HC. 50
Reference numerals 07 and 5008 denote photocouplers, which confirm the presence of a carriage lever 5006 in this area, and
Is a home position detector for switching the rotation direction of the camera. A member 5016 supports a cap member 5022 for capping the front surface of the recording head IJH.
Reference numeral 15 denotes a suction device that suctions the inside of the cap, and performs suction recovery of the recording head through the opening 5023 in the cap. 5
Reference numeral 017 denotes a cleaning blade. Reference numeral 5019 denotes a member which allows the blade to move in the front-rear direction. These members are supported by a main body support plate 5018. It goes without saying that the blade is not limited to this form and a known cleaning blade can be applied to this example. Reference numeral 5021 denotes a lever for starting suction for recovery of suction. The lever 5021 moves with the movement of the cam 5020 that engages with the carriage, and the driving force from the driving motor is controlled by a known transmission mechanism such as clutch switching. Is done.

The capping, cleaning, and suction recovery are configured so that desired operations can be performed at the corresponding positions by the action of the lead screw 5005 when the carriage comes to the area on the home position side. If a desired operation is performed at the timing, any of the embodiments can be applied.

Further, it is assumed that the recording head IJH has N recording elements for ejecting ink in the transport direction of the recording paper.

Further, the printer IJRA has a recording head I
Recording can be performed in both directions when the JH moves in the direction of arrow a (forward direction) and when the JH moves in the direction of arrow b (return direction).

<Description of Control Structure> Next, a control structure for executing the recording control of the above-described apparatus will be described.

FIG. 2 is a block diagram showing a configuration of a control circuit of the ink jet printer IJRA. In the figure showing the control circuit, the same components as those described in FIG. 12 are denoted by the same reference numerals, and description thereof will be omitted. 17
01 is an MPU, 1702 is a ROM for storing a control program to be executed by the MPU 1701, and 1703 is a work area for temporarily storing various data (such as input image data and image data to be supplied to the printhead IJH) and for executing a control program. RAM 1704 is a bidirectional H
This is a bidirectional HV conversion circuit that performs V conversion. Reference numeral 1710 denotes a carrier motor for transporting the recording head IJH;
Reference numeral 09 denotes a transport motor for transporting the recording paper. 170
5 is a head driver for driving the recording head IJH, 17
Reference numerals 06 and 1707 denote motor drivers for driving the transport motor 1709 and the carrier motor 1710, respectively.

The RAM 1703 has a recording head IJ
One buffer for storing data corresponding to image data recorded by one scan of H is secured. Logically, this buffer has the maximum number of pixels (LP) of image data that can be recorded in the scanning direction of the recording head IJH as the buffer length, and the number of recording elements in which the recording head IJH is arranged in the recording paper transport direction (LP). WP) as a buffer width, and has a rectangular area as a storage area for image data.

An outline of the operation of the above control configuration will be described. When image data is input to the interface 103, the MPU
A bidirectional HV conversion circuit 1704 performs bidirectional HV conversion of input image data according to an instruction of
The output image data 705 is bidirectional HV converted.
Then, the motor drivers 1706 and 1707 are driven, and the printhead IJH is driven in accordance with the image data sent to the head driver 1705 to perform printing.

FIG. 3 is a block diagram showing a detailed configuration of the bidirectional HV conversion circuit 1704. In FIG. 3, FIG.
The same components as those described in 2 are denoted by the same reference numerals, and description thereof will be omitted. As can be seen from a comparison with FIG. 2, among the components shown in FIG. 3, components other than the interface (I / F) 103 and the RAM 1703 are components of the bidirectional HV conversion circuit 1704.

In FIG. 3, 12 and 25 are counters, 1
Reference numeral 3 denotes an up / down (U / D) counter for outputting a carry signal (Carry) when the count value is incremented (or decremented) N times, and 14 denotes a carry when the count value is incremented (or decremented) M times. An up / down (U / D) counter that outputs a signal (Carry), 26 is a counter that outputs a carry signal (Carry) when the count value is incremented M times, 27
Is a counter that outputs a carry signal (Carry) when the count value is incremented N times, 16 and 23 are matrix switches, 17 is a RAM controller, 18,
21 is an address generation circuit, and 20 is an address controller.

In the following description, the number of words per line (buffer length (L
P) divided by the number of words in the RAM 1703) is “H”, the number of lines of image data that can be stored in the buffer is “N” (this is equal to the buffer width (WP)), and H is N
The number (rounded up below the decimal point) divided by is defined as “M”. For the sake of simplicity, the number of words per line (H) and the number of pixels of the maximum recording length (V) in the transport direction of one page of recording paper are integral multiples of the number of lines (N) in the buffer. (Ie, H = N × M; V = n × N; H = m × N;
m, n: natural numbers).

First, the interface circuit (I / F) 10
3 receives the image data from the input terminal 101,
A request signal (Req) is output to the M controller 17. In response to the reception of the request signal, the RAM controller 17 outputs an acknowledgment signal (Ack) to the interface circuit 103 if data can be stored in the buffer of the RAM 1703, and outputs from the address generation circuit 18 the address of the RAM 1703. The selector 107 is operated so as to be output to the bus, and the RAM 1703 is set to the write mode.

On the other hand, the interface circuit (I / F) 10
3 receives the acknowledge signal,
1 to output the image data and stop outputting the request signal. The RAM controller 17 confirms that the output of the request signal has ceased, ends the data storage in the RAM 1703, and sets the up / down (U / D) counter 14
Is incremented in the A mode, decremented in the B mode, and the output of the acknowledge signal is stopped.
The details of each mode will be described later.

The input terminal 102 from the MPU 1701
When the read pulse is input through the RAM controller 17, if the RAM 1703 is not in the write mode, the output from the address generation circuit 21 is output to the RAM 1703.
The selector 19 is operated so that the image data is output to the address bus, the image data stored in the RAM 1703 is read out, and the image data is stored in the buffer of the bit plane readout circuit 111 via the data bus 201 and the count of the counter 27 is counted. Increment the value. on the other hand,
When the RAM 1703 is in the write mode, the RAM 17
After completion of the write operation to the memory cell 03, the above operation is executed. The bit plane read circuit 111 has a double buffer configuration as described with reference to FIG. 11, and is controlled so as to execute HV conversion within one word and output image data in synchronization with a clock from an output terminal 113 at the same time. .

The count values of the counters 12, 25 to 27 are reset by a reset signal (Reset) from the address controller 20 when switching between the A mode and the B mode. The up / down (U / D) counter 13 and the up / down (U / D) counter 14 are loaded with “0” when switching from mode B to mode A, and address controller when switching from mode A to mode B. In response to the reset (load) signal from 20, the counters are loaded with "N-1" and "M-1".

Now, an up / down (U / D) counter 1
4 counts up M times from "0" to "M-1" in mode A by an enable signal (EN) from the RAM controller 17, and when the count value is "M-1," the enable signal is input. And carry signal (Ca
ry) is output to an up / down (U / D) counter 13, and the count value of the counter 13 is counted up.
In the mode B, the countdown is performed M times from “M−1” to “0”, and when the enable signal is input when the count value is “0”, the carry signal (Carry) is up / down (U / D). It outputs to the counter 13 and counts down the count value of the counter 13.

On the other hand, an up / down (U / D) counter 1
Numeral 3 indicates a carry signal (Carry) from the up / down (U / D) counter 14 in the mode A from “0” to “N”.
When the carry value (Carry) is input from the up / down (U / D) counter 14 when the count value is “N−1”, the carry signal is output to the counter 12. , And counts up the counter 12. In the mode B, "N-1" is changed to "0".
The carry signal (Carry) is counted up and down (U / N) when the count value is “0”.
D) When input from the counter 14, the carry signal (Car
ry) is output to the counter 12, and the counter 12 is counted up.

The count values of the counter 12 and the up / down (U / D) counter 13 are
Is output to the address generation circuit 18 through The matrix switch 16 has a counter 12 and an up / down (U /
D) The count value of the counter 13 is switched for each mode and output. For example, in the B mode, the count value of the up / down (U / D) counter 13 is output from the output terminal y.
The count value of the counter 12 is output from the output terminal z,
In the A mode, up / down (U /
D) The count value of the counter 13 is output from the output terminal y, and the count value of the counter 12 is output from the output terminal y.

The address generation circuit 18 converts the count value (x) of the up / down (U / D) counter 14 and the output values from the output terminals y and z of the matrix switch 16 (these values are referred to as y and z, respectively). RAM 1703 based on
, And outputs it to selector 107. Here, assuming that the head address of the buffer is A0, the generated address (Αdr) is as shown in Expression (1).

Adr = x + Hy + M · z + A0 (1) Since H = N × M, 0 ≦ x ≦ M−1, and 0 ≦ y ≦ N−1, N = 2 ⁿ , M = when the lower A0 (n + m) bits are all "0" at 2 ^m, the address generating circuit 18 can be constituted by merging bits (i.e., wiring only). Even if the above conditions are not satisfied, if there is room in the capacity of the RAM 1703, the address generation circuit 18 may be configured by merging bits. At this time, H and M in the above equation (1) are rounded up to the power of 2. Further, the address generation circuit 18 may be configured by a look-up table (LUT) or an arithmetic circuit.

The counter 27 is counted N times from "0" to "N-1" by an enable signal (EN) from the RAM controller 17, and the count value is N.
When the enable signal is input at −1, a carry signal (Carry) is output to the counter 26, and the counter 26
Count up. The counter 26 counts up M times from “0” to “M−1” by the carry signal from the counter 27, and when the carry signal from the counter 27 is input when the count value is M−1, the carry signal ( Carry) to the counter 25.
Count up. The count values of the counters 25 and 27 are output to the address generation circuit 21 via the matrix switch 23. Matrix switch 23
Replaces the count values of the counter 25 and the counter 27 for each mode. For example, in the Α mode, the count value of the counter 27 is output from the output terminal y, and from the output terminal z, the count value of the counter 25 is output. On the other hand, in the B mode, the count value of the counter 27 is output from the output terminal z. The output terminal y outputs the count value of the counter 25.

The address generation circuit 21 determines the RAM 17 based on the count value (x) of the counter 26 and the outputs (y, z) from the output terminals y, z of the matrix switch 23.
An access address to the address generator 03 is generated and output to the selector 107. The configuration of the address generation circuit 21 is the same as that of the address generation circuit 18.

The address controller 20 has a counter 1
2, 25 count output and address generation circuits 18, 2
1 is connected, and normally, control is performed so that the count value of the counter 12 does not match the count value of the counter 25. That is, when the values of both counters match, a busy signal (Busy) is output to the RAM controller 17, and the writing operation to the RAM 1703 is stopped. When the reading operation from the RAM 1703 proceeds and the counter 25 counts up, the busy signal is released and the writing is restarted. On the other hand, the address generation circuit 21
Becomes the final address of the buffer, a busy signal (B) is sent to the motor driver 1707 via the output terminal 29.
usy), and instructs to wait just before the next scanning operation of the carriage HC. At this time, even if the count values of the counter 12 and the counter 25 match, the RAM
No busy signal is output to the controller 17. Next, when the output of the address generation circuit 18 becomes the final address of the buffer, the busy signal to the motor driver 1707 is released, and an instruction is issued to start the next scanning operation by the carriage HC. The up / down (U / D) counters 13 to 14 are reset or loaded with initial values to switch the mode.

When the input / output address control to the buffer secured in the RAM 1703 described above is realized by software, the counters 12 to 14, 25 to 2
7. Instead of the address generation circuits 18 and 21, an initial value set in each counter is set in a predetermined area of the RAM 1703, and an increment is cumulatively added or subtracted from the initial value to generate an address. Is also good. When the address generation circuits 18 and 21 are configured by LUTs, the same address is always accessed in areas other than the area where the image data is stored, and "0" is stored in advance in the corresponding address of the RAM 1703. good.

Since the address generating circuits 18 and 21 and the matrix switches 16 and 23 are the same circuit, a selector is provided in front of the matrix switches 16 and 23 instead of the selector 107, and the selector is provided in accordance with the write and read modes. By selecting the output of each counter in this way, the address generation circuits 18 and 21 and the matrix switches 16 and 23 may be shared for writing and reading.

Next, a bidirectional H using the apparatus having the above configuration is described.
The V conversion process will be described with reference to a conceptual diagram of bidirectional HV conversion shown in FIG. 4 and a flowchart shown in FIG.

Here, it is assumed that the above-mentioned one buffer is accessed and used while switching between two modes (mode A and mode B) to perform a recording operation for one page of recording paper. In mode A, as shown in FIGS. 4A and 4C, input image data arranged in the scanning direction of the recording head IJH is sequentially written to the buffer line by line, and the M word interval is set in the buffer length direction. Is an access mode for reading data word by word. On the other hand, the mode B refers to the recording head IJH as shown in FIG.
The input image data for one line arranged in the scanning direction of
Divide by word length, N words in the buffer length direction
This is an access mode in which data is written in the buffer width direction by the number of lines and data is sequentially read in N-word units in the buffer width direction.

In mode A, the image data is read from the buffer in accordance with the backward scan (direction of arrow b in FIG. 1) of the normal print head IJH to execute the printing operation, and the image data is read for the next forward scanning. This is the access mode for writing to the buffer. On the other hand, the mode B is the recording head I
This is an access mode in which image data is read from a buffer in accordance with a forward scan of JH, a printing operation is performed, and image data is written in the buffer for a printing operation in the next backward scan.

First, in step S10, circuits and buffers are initialized. As a result, all data in the buffer is cleared and all become "0". Next, in step S15, the mode is set to mode A, and FIG.
As shown in (a), image data for N lines is written. At this point, the data is not read.

Next, in step S20, the mode is switched from mode A to mode B.
As shown in (b), in step S25, image data of N lines (buffer width direction) × 1 word (buffer length direction) is read from the buffer, and the bit plane circuit 1
The image data is output through step S11, and the recording operation is performed by the recording head IJH during forward scanning. On the other hand, when image data of one line (N × M) or more is read, in step S30, the area where the reading is completed is
As shown in (b), the image data for one line is N × M
Is written in the form of a block. This writing operation is performed so that the pixels of the image data are arranged in the data reading order at the time of the backward scanning in consideration of the printing operation by the backward scanning of the recording head IJH.

Further, in step S35, the reading operation of all the image data stored in the buffer before the mode is switched and the recording operation related thereto, and the entire area (H words × N lines) of the buffer after the mode is switched. ) Is checked to see if the image data writing operation has been completed. Here, if it is determined that all of these operations have not been completed, the process returns to step S25, and if it is determined that they have been completed, the process proceeds to step S40, and it is determined whether or not the recording operation has been completed. . If it is determined in step S40 that the recording operation is to be ended,
The process ends, but if it is determined that the recording operation should be continued, the process proceeds to step S45, and the mode is switched from mode B to mode A. Since these processes involve data input / output to and from the same buffer and a recording operation by moving the recording head IJH, steps S25 and S3 are performed.
The processing of 0 is synchronized. Therefore, even if the writing operation is completed but the recording operation is not completed, the next reading operation may be interrupted.

Now, when the mode is switched to the A mode,
In step S50, as shown in FIG. 4C, data is read out one word at a time at M word intervals,
Outputs image data through the bit plane circuit 111,
The recording operation at the time of backward scanning is performed by the recording head IJH. On the other hand, when image data of one line (N × M) or more is read, in step S55, one line of image data is written in the area where the reading has been completed, as shown in FIG. 4C. This writing operation is performed so that the pixels of the image data are arranged in the data reading order at the time of the forward scan in consideration of the print operation by the forward scan of the print head IJH.

Further, in step S60, the reading operation of all the image data stored in the buffer before the mode is switched and the recording operation related thereto, and the entire area (H words × N lines) of the buffer after the mode is switched. ) Is checked to see if the image data writing operation has been completed. Here, if it is determined that all of these operations have not been completed, the process returns to step S50, and if it is determined that they have been completed, the process proceeds to step S65.

The processing in steps S50 and S55 is as follows.
As in the processes in steps S25 and S30, data input / output to the same buffer and a recording operation by moving the recording head IJH are involved, so that these processes are synchronized. Therefore, even if the writing operation is completed but the recording operation is not completed, the next reading operation may be interrupted.

In step S65, it is determined whether the printing operation for one page has been completed. Here, if it is determined that the operation has not been completed, the process returns to step S20,
The mode is switched and the process is executed. If it is determined that the operation is completed, the process is completed.

Normally, various printing control times are required from the end of the printing operation for one scan by the print head IJH to the start of printing of the next scan. The interruption of the recording operation hardly occurs.
If the interface circuit 15 has a FIFO buffer for one line or more of image data,
Even if the weight for the line is applied, the host computer is hardly kept waiting.

As described above, according to this embodiment, a mode for storing one line of image data in a line and a mode for storing the image data in a block of M words × N lines are provided. Are alternately switched to change the manner of writing and reading data, thereby performing a smooth recording operation while performing bidirectional HV conversion using one buffer.

[0071]

Other Embodiments The present invention is not limited by the configuration of the bidirectional HV conversion circuit described above. For example,
A bidirectional HV conversion circuit having another configuration can be used.
Hereinafter, four embodiments of the configuration of the bidirectional HV conversion circuit will be described with reference to FIGS. In addition,
In these figures, the same components as those described in FIGS. 3 and 12 are denoted by the same reference numerals, and description thereof will be omitted. Here, regarding each embodiment, only the characteristic portions will be described.

(Second Embodiment) FIG. 6 is a block diagram showing a configuration of a bidirectional HV conversion circuit according to a second embodiment.

In FIG. 6, 31 is a counter that outputs a carry signal (Carry) when the count value is incremented N times, 32 is a counter that outputs a carry signal (Carry) when the count value is incremented 33, 33 Is an address generation circuit.

In the circuit shown in FIG. 6, the count values of the counters 12, 31 and 32 are reset by a reset signal from the address controller 20 when the mode (mode A, mode B) is switched. The counter 32 counts M times from "0" to "M-1" by the enable signal (EN) of the RAM controller 17, and when the count value is "M-1," the enable signal (EN) is input. And carry signal (C
arry) is output to the counter 31, and the counter 31 is counted up.

In response, the counter 31 sets the counter 3
2 is counted N times from “0” to “N−1” by the carry signal (Carry) from “2”, and the count value becomes “N”.
When the carry signal (Carry) is input at -1 ", the carry signal (Carry) is output to the counter 12, and
The counter 12 is counted up.

The count values of the counters 12 and 31 pass through the matrix switch 16 and the address generation circuit 3
3 is output. The matrix switch 16 exchanges the count values of the counter 12 and the counter 31 for each mode and outputs the result. For example, in the mode B, the count value of the counter 31 is output from the output terminal y, and the count value of the counter 12 is output from the output terminal z. In the mode A, the count value of the counter 31 is output from the output terminal z. , Output terminal y
Outputs the count value of the counter 12.

Now, the address generation circuit 33 has the counter 3
An access address to the RAM 1703 is generated from the count value (x) of 2 and the output (y, z) from the matrix switch 16, and this is output to the selector 107 and the address controller 20. Here, if the head address of the buffer is A0, the generated address Adr is as shown in equation (2) in mode A and as shown in equation (3) in mode B.

Adr = x + Hy + Mz + A0 (2) Adr = −x−Hy + Mz + A0 + H (N−1) + M−1 (3) That is, in the mode B, the term of the buffer head address A0 in the mode A is A0 + H (N−1). + M-1 and the addition of the first and second terms may be replaced by subtraction. Alternatively, the first (in equation (2)) in mode A
Term and the second term are inverted and added (one's complement addition)
A0 + HN + M may be added instead of 0 + H (N-1) + M-1.

The matrix switch 16 may be connected so that the input / output relationship is always through, and the matrix switch 16 may be omitted. In this case, Expression (2) for obtaining the address Adr in Mode A is changed to Expression (4).

Adr = x + Hz + My + A0 (4) In this case, the address Adr in the mode B is given by the equation (3)
Is required.

Similarly, the input / output relationship of the matrix switches 16 may be connected so that they always cross each other, and the matrix switches 16 may be omitted. In this case, the equation (3) for obtaining the address Adr in the mode B is changed to the equation (5).

Adr = −x−Hz + My + A0 + H (N−1) + M−1 (5) In this case, the address Adr in the mode A is expressed by the equation (2)
Is required.

Therefore, according to the configuration described above, the operation of the address generation circuit is switched in accordance with the mode, so that the up-down count described in the above embodiment is not required, and the configuration of the counter is simplified. There is.

(Third Embodiment) FIG. 7 is a block diagram showing a configuration of a bidirectional HV conversion circuit according to a third embodiment.

In FIG. 7, reference numeral 34 denotes an up / down (U / D) counter which outputs a carry signal (Carry) when the count value is incremented (or decremented) M times.

In the circuit shown in FIG.
5, 27 and 32 are modes (mode A, mode B)
Are reset by the reset signal of the address controller 20 at the time of switching. On the other hand, up-down (U /
D) The counter 13 and the up / down (U / D) counter 34 are respectively switched when the mode B is switched to the mode A.
"0" and "M-1" are loaded, and at the time of switching from mode A to mode B, "N-1" and "0" are reset by the reset (load) signal of the address controller 20, respectively.
Is loaded. The counter 32 is set to “0” by the enable signal (EN) from the RAM controller 17.
To "M-1", and when the enable signal (EN) is input when the count value is "M-1", the carry signal (Carry) is up / down (U / D).
It outputs to the counter 13 and counts up the up / down (U / D) counter 13 in the mode A, or counts down in the mode B.

The counter 27 changes from “0” to “N−” by the enable signal (EN) of the RAM controller 17.
Count N times up to 1 ", and the count value is" N-1 "
When the enable signal (EN) is input at the time of (1), the carry signal (Carry) is up-down (U / D) counter 3.
4 and up / down (U / D) in mode A
The counter 34 counts down, or counts up in the mode B. In response to this, the up / down (U / D) counter 34 counts down M times from “M−1” to “0” in mode A according to the carry signal (Carry) from the counter 27, and the count value becomes “0”. When the carry signal (Carry) is input when "", the carry signal (Carry) is output to the counter 25, and the counter 25 is counted up. In mode B, the up / down (U / D) counter 34 counts up M times from “0” to “M−1”, and when the count value is “M−1”, a carry signal (Carry) is input. Then, a carry signal (Carry) is output to the counter 25, and the counter 25 is counted up.

FIG. 8 is a diagram showing the operation of the bidirectional HV conversion circuit shown in FIG.

First, at the beginning of the recording operation, the mode is set to mode A, and image data for N lines is written as shown in FIG. At this point, the data is not read. Next, the mode is switched from mode A to mode B. Further, as shown in FIG. 8B, image data for N lines (buffer width direction) × 1 word (buffer length direction) is read from the buffer, and The image data is output through the plane circuit 111, and the recording head IJH performs a recording operation in the forward scan direction. On the other hand, when image data for one line (N × M) or more is read, the area where the reading has been completed is displayed in FIG.
As shown in (b), one line of image data is written in an N × M block in consideration of data reading in the next printing operation in the backward scanning direction.

Further, the reading operation of all the image data stored in the buffer before the mode is switched and the recording operation related thereto, and the image to the entire area (H words × N lines) of the buffer after the mode is switched. After synchronizing the data write operation, the mode is switched from mode B to mode A. Note that the synchronous processing of these operations involves data input / output to / from the same buffer and a recording operation by moving the recording head IJH. Therefore, even if writing is completed, if the recording operation is not completed, the next read operation is performed. However, the operation may be interrupted.

Now, when the mode is switched to mode A,
As shown in FIG. 8C, data is read out at M word intervals, image data is output via the bit plane circuit 111, and the recording head IJH performs a recording operation in the backward scanning direction. On the other hand, when the image data of one line (N × M) or more is read, the image data of one line is written in the area where the reading is completed, as shown in FIG. 8C. Further, the reading operation of all the image data stored in the buffer before the mode is switched and the recording operation related thereto, and the writing of the image data to the entire area (H words × N lines) of the buffer after the mode is switched. After the operation is synchronized, the mode is changed to mode A again.
To mode B. Note that the synchronous processing of these operations involves data input / output to and from the same buffer and a recording operation by moving the recording head IJH, as in the recording operation in the forward scan direction, so that these processes are synchronized. Therefore, even if the writing operation is completed but the recording operation is not completed, the next reading operation may be interrupted.

Thereafter, the image data input / output operation described above (FIGS. 8B and 8C) is executed until all the image data is recorded on the recording paper.

Therefore, according to the configuration as described above, a mode for storing one line of image data in a line and a mode for storing in a block of M words × N lines are provided. By alternately changing the way of writing and reading data, it is possible to perform processing as if using a double buffer while using one buffer, and to perform smooth bidirectional HV conversion. A recording operation can be performed.

Note that the present invention is not limited by the configuration of the counter described in this embodiment. For example, the same effect can be obtained with a counter configuration as shown in Table 1.

[0095]

[Table 1]

(Fourth Embodiment) FIG. 9 is a block diagram showing a configuration of a bidirectional HV conversion circuit according to a fourth embodiment. In FIG. 9, reference numerals 35 to 36 denote address generation circuits.

In the circuit shown in FIG.
5 generates a write address of the RAM 1703 from the count value (x) of the counter 32 and the output (y, z) of the matrix switch 16, and outputs this to the selector 107 and the address controller 20. Here, assuming that the head address of the buffer is A0, the generated address A
dr is represented by equation (6) in mode A, and by equation (7) in mode B.

Adr = x + Hy + Mz + A0 (6) Adr = x−Hy + Mz + A0 + H (N−1) (7) That is, in the case of the mode B, the equation (6), that is, the term A0 of the head address in the mode A is A0 + H (N−1). Equation (6)
May be replaced by subtraction. Alternatively, the second term on the right side of equation (6) is inverted and added (one's complement addition)
Alternatively, A0 + HN may be added instead of A0 + H (N-1).

The matrix switches 16 may be connected so that the input / output relationship is always through, and the matrix switches 16 may be omitted. In this case, for the address calculation in mode B, y and z in equation (6) may be exchanged. Similarly, the matrix switches 16 may be connected such that the input / output relationship always crosses, and the matrix switches 16 may be omitted. In this case, for the address calculation in mode A, y and z in equation (7) may be exchanged.

On the other hand, the address generation circuit 36
A read address of the RAM 1703 is generated from the count value (x) of 6 and the output (y, z) of the matrix switch 23, and is output to the selector 107 and the address controller 20. Here, if the head address of the buffer is A0, the generated address Adr is the mode A
Is expressed by equation (8), and in mode B is expressed by equation (9).

Adr = −x + Hy + Mz + A0 + M−1 (8) Adr = x + Hy + Mz + A0 (9) That is, in the address calculation in the mode A, the first address term A0 in the equation (9) is added to A0 + M−1 and the first term on the right side is added. Can be replaced by subtraction. Alternatively, the first term on the right side of Expression (9) is inverted and added (one's complement addition), and A0 + M-1
Alternatively, A0 + M may be added.

The matrix switches 23 may be connected so that the input / output relationship is always through, and the matrix switches 23 may be omitted. In this case, the address calculation in the mode B may be performed by exchanging y and z in Expression (8). Similarly, when the matrix switch 23 is connected so that the input / output relationship always crosses, and the matrix switch 23 is omitted, the address calculation in the mode A may be performed by exchanging y and z in Expression (9).

Therefore, according to the configuration as described above, the operation of the address generation circuit is switched according to the mode, so that an up / down counter is not required and the configuration of the counter is simplified.

It is also possible to configure address generation circuits 35 and 36 corresponding to each of the counter configurations shown in Table 1.

(Fifth Embodiment) FIG. 10 is a block diagram showing a configuration of a bidirectional HV conversion circuit according to a fifth embodiment.

In FIG. 10, 37 to 39, 45 to 47
Is a selector, 40 and 44 are adders, 41 and 43 are registers, 42 is an address controller, and 51 is a RAM controller. Here, the number of data of one line in the buffer of the RAM 1703 is Hm.

The selectors 37 to 39 are controlled by the address controller 42, and the next address increment is output from the selector 39. The adder 40 adds the increment to the address of the previous data held in the register 41 to generate the address of the next data. According to the load signal (Load) from the address controller 42, the register 41 loads the buffer top address $ 0 when switching from mode B to mode A, and switches from mode A to mode B.
A0 + Hm (N-1) + M-1 is loaded when switching to. Next, when the image data is stored in the RAM 1703, according to a control signal from the RAM controller 51,
The register value is added to the output of the adder 40.

When the selector 39 is in the mode A, the selector 3
7, the selector 37 outputs the value of (Hm-H) at the end of each line, and otherwise outputs "1". Therefore, the output of the register 41 is $ 0 at the beginning of the mode A, increases by one from the data of the next pixel to the end of one line, and becomes $ 0 + Hm at the head of the next line. Therefore, the image data is stored in the RAM 1703 in the order as shown in FIG.

Similarly, in mode B, the selector 39 selects the output of the selector 38, and the selector 38 outputs (N-1) · Hm + M at the end of each line, and −Hm for every M words.
The value of + M-1 is output, otherwise "-1" is output.
Therefore, the output of register 41 is A at the beginning of mode B.
0 + Hm (N−1) + M−1, and (M−
Since it is decreased by 1 until 1) and is decreased by Hm-M + 1 at the Mth word, this becomes the (M-1) th address in the buffer of the RAM 1703. Such an addressing sequence continues to the end of one line. The data of the last pixel on one line is stored in RAM1.
703, the address value is (N-1).
Hm + M is increased to A0 + Hm (N-1) + 2M-1. Therefore, the image data is stored in the RAM 1703 in the order as shown in FIG.

On the other hand, on the read side, the selector 4
5 to 47 are controlled by the address controller 42;
The next address increment is output from the selector 45. The adder 44 adds the increment to the address of the previous data held in the register 43 to generate the address of the next data. In accordance with a load signal (Load) from the address controller 42, the register 43 loads the head address $ 0 of the buffer when the mode is switched. Next, when the image data is read from the RAM 1703, R
In accordance with a control signal from the AM controller 51, the register value is updated to the output of the adder 44.

In the mode B, the selector 45 selects the output of the selector 47. The selector 47 outputs − (N−1) · Hm + 1 every N words, and outputs Hm otherwise. Therefore, the output of the register 43 is $ 0 at the beginning of the mode B, and Hm from the data of the next pixel to (N-1).
The scanning is performed in the buffer width direction because the number increases in increments. Then, since − (N−1) · Hm + 1 is added at the Nth word, a data address (Α0 + 1) of the pixel next to the first line of the buffer of the RAM 1703 is generated. Accordingly, the image data is read from the RAM 1703 in the order as shown in FIG.

Similarly, in the mode B, the selector 47 selects the output of the selector 46. The selector 46 outputs (Hm−H) at the end of each line, −H + M + 1 every N, and outputs M otherwise. Accordingly, in the register 43, the register value is added to $ 0 at the beginning of the mode B, M at a time from the next pixel data to N-1, and -H + at the Nth pixel.
Since M + 1 is added, the address of the next data of the head line of the buffer of the RAM 1703 becomes ($ 0 + 1). This addressing sequence continues until the end of one line. And the last data of one line is R
When read from the AM 1703, (Hm-H) is added to the register value, and becomes the start address Hm of the next line in the buffer of the RAM 1703. Accordingly, the image data is read from the RAM 1703 in the order shown in FIG.

Therefore, according to the configuration described above, address control can be performed by a combination of a register, an adder, and a selector. Thus, the difference from the address of the previous pixel is selected and accumulated and added, whereby the number of data Hm of one line on the buffer memory is obtained.
There is an advantage that processing can be easily performed even if the number of words H in one line of the input image is different.

By changing the initial values of the registers 41 and 43 and the inputs of the selectors 37 to 38 and 46 to 47, it is possible to generate addresses corresponding to Table 1. Table 2
The specific numerical values are shown in FIG.

[0115]

[Table 2]

The above-described embodiment is particularly provided with a means (for example, an electrothermal converter or a laser beam) for generating thermal energy as energy used for performing ink ejection even in an ink jet recording system. By using a method in which a change in the state of the ink is caused by energy, it is possible to achieve higher density and higher definition of recording.

The typical configuration and principle are described in, for example, US Pat. Nos. 4,723,129 and 4,740.
It is preferable to use the basic principle disclosed in the specification of Japanese Patent No. 796. This method can be applied to both the so-called on-demand type and continuous type. In particular, in the case of the on-demand type, liquid (ink)
By applying at least one drive signal corresponding to the recorded information and providing a rapid temperature rise exceeding the film boiling to the electrothermal transducer arranged corresponding to the sheet or the liquid path holding the Since thermal energy is generated in the electrothermal transducer and film boiling occurs on the heat-acting surface of the recording head, bubbles in the liquid (ink) corresponding to this drive signal on a one-to-one basis can be formed. It is valid. By discharging the liquid (ink) through the discharge opening by the growth and contraction of the bubble, at least one droplet is formed. When the drive signal is formed into a pulse shape, the growth and shrinkage of the bubble are performed immediately and appropriately, so that the ejection of the liquid (ink) having particularly excellent responsiveness can be achieved, which is more preferable.

As the pulse-shaped driving signal, those described in US Pat. Nos. 4,463,359 and 4,345,262 are suitable. Further, if the conditions described in US Pat. No. 4,313,124 relating to the temperature rise rate of the heat acting surface are adopted, more excellent recording can be performed.

As the configuration of the recording head, in addition to the combination of the discharge port, the liquid path, and the electrothermal converter (linear liquid flow path or right-angle liquid flow path) as disclosed in the above-mentioned respective specifications, A configuration using U.S. Pat. No. 4,558,333 or U.S. Pat. No. 4,459,600, which discloses a configuration in which a heat acting surface is arranged in a bent region, is also included in the present invention. In addition, for multiple electrothermal transducers,
JP-A-59-123670 which discloses a configuration in which a common slot is used as a discharge part of an electrothermal transducer, and JP-A-59-123670 which discloses a configuration in which an opening for absorbing a pressure wave of thermal energy corresponds to a discharge part. A configuration based on 138461 may be adopted.

Further, as a full-line type recording head having a length corresponding to the width of the maximum recording medium that can be recorded by the recording apparatus, the length is determined by combining a plurality of recording heads as disclosed in the above specification. This may be either a configuration satisfying the above requirements or a configuration as a single recording head formed integrally.

In addition to the cartridge type recording head in which an ink tank is provided integrally with the recording head itself described in the above embodiment, the recording head is electrically connected to the apparatus main body by being mounted on the apparatus main body. A replaceable chip-type recording head, which enables a simple connection and supply of ink from the apparatus main body, may be used.

It is preferable to add recovery means for the printhead, preliminary auxiliary means, and the like to the configuration of the printing apparatus described above, since the printing operation can be further stabilized. Specific examples thereof include capping means for the recording head, cleaning means, pressurizing or suction means, preheating means using an electrothermal transducer or another heating element or a combination thereof. It is also effective to provide a preliminary ejection mode for performing ejection that is different from printing, in order to perform stable printing.

Further, the recording mode of the recording apparatus is not limited to the recording mode of only the mainstream color such as black, and may be a single recording head or a combination of plural recording heads. Alternatively, the apparatus may be provided with at least one of full colors by color mixture.

In the embodiment described above, the description is made on the assumption that the ink is a liquid. However, even if the ink solidifies at room temperature or lower, it is possible to use an ink that softens or liquefies at room temperature. Or, in the ink jet method, generally, the temperature of the ink itself is controlled within a range of 30 ° C. or more and 70 ° C. or less to control the temperature so that the viscosity of the ink is in a stable ejection range.
It is sufficient that the ink is in a liquid state when the use recording signal is applied.

In addition, in order to positively prevent the temperature rise due to thermal energy as energy for changing the state of the ink from the solid state to the liquid state, the temperature is positively prevented.
Alternatively, in order to prevent evaporation of the ink, an ink which solidifies in a standing state and liquefies by heating may be used. In any case, the application of heat energy causes the ink to be liquefied by the application of the heat energy recording signal and the liquid ink to be ejected, or by the time the ink reaches the recording medium, the solidification of the ink already begun. The present invention is also applicable to a case where an ink having a property of liquefying for the first time is used. In such a case, as described in JP-A-54-56847 or JP-A-60-71260, the ink is held in a liquid state or a solid state in the concave portion or through hole of the porous sheet. It is good also as a form which opposes an electrothermal transducer. In the present invention, the most effective one for each of the above-mentioned inks is to execute the above-mentioned film boiling method.

In addition to the above, the recording apparatus according to the present invention may be provided not only as an image output terminal of an information processing apparatus such as a computer but also integrally or separately, a copying apparatus combined with a reader, etc. It may take the form of a facsimile machine having functions.

Even if the present invention is applied to a system including a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), an apparatus (for example, a copying machine, a facsimile machine, etc.) Device). Further, an object of the present invention is to provide a storage medium storing a program code of software for realizing the functions of the above-described embodiments to a system or an apparatus, and a computer (or CPU or MPU) of the system or apparatus to store the storage medium. Needless to say, this can also be achieved by reading and executing the program code stored in the program.

In this case, the program code itself read from the storage medium implements the functions of the above-described embodiment, and the storage medium storing the program code constitutes the present invention. Examples of a storage medium for supplying the program code include a floppy disk, hard disk, optical disk, magneto-optical disk, and C
A D-ROM, a CD-R, a magnetic tape, a nonvolatile memory card, a ROM, and the like can be used.

[0129]

As described above, according to the present invention, H
Each time data input / output of a capacity corresponding to the buffer is used using only a data buffer for storing image data for pixels × L lines, the input / output method for the data buffer is determined by two access methods. By switching between the two, a bidirectional HV similar to the conventional double buffer system can be used.
Conversion can be performed.

As a result, bidirectional HV conversion with a smaller buffer capacity is realized, which can contribute to cost reduction and circuit miniaturization.

[0131]

[Brief description of the drawings]

FIG. 1 is an external perspective view showing an outline of a configuration of an ink jet printer IJRA which is a typical embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a control circuit of the inkjet printer IJRA.

FIG. 3 is a block diagram illustrating a detailed configuration of a bidirectional HV conversion circuit.

FIG. 4 is a diagram showing how the bidirectional HV conversion circuit shown in FIG. 3 accesses a buffer.

FIG. 5 is a flowchart illustrating a bidirectional HV conversion process.

FIG. 6 is a block diagram showing a configuration of a bidirectional HV conversion circuit according to a second embodiment.

FIG. 7 is a block diagram showing a configuration of a bidirectional HV conversion circuit according to a third embodiment.

FIG. 8 is a diagram showing a state of buffer access of the circuit shown in FIG. 7;

FIG. 9 is a block diagram showing a configuration of a bidirectional HV conversion circuit according to a fourth embodiment.

FIG. 10 is a block diagram showing a configuration of a bidirectional HV conversion circuit according to a fifth embodiment.

FIG. 11 is a diagram illustrating a state of buffer access in the HV conversion process of the double buffer system.

FIG. 12 is a block diagram showing a configuration of a conventional bidirectional HV conversion circuit.

[Description of Signs] 12, 25-27, 31-32 Counters 13-14, 34 Up / Down (U / D) Counter 16, 23 Matrix Switch 17 RAM Controller 18, 21, 33, 35, 36 Address Generation Circuit 20 Address Controllers 37 to 39, 45 to 47 Selectors 40, 44 Adders 41, 43 Registers 42 Address controllers 51 RAM controllers 103 Interface circuits 107 Selectors 111 Bitmap readout circuits 1703 RAM

Claims (11)

[Claims] 1. A data buffer having a length of H pixels in a first direction and L lines in a second direction and storing image data of H pixels × L lines is used. A recording apparatus that performs recording on a recording medium during both a forward movement and a backward movement of the reciprocating movement while reciprocating a recording head having a plurality of recording elements arranged in the first direction. Input means for inputting image data in which pixels are arranged in a first direction; initial writing means for storing L lines of image data in the data buffer by H pixels along the first direction; A first reading unit that reads the image data by a predetermined number of pixels in the first direction from the data buffer in the second direction at a time of a recording operation by moving the head in the first direction; By reading means In the read area of the data buffer, image data for the predetermined number of pixels is stored in the data buffer by the predetermined number of pixels along the first direction for the recording operation by the backward movement of the recording head. A first writing unit, a second reading unit that reads the image data from the data buffer at the predetermined number of pixels along the first direction during a printing operation by the return movement of the printing head; A second writing unit that stores the image data in the data buffer by one line along the first direction for the recording operation by the next forward movement of the recording head; and the first reading and writing. Switching means for switching between a first mode for operating the writing means and a second mode for operating the second reading and writing means; and switching between forward movement and backward movement of the recording head. A recording apparatus comprising: a switching control unit that controls the switching unit so as to switch between the first mode and the second mode every time the switching is performed. 2. In the first mode, the first read and write operations are performed until the read operation by the first read means and the write operation by the first write means are completed with respect to the entire area of the data buffer. First control means for controlling the first read and write means so as to repeat the operation by the read means, and in the second mode, the read operation by the second read means and the second operation for the entire area of the data buffer.
And a second control means for controlling the second reading and writing means so as to repeat the operation by the second reading and writing means until the writing operation by the writing means is completed. The recording device according to claim 1. 3. The recording apparatus according to claim 2, further comprising a conveying unit that conveys the recording medium in the second direction. 4. A third control for controlling the operations of the first read, write, control, and second read, write, and control means to be repeated until input / output processing of a predetermined amount of image data is completed. 3. The method according to claim 2, further comprising:
The recording device according to claim 1. 5. A plurality of counters are used for determining an address for accessing said data buffer by said first read / write means and said second read / write means. The recording device according to claim 1. 6. The image processing apparatus according to claim 4, further comprising a first difference output unit that outputs a difference between a write address of the previous image data and a write address of the current image data, and generates a write address of the current image data from the difference. The recording device according to claim 1. 7. The image processing apparatus according to claim 6, further comprising a second difference output unit that outputs a difference between a read address of the previous image data and a read address of the current image data, and generates a read address of the current image data from the difference. The recording device according to claim 1. 8. The apparatus according to claim 4, wherein said first and second writing means include a counter for counting up or down the number of pixels for writing image data.
The recording device according to claim 1. 9. The recording apparatus according to claim 4, wherein said first and second reading means include a counter for counting up or counting down the number of pixels read out of image data. 10. The recording apparatus according to claim 1, wherein the recording head is an inkjet recording head that performs recording by discharging ink. 11. The recording head, which ejects ink by using thermal energy, includes a thermal energy converter for generating thermal energy to be applied to the ink. Item 2. The recording device according to Item 1.