JPH11103328A - Digital signal converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent deterioration in sound quality, to suppress large-sized configuration and to reduce the cost in the case of converting a digital audio signal with a format in compliance with a signal transmission standard into a digital audio signal with a format in compliance with other signal transmission standard. SOLUTION: The converter converts a digital audio signal with a DV format in compliance with the IEEE 1394 into a digital audio signal with a format of the IEC 958 standard, and is provided with a 1st oscillation circuit 11 for the 1394 audio signal, a 2nd oscillation circuit 26 for the 958 audio signal, a sample rate converter 4 that converts the 1394 audio signal into the 958 audio signal based on clock signals from the 1st oscillation circuit 11 and the 2nd oscillation circuit 26, a microcomputer 12 that converts the format of the digital audio signal subject to sampling rate conversion into the 958 audio signal and a signal processing circuit 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal converter for converting a digital signal of a certain signal transmission standard into a digital signal of another signal transmission standard.

[0002]

2. Description of the Related Art Digital signal transmission standards include, for example, IEC (International Electrotechnical Communication).
ion: International Electrotechnical Standards Institution (IEEE) and IEEE (Institute o
f There are many standards, including those from the Electrical and Electronics Engineers Association. Among them, for example, IEEE 1394 has attracted attention as being suitable for multimedia applications such as connection between digital video recorders and connection between a digital video camera and a computer.

[0003] The IEEE 1394 standard will be described. In the following description, the IEEE 1394 standard is simply called the 1394 standard.

[0004] In the 1394 standard, transmission is performed using two twisted pair wires. The transmission method is a so-called half-duplex communication in which two pairs of twisted pair wires are used for one-way transmission. This communication method employs a communication method called DS coding. In this method, a clock is reproduced on the receiving side by sending data to one side of a twisted pair line and sending a signal called a strobe to the other side, and taking an exclusive OR of the two signals.

[0005] The data rate of the 1394 standard is 98.3.
04Mbps (S100), 196.608Mbps
(S200) and 393.216 Mbps (S400) are defined, and so-called upward compatibility is defined, in which a device corresponding to a high-speed rate must support a device at a lower rate.

Each device is allowed to have up to 26 ports, and up to 63 devices can be networked by connecting the ports of each device. According to the 1394 standard, a bus initialization process is performed at the time of connection, and when a plurality of devices are connected, a tree structure is automatically configured internally. After that, the addresses of the respective devices are automatically allocated.

[0007] According to the 1394 standard, a signal transmitted by one device is relayed by another device, so that a signal having the same content can be transmitted to all devices in the network. Therefore, in order to prevent disorderly transmission and reception, each device needs to arbitrate the right to use the bus before starting transmission. In order to obtain the right to use the bus, first, it waits for the bus to be released, and sends a bus use right request signal to the parent device on the tree. Then, the master unit that has received the request relays the signal to a further master unit, and the request signal eventually reaches the route that is the highest-order master unit. When the route receives the request signal, the route returns a use permission signal, and the permitted device can perform communication. However, at this time, when a request signal is issued from a plurality of devices at the same time, a permission signal is given to only one device, and other requests are rejected.

As described above, according to the 1394 standard, it can be said that a plurality of devices use one bus by time division multiplexing while competing for the right to use the bus. However, for data that requires real-time properties, such as video signals and audio signals, data loss may occur if communication is not guaranteed at regular time intervals. So 13
The 94 standard defines such data as Isochronos (Isocnos).
Transmission is performed using a communication method called hronous). That is, a management node is selected at the time of the above-mentioned bus initialization, and a device transmitting by isochronous communication receives a necessary band allocation from the management node. Route is 125 μs
Each time a cycle start packet is transmitted, the device to which the band is allocated transmits an isochronous packet following the cycle start packet. By performing such a process, the device to which the band has been allocated is 125 μs
An opportunity to transmit data can be obtained every time, and data loss can be prevented.

In the following description, a signal format used when a digital video recorder sends digital video and digital audio signals using the 1394 standard isochronous communication will be referred to as, for example, an AV protocol. In this signal format, a video signal (for example, a compressed video signal) and an audio signal on a video tape are handled as a group of 80-byte block data called a DIF block.

525/60 of the standard television broadcasting system
150DI for the system (so-called NTSC system)
A 1DIF sequence is composed of F blocks.
The DIF sequence is one video frame. Since one packet is transmitted every 125 μs in the isochronous communication, 29.97 × 10 × 1 per packet is transmitted.
It suffices to transmit 50 × 125 × 10−6 = 5.619 DIF blocks. In practice, the fraction is rounded up to make one 6 DIF block. As a result, data for one video frame is transmitted in 250 packets as shown in FIG.

FIG. 8 shows the structure of one isochronous packet. In FIG. 8, the first 32 bits of the packet are a packet header defined by the 1394 standard. The data portion after the header CRC and before the data CRC is a portion defined as a data field in the 1394 standard. At the beginning of this portion, a CIP for indicating information of an audio / video signal is transmitted. Is added in this AV protocol.

The SYT field of the CIP header is a time stamp for performing frame synchronization. In communication of a video signal, it is necessary to send a frame synchronization signal. Therefore, a time stamp using a cycle time defined in the 1394 standard is sent to the beginning of a video frame. The cycle time is a counter that counts 24.576 MHz, which is the basic clock of the 1394 standard. The route transmits its own count value in a cycle start packet. Each node copies it to its own cycle time to synchronize the cycle time.

When transmitting a video signal, a value obtained by adding the maximum delay amount of communication to the value of the cycle time at the beginning of the frame is put in the CIP header as SYT. This makes it possible to generate a frame synchronization signal delayed by the maximum delay by comparing the cycle time with the cycle time on the receiving side, as shown in FIG.

FIG. 10 shows an example of the configuration of a digital video recorder for recording / reproducing the 1394 standard digital audio / video signal and inputting / outputting it to / from an external device.

In FIG. 10, a video input / output terminal 1
00 and an audio input / output terminal 101 are terminals for inputting / outputting an analog video signal and an analog audio signal.

A / D converter, D / A converter 10
Numeral 2 digitizes an analog video signal input from the video input / output terminal 100 and conversely converts a digital video signal supplied from the video compression / expansion circuit 104 into an analog signal. An A / D converter and a D / A converter 103 digitize the analog audio signal input from the audio input / output terminal 101, and conversely, a digital signal supplied from an audio interleave / deinterleave circuit 105. The audio signal is converted into an analog signal.

The video compression / expansion circuit 104 performs a compression process on the digital video signal input from the A / D converter 102, and conversely, a compression digital signal supplied from a multiplexer / demultiplexer (MPX / DMPX) 106. The video signal is subjected to a decompression process.
Also, the audio interleave / deinterleave circuit 105 performs an interleave process on the digital audio signal input from the A / D converter 103, and conversely, a multiplexer / demultiplexer 106
The deinterleaving process is performed on the interleaved digital audio signal supplied from the CDMA.

Multiplexer / Demultiplexer 106
Multiplexes the compressed digital video signal from the video compression / decompression circuit 104 with the interleaved digital audio signal from the audio interleave / deinterleave circuit 105, and conversely,
When multiplexed data is supplied, a compressed digital video signal and an interleaved digital audio signal are separated (demultiplexed) from the multiplexed data.

Recording / playback signal processing (FEC) circuit 107
The multiplexed data is modulated by adding an error correction code to the multiplexed data, and then generates a recording signal and sends it to the magnetic head 108. Conversely, the reproduced signal reproduced from the magnetic tape by the magnetic head 108 is demodulated. And then perform error correction processing.

Digital interface block 10
Reference numeral 9 denotes a block for performing signal processing for an interface based on the 1394 standard with an external computer or another digital video recorder under the control of a control microcomputer (microcomputer) 110. Link (LI
The NK) circuit 111 performs the 1394 standard link layer and the AV protocol processing on the multiplexed data supplied from the multiplexer / demultiplexer 106 or the recording / reproducing signal processing circuit 107. Relay (PH
Y) The circuit 112 performs initialization of the bus, arbitration of the right to use, signal relay of other devices, and the like. The control microcomputer 110 controls the link circuit 111 and the relay circuit 112, acquires a band for isochronous communication, and manages a bus as a limited manager.

[0021]

By the way, the above 134
Conventionally, when there is a request to convert a digital audio signal among digital video and digital audio signals having a signal format conforming to the N.9 standard into a digital audio signal having a signal format conforming to another signal transmission standard, A digital audio signal having a signal format conforming to the 1349 standard is converted into an analog audio signal, and the analog audio signal is reconverted into a digital audio signal having a signal format conforming to the other standards.

In the following description, the other standard is IE
This will be described using the C958 standard as an example. After this,
The IEC958 standard will simply be referred to as the 958 standard.
A digital audio signal having a signal format conforming to the 1349 standard will be simply referred to as a 1349 audio signal, and a digital audio signal having a signal format conforming to the 958 standard will be hereinafter simply referred to as a 958 audio signal.

In any case, when converting the 1349 audio signal to the 958 audio signal, the 1349 audio signal is converted to an analog signal, and then the analog signal is digitized to form the 958 audio signal. Is done.

Here, a device for converting the 1394 audio signal to an analog signal and a device for converting an analog audio signal to a 958 audio signal have conventionally existed, and there is also a device integrating these devices. However, whichever device is used, the following problems occur because the digital audio signal is once converted into an analog audio signal and then converted again into a digital audio signal.

First, distortion (quantization distortion and the like), noise, and the like increase due to the characteristics of the quantizer and other converters, and the sound quality is degraded.

Second, since the D / A and A / D converters each have a variation in conversion sensitivity, overload distortion occurs, for example, in a signal at the maximum level (and a large level near the maximum level). There are cases. To prevent the occurrence of the overload distortion, it is necessary to adjust the level.
It is necessary to perform D conversion. However, in the former case, an arrangement for adjustment must be provided, which leads to an increase in the cost of the device, and in the latter case, the sound quality is deteriorated and the signal level is lowered.

In addition to the above-mentioned problems associated with the D / A and A / D conversion, the following problems also occur due to the standard features of the 1349 audio signal and the 958 audio signal.

That is, the 1394 audio signal and the 958 audio signal have a sampling frequency of 48 kHz, 44.1 kHz and 32 kHz, respectively.
There are various modes. For example, in the case of the above-mentioned 32 KHz mode, in a signal format conforming to the above-mentioned 1394 standard, in addition to normal monaural and stereo, four audio channels including two stereo S1 and stereo S2 systems, so-called While it is possible to transmit a 4-channel audio signal called 3-1 stereo, a signal format conforming to the 958 standard can transmit only up to two audio channels on one line. Note that 3-1 stereo is the left (L) of stereo
This is a system including a center channel and a surround channel in addition to a channel and a right (R) channel. In the case of a 1394 audio signal, 48 KHz and 4
The 4.1 KHz mode has 16 bits and 2 channels, and the 32 KHz mode has 12 bits and 4 channels and 16 bits and 2 channels.

As described above, when a 958 audio signal is generated from the 1394 audio signal in the 32 kHz mode, the 1394 audio signal is output from the stereo S1 and the stereo S2 audio 4 signals.
When it is composed of four channels, two audio channels obtained by converting the stereo S1 of the four audio channels into analog, two audio channels obtained by converting the stereo S2 into analog, and the stereo S1, S2
, After analog conversion, mixes and selects one of the two audio channels generated, and digitizes the audio 2 channel signal resulting from the switching and converts it to the 958 audio signal. Therefore, an analog mix circuit and an analog switching circuit are required. When the 1394 audio signal is a 3-1 stereo signal, the 3-1 stereo 4-channel digital audio signal is converted into an analog signal, and an audio 2 channel is generated from the digital audio signal by arithmetic processing. A process for converting to a 958 audio signal is required, and the circuit configuration becomes large.

Thus, 1349 audio signals and 9
Due to the standard features of the 58 audio signal, the sound quality deteriorates and the circuit configuration becomes complicated.

Therefore, the present invention has been made in view of such circumstances, and converts a digital audio signal having a signal format conforming to a certain signal transmission standard into a digital audio signal having a signal format conforming to another signal transmission standard. It is an object of the present invention to provide a digital signal converter capable of preventing sound quality deterioration when converting, and suppressing an increase in the size and cost of the device.

[0032]

A digital signal converter according to the present invention converts a digital signal of a first format conforming to a first signal transmission standard into a digital signal of a second format conforming to a second signal transmission standard. A first oscillating means for oscillating within a first allowable frequency deviation allowed for the digital signal of the first format and a digital signal of the second format. A second oscillating unit that oscillates within a second allowable frequency deviation, and a sampling rate of the first format digital signal based on a clock signal from the first and second oscillating units. Digital sample rate conversion means for converting the digital signal to a sampling rate of By having the format conversion means for converting the formats to the second format,
The above-mentioned problem is solved.

That is, according to the present invention, a digital signal in the first format is converted into a digital signal in the second format without converting it into an analog signal without being converted into an analog signal. Therefore, it is possible to prevent signal deterioration caused by the conversion.

[0034]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a specific configuration of the digital signal converter of the first embodiment, and FIG. 2 shows a specific configuration of the digital signal converter of the second embodiment.
In order to facilitate the understanding of the digital signal conversion operation of the present invention, prior to the description of the operation of the configuration of FIGS.
With reference to FIGS. 3 to 6, a brief description will be given of a signal transmission standard handled in the present embodiment and a signal format conforming thereto.

In this embodiment, for example, the above-mentioned IEEE 1394 standard and IEC 958 standard are taken as examples of the signal transmission standard, and a digital audio signal (1394 audio signal) of a signal format called a DV format conforming to the 1394 standard is converted to the above-mentioned 958. Digital audio signals (9
58 audio signal).

The 1394 audio signal is the same as that shown in FIG.
0 is a signal transmitted from the audio interleave / deinterleave circuit 105 to the multiplexer / demultiplexer 106, and its signal format is as shown in FIG.

That is, in FIG.
The four audio signals include a sync area, an ID code area, an audio auxiliary data (AAUX) area, an audio data area, an outer parity area, and an inner parity area. An actual digital audio signal is arranged in the audio data area.

As shown in FIG. 4, the digital audio signal in the audio data area has a sampling frequency of 525/60 system (NTSC system) and 625/50 system (PAL system) of the television standard broadcasting system. 48KHz, 44.1KH
There are four channel modes of z, 32 KHz, and 32 KHz. In each mode of each system,
An allowable range of the number of samples (bytes) per frame is defined, and an error of about 1% (that is, an allowable frequency deviation of the sampling frequency of about 1%) is allowed as the allowable range. For example, taking the 32 kHz 4 channel mode of the 525/60 system as an example, the number of samples (byte) per frame is as follows.
Maximum of 1080 samples (3240 bytes), minimum of 1
053 samples (3158 bytes), on average 1067.
There are 73 samples (3203.2 bytes).

The audio auxiliary data (AAU)
In the X) area, a plurality of auxiliary data are defined as shown in FIG. Since these data are already known as standards, only the auxiliary data related to the present embodiment among the auxiliary data will be briefly described. AF in the figure
In the area indicated by SIZE, information on the number of samples in one frame is arranged. In the area indicated by AUDIO MODE in the figure, information indicating the mode is arranged.
, Information indicating a sampling frequency in an area indicated by SMP in the figure, an emphasis flag in an area indicated by EF in the figure, and 3-1 in an area indicated by PA in the figure. In the area indicated by CGMS in which information indicating a channel is shown, information on copyright is allocated.

FIG. 6 shows the signal format of the 958 audio signal. Since this signal format is already known as a standard, the detailed description is omitted, but the area indicated by C in the figure is a channel status area, which includes information for controlling copyright, category code, and sampling. A frequency flag, an emphasis flag, and the like are provided.

In the digital signal converter of the present embodiment, 958 audio signals are converted to 958 by digital signal processing without analog conversion.
Converts digital signals to audio signals. That is,
In the digital signal converter according to the present embodiment, a 1394 audio signal having an allowable range of about 1% and a 0.1%
(That is, level 2: Normal accuracy mo)
Digital sampling rate conversion is performed to match both of the 958 audio signals, which must be within a range called "de". In addition, 1
From the audio 4 channels in the 32 kHz mode of the 394 audio signal, stereo S1 and stereo S
2. A process of selecting one of digital mixes (variable mix ratio) of the stereo S1 and S2 and converting the 958 audio signal into a 2-channel audio signal of one line or a digital signal of 1394 audio signal.
The digital signal is converted from four channels of one stereo to two channels of stereo to generate a two-channel audio signal of 958 audio signals per line.

First, the digital signal converter according to the first embodiment shown in FIG. 1 will be described. The first shown in FIG.
In the digital signal converter according to the embodiment, 13
A configuration for digital sample rate conversion from a 94 audio signal to a 958 audio signal will be described.
FIG. 1 shows an example corresponding to 48 kHz as the sampling frequency mode, and other modes will be described as necessary.

In FIG. 1, the 1394 audio signal input from the outside or the audio signal reproduced from the tape by the digital video recorder is supplied to a terminal 1, and a frame of 29.97 Hz is supplied to a terminal 10. A reference signal (a frame of a video signal) is supplied.

The 1394 audio signal is sent to the deinterleave circuit 13, the control signal demodulation circuit 14, and the frequency divider 17 of the audio signal processing circuit 2. The deinterleave circuit 13 performs deinterleave processing, error correction processing, and the like on the 1394 audio signal, and then sends the signal to the interpolation filter 3. Further, the control signal demodulation circuit 14 demodulates various kinds of code information as shown in FIG. 5 added to the 1394 audio signal, and sends it to the microcomputer 12.

The interpolation filter 3 performs high-order digital interpolation using, for example, Lagrange's polynomial when an error such as data loss exists in the audio signal after the deinterleave processing and the error correction processing. Is what you do. The digital audio signal output from the interpolation filter 3 is output to a sample rate converter 4
Is sent to the D / A converter 7.

The sample rate converter 4 provides a clock for the 1394 audio signal (hereinafter 1394 clock).
System clock signal) and a 1394 rate converter 4a operating with a clock for the 958 audio signal (hereinafter, referred to as a 958 system clock signal).
An eight-rate conversion unit 4b for converting the sampling rate of the 1394 audio signal to the sampling rate of the 958 audio signal based on the respective 1394 clock signals and 958 clock signals generated as described later. It is.

The digital audio signal based on the 958 clock signal converted by the sample rate converter 4 is sent to the signal processing circuit 5. The signal processing circuit 5 generates a digital audio signal of a signal format conforming to the 958 standard based on the 958-system clock signal, and outputs the digital signal from the microcomputer (microcomputer) 12 as shown in FIG. Various code information for a 958 audio signal and the like are added, and further subjected to optical modulation processing for optical transmission and sent to a terminal 6. The terminal 6 is connected to an optical cable, so that the 958 audio signal is transmitted via the optical cable.

The microcomputer 12 generates various code information for the 958 audio signal based on various code information of the 1394 audio signal supplied from the control signal demodulation circuit 14 of the audio signal processing circuit 2 and It is sent to the processing circuit 5.

The D / A converter 7 converts the audio signal supplied from the interpolation filter 3 into an analog signal. The left (L) channel audio signal analog-converted by the D / A converter 7 is output from a terminal 8, and the right (R) channel audio signal is output from a terminal 9.

The above-described path is a main configuration for converting the rate of an audio signal. Next, a path and a configuration for generating the 1394 system clock signal and the 958 system clock signal will be described.

The frame reference signal supplied to the terminal 10 is input to the first oscillation circuit 11. The first oscillating circuit 11 includes a phase comparator 18 to which the frame reference signal is input to one input terminal, a voltage-controlled oscillator 20, and an external integrating circuit 21 as main components.
An LL (Phase-Locked Loop) circuit, for example, 49.152 MHz ± 1% (in the 48 KHz mode) or 45.158 MHz ±
A first clock signal of 1% (in the 44 kHz mode) is generated. This first clock signal is supplied to the frequency divider 1
At 9 the frequency is divided by 1/4 (or 1/6). The 1/6 frequency division in the frequency divider 19 is used when corresponding to the 32 KHz mode. The first clock signal frequency-divided by the frequency divider 19 of the first oscillation circuit 11 is used as the 1394-system clock signal as the 1394 rate converter 4a of the sample rate converter 4 and the D / A converter. 7 and the audio signal processing circuit 2.

The 1/4 frequency-divided first clock signal sent to the audio signal processing circuit 2 is sent to the frequency divider 15 in the audio signal processing circuit 2 and further divided by 1/4. Is done. The output clock signal of the frequency divider 15 is supplied to one of the interpolation filter 3 and the sample rate converter 4.
394 rate converter 4a, which is sent to the D / A converter 7 and the frequency divider 1 in the audio signal processing circuit 2
After being sent to 6 and divided by 1/64, it is sent to the frequency divider 17. The frequency divider 17 is a 1 / N frequency divider where the number of samples shown in FIG. Therefore, when the frequency of the first clock signal is 49.152 MHz, a signal having substantially the same frequency as the frame reference signal is extracted from the frequency divider 17. The output signal of the frequency divider 17 is supplied to the other input terminal of the phase comparator 18 of the first oscillation circuit 11, so that the first oscillation circuit 11 has the first phase synchronized with the 1394 audio signal. Is generated.

Here, the interpolation filter 3 is provided with a second oscillation circuit 26. The second oscillation circuit 2
Reference numeral 6 denotes a high-precision oscillation circuit using a crystal oscillator.
958 standard output system clock (958 system clock signal)
To generate a second clock signal of 49.158 MHz. This second clock signal is supplied to the frequency divider 2
After being sent to 2 and divided by ２ (or １ ／), it is sent to the frequency divider 23 in the 958 rate converter 4 b of the sample rate converter 4. The 1/3 frequency division in the frequency divider 22 corresponds to a mode in which the sampling frequency is 32 KHz.

Frequency divider 23 of sample rate converter 4
Then, the output signal from the frequency divider 22 is further frequency-divided by 、, and the output signal is sent to the frequency divider 25. The divider 2
5 is also a 1/2 frequency divider, and the 1/2 frequency divided output is sent to the frequency divider 24 of the signal processing circuit 5. The signal processing circuit 5
The frequency-divided output of the frequency divider 24 is sent to the 958 rate converter 4b of the sample rate converter 4.

Next, the digital signal converter according to the second embodiment shown in FIG. 2 will be described. In the digital signal conversion apparatus according to the second embodiment, stereo S1, stereo S2, and stereo S2 are converted from four audio channels in the 32 kHz mode of the 1394 audio signal.
A process of selecting one of the digital mixes (variable mix ratio) of S1 and S2 and converting the 958 audio signal into a 2-channel audio signal per line, or a 1394 audio signal from 3-1 stereo 4-channel. A configuration for performing digital conversion into two stereo channels and generating two-channel audio signals of 958 audio signals per line will be described.

In FIG. 2, a terminal 31 is supplied with a 1394 audio signal in a 32 kHz mode from the outside, and a terminal 10 is supplied with a 29.97 Hz frame reference signal (frame of a video signal).

The 1394 audio signal is supplied to the deinterleave circuits 43 and 44 of the audio signal processing circuit 32.
Is sent to the control signal demodulation circuit 47 and the frequency divider 51.
In the deinterleave circuits 43 and 44, the 139
4 The audio signal is subjected to a deinterleave process, an error correction process, etc., and then a digital mix circuit 4
5 and the digital switching circuit 46. The deinterleave circuit 43 is responsible for processing the audio signal of the stereo S1 of the 1394 audio signal, and the deinterleave circuit 44 is responsible for processing the audio signal of the stereo S2. Further, the 3-1 stereo processing circuit 48 converts the digital audio signals of the deinterleave circuits 43 and 44 into three.
-1 stereo audio signal is generated.
A signal of two channels of audio is generated from four channels of -1 stereo and sent to the digital switching circuit 46. Therefore, the four switched terminals of the digital switching circuit 46 are provided with the digital audio signals processed by the deinterleaving circuits 43 and 44 and the digital audio signals from the deinterleaving circuits 43 and 44, respectively. A mixed digital audio signal 45 is mixed at a variable mix ratio, and a 2-channel audio signal from the 3-1 stereo processing circuit 48 is supplied. The mixing variable amount in the digital mixing circuit 45 and the switching in the digital switching circuit 46 are automatically switched by the microcomputer 42, or the variable volume or digital volume of the digital video recorder to which the digital signal converter is applied. A case in which the user manually operates in conjunction with the changeover switch may be considered.

The control signal demodulation circuit 14 of the audio signal processing circuit 32 demodulates various code information for the 1394 audio signal as shown in FIG. Microcomputer) 42.

The digital audio signal switched and selected by the digital switching circuit 46 of the audio signal processing circuit 32 is sent to the interpolation filter 33. The interpolation filter 33 is basically the same as the interpolation filter 3 of FIG. 1 described above. When there is an error such as data loss in the supplied audio signal, for example, high-order digital interpolation using Lagrange polynomial Is what you do. The digital audio signal output from the interpolation filter 33 is sent to a sample rate converter 34 and a D / A converter 37.

The sample rate converter 34 is also the same as that shown in FIG. 1, and includes a 1394 rate converter 34a which operates on a clock for the 1394 audio signal (a 1394 clock signal) and a 1394 audio signal. And a 958 rate conversion unit 34b that operates with the 958 clock (958 clock signal).
The sampling rate of the 1394 audio signal is converted to the sampling rate of the 958 audio signal based on the 58 system clock signal.

The digital audio signal based on the 958 clock signal converted by the sample rate converter 34 is sent to the signal processing circuit 35. The signal processing circuit 35 is also the same as that shown in FIG. 1 and generates a digital audio signal having a signal format conforming to the 958 standard based on the 958 clock signal. Various kinds of code information for the 958 audio signal as shown above are added, and further subjected to optical modulation processing for optical transmission and sent to the terminal 36. The terminal 36 is connected to an optical cable, so that the 958 audio signal is transmitted via the optical cable.

The microcomputer 42 is also the same as that shown in FIG. 1, and based on the various code information of the 1394 audio signal supplied from the control signal demodulation circuit 47 of the audio signal processing circuit 32, various codes for the 958 audio signal are used. Information is generated and sent to the signal processing circuit 35.

The D / A converter 37 converts the audio signal supplied from the interpolation filter 33 into an analog signal. The left (L) channel audio signal that has been analog-converted by the D / A converter 7 is
8, the audio signal of the right (R) channel is
9 is output.

Next, a description will be given of a path and a configuration for generating the 1394 clock signal and the 958 clock signal in the configuration of the second embodiment.

The frame reference signal supplied to the terminal 40 is input to the first oscillation circuit 41. In addition, this first
The oscillation circuit 41 includes a phase comparator 58 in which the frame reference signal is input to one input terminal and a voltage-controlled oscillator 6
0, and a PLL circuit having an external integration circuit 61 as a main component.
9. Generate a first clock signal of 152 MHz ± 1%. In the second embodiment, 32 KH
Although the z mode is taken as an example, the first oscillation circuit 41
Uses 49.152 MHz, and by dividing this frequency by 1/6 using a frequency divider 59, a new 32 KH
It is not necessary to add an oscillation circuit for z-mode. 1/6 in the frequency divider 59 of the first oscillation circuit 41
The frequency-divided first clock signal is used as the 1394 clock signal,
The signal is sent to the 394 rate converter 34a, the D / A converter 37, and the audio signal processing circuit 32.

The 1/4 frequency-divided first clock signal sent to the audio signal processing circuit 32 is sent to a frequency divider 49 in the audio signal processing circuit 32, and further divided by 1/4. Is done. The output clock signal of the frequency divider 49 is sent to the interpolation filter 33, the 1394 rate converter 34a of the sample rate converter 34, and the D / A converter 37, and the audio signal processing circuit 3
After being sent to the frequency divider 506 in 2 and divided by 1/64,
The signal is sent to the frequency divider 51. The frequency divider 51 is a 1 / N frequency divider where the number of samples shown in FIG.
Therefore, the frequency of the first clock signal is 49.
When the frequency is 152 MHz, a signal having substantially the same frequency as the frame reference signal is extracted from the frequency divider 51. The output signal of the frequency divider 51 is supplied to the other input terminal of the phase comparator 58 of the first oscillation circuit 41,
As a result, the first oscillation circuit 41 generates a first clock signal phase-synchronized with the 1394 audio signal.

Also in the second embodiment,
The interpolation filter 33 is provided with a second oscillation circuit 56. The second oscillating circuit 56 is a high-precision oscillating circuit using a crystal oscillator, and is 49.158 as an output system clock (958 system clock signal) of the IEC958 standard.
A second clock signal of MHz is generated. This second clock signal is sent to the frequency divider 52 and
After being divided, 958 of sample rate converter 34
The signal is sent to the frequency divider 53 in the rate converter 34b.

Frequency divider 53 of sample rate converter 4
Then, the output signal from the frequency divider 52 is further divided by ２, and the output signal is sent to the frequency divider 55. The divider 5
5 is also a 1/2 frequency divider, and the 1/2 frequency divided output is sent to the frequency divider 54 of the signal processing circuit 35. The frequency-divided output of the frequency divider 54 of the signal processing circuit 35 is sent to the 958 rate converter 34b of the sample rate converter 34.

Further, the configuration of the above-described second embodiment is provided for two systems (for example, two configurations shown in FIG. 2), and, for example, one of the two systems has an audio signal processing circuit. It is also possible to select the stereo S1 deinterleave circuit 43 in the audio signal processing circuit 32 and select the stereo S2 deinterleave circuit 44 in the audio signal processing circuit 32 in the other configuration. As described above, by dividing the configuration of the second embodiment into two systems, 95
It becomes possible to output four channels of eight audio signals and four channels of analog audio signals.

In the above-described first and second embodiments, the second oscillating circuits are provided in addition to the interpolation filters. However, the second oscillating circuits do not necessarily need to be provided, and may be provided separately. It is also possible to attach it to the element.

In the above-described embodiment, 1394
Although the standard and the 958 standard are taken as examples, the present invention is not limited to these, and can be applied to various standards. Conversely, conversion from the 958 standard to the 1394 standard can be realized by applying the present invention.

Further, in the above-described embodiment, three types of sampling frequency modes have been described. However, the present invention is not limited to this, and can be applied to two or four or more types of modes.

As described above, in the digital signal converter according to the embodiment of the present invention, since a 1394 audio signal can be converted into a 958 audio signal satisfactorily, there is almost no deterioration in sound quality and a plurality of modes can be switched. Can be automatically switched, for example, 3
It is also possible to digitally mix four channels of 2 kHz mode audio with variable mix ratio. Further, according to the present embodiment, there is no change or variation in the audio signal level, and the interpolation of the data after the error correction processing can be automatically performed. be able to. Furthermore, in the present embodiment, since an audio signal is output to an optical cable, it can be electrically separated from a video signal processing system in, for example, a digital video recorder, and therefore, there is no possibility that noise due to ground level fluctuation will occur in the audio signal. In addition, in the present embodiment, the crystal oscillator of the second oscillation circuit 26 is only one 49.158 MHz,
For example, the clock signal in the 44 kHz mode is generated by dividing the output from the crystal oscillator, so that one expensive crystal oscillator can be saved.

[0075]

As is apparent from the above description, in the digital signal converter of the present invention, the first oscillation oscillating within the first allowable frequency deviation allowed for the digital signal of the first format. Means for sampling the digital signal in the first format to a second rate based on the clock signal from the second oscillating means oscillating within a second allowable frequency deviation allowed for the digital signal in the second format. Digital sample rate conversion means for converting the digital signal into a sampling rate of the digital signal of the format described above, and format conversion means for converting the format of the digital signal subjected to the sampling rate conversion into the second format. The digital signal of the first format conforming to the transmission standard is Even in the second format digital signals conforming to signal transmission standards, can prevent degradation of signal quality, it is possible to further reduce the size and cost increases of the apparatus configuration.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram illustrating a schematic configuration of a digital signal conversion device according to a first embodiment of the present invention.

FIG. 2 is a block circuit diagram illustrating a schematic configuration of a digital signal conversion device according to a second embodiment of the present invention.

FIG. 3 is a diagram used to describe the format of an audio signal conforming to the IEEE 1394 standard.

FIG. 4 is a diagram used for describing a mode based on a difference in sampling frequency.

FIG. 5 is a diagram used for describing audio auxiliary data (code information).

FIG. 6 is a diagram used to describe the format of an audio signal conforming to the IEC958 standard.

FIG. 7 is a diagram used to explain the data structure of one video frame in a signal format conforming to the IEEE 1394 standard.

FIG. 8 is a diagram used to describe a packet structure in a signal format conforming to the IEEE 1394 standard.

FIG. 9 is a diagram used to describe frame synchronization in a signal format conforming to the IEEE 1394 standard.

FIG. 10 is a block circuit diagram showing a schematic configuration of a digital video recorder that records and reproduces a digital video signal and a digital audio signal in a signal format conforming to the IEEE 1394 standard.

[Explanation of symbols]

2,32 audio signal processing circuit, 3,33 interpolation filter, 4,34 sample rate converter,
5,35 signal processing circuit, 6,36 VD terminal,
7, 37 D / A converter, 11, 41 First oscillation circuit, 12, 42 Microcomputer, 1
3, 43, 44 deinterleave circuit, 14, 47
Control signal demodulation circuit, 15, 16, 17, 19, 22,
23, 24, 25, 49, 50, 51, 52, 53, 5
4,55,59 divider, 18,58 phase comparator,
20, 60 voltage-controlled oscillator, 21, 61 integrating circuit, 26, 56 second oscillating circuit, 48 3-1 stereo processing circuit

────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] November 27, 1997

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0039

[Correction method] Change

[Correction contents]

As shown in FIG. 4, the digital audio signal in the audio data area has a sampling frequency of 525/60 system (NTSC system) and 625/50 system (PAL system) of the television standard broadcasting system. 48KHz, 44.1KH
There are four channel modes of z, 32 KHz, and 32 KHz. In each mode of each system,
An allowable range of the number of samples (bytes) per frame is defined, and an error of about 1% (that is, an allowable frequency deviation of the sampling frequency of about 1%) is allowed as the allowable range. For example, taking the 32 kHz 4 channel mode of the 525/60 system as an example, the number of samples (byte) per frame is as follows.
Maximum of 1080 samples (3240 bytes), minimum of 1
053 samples (3159 bytes), on average 1067.
There are 73 samples (3203.2 bytes).

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0057

[Correction method] Change

[Correction contents]

In FIG. 2, a terminal 31 is supplied with a 1394 audio signal in a 32 kHz mode from the outside, and a terminal 40 is supplied with a frame reference signal (frame of a video signal) of 29.97 Hz.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0059

[Correction method] Change

[Correction contents]

The control signal demodulation circuit 47 of the audio signal processing circuit 32 demodulates various code information for the 1394 audio signal added to the 1394 audio signal as shown in FIG. Microcomputer) 42.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0067

[Correction method] Change

[Correction contents]

The 1/4 frequency-divided first clock signal sent to the audio signal processing circuit 32 is sent to a frequency divider 49 in the audio signal processing circuit 32, and further divided by 1/4. Is done. The output clock signal of the frequency divider 49 is sent to the interpolation filter 33, the 1394 rate converter 34a of the sample rate converter 34, and the D / A converter 37, and the audio signal processing circuit 3
After being sent to the frequency divider 50 in 2 and divided by 1/64, it is sent to the frequency divider 51. The frequency divider 51 corresponds to FIG.
Is a 1 / N frequency divider where the number of samples shown in FIG. Therefore, the frequency of the first clock signal is 49.1.
When the frequency is 52 MHz, a signal having substantially the same frequency as the frame reference signal is extracted from the frequency divider 51. The output signal of the frequency divider 51 is supplied to the other input terminal of the phase comparator 58 of the first oscillation circuit 41, so that the first oscillation circuit 41 performs the first phase synchronization with the 1394 audio signal. Is generated.

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name]

[Correction method] Change

[Correction contents]

As described above, in the digital signal converter according to the embodiment of the present invention, since a 1394 audio signal can be converted into a 958 audio signal satisfactorily, there is almost no deterioration in sound quality and a plurality of modes can be switched. Can be automatically switched, for example, 3
It is also possible to digitally mix four channels of 2 kHz mode audio with variable mix ratio. Further, according to the present embodiment, there is no change or variation in the audio signal level, and the interpolation of the data after the error correction processing can be automatically performed. be able to. Further, in the present embodiment, since the audio signal is output to the optical cable, the digital signal can be electrically separated from the video signal processing system in, for example, a digital video recorder. In addition, in the present embodiment, the crystal oscillator of the second oscillation circuit 26 is only one 49.158 MHz,
For example, even when the input sampling frequency is in the 44 kHz mode, the clock signal is generated by dividing the output from the crystal oscillator, so that one expensive crystal oscillator can be saved. In this case, the code information indicating the sampling frequency is also 48KH
It is rewritten to the code corresponding to z and output.

[Procedure amendment 6]

[Document name to be amended] Statement

[Correction target item name] Explanation of sign

[Correction method] Change

[Correction contents]

[Description of Codes] 2,32 audio signal processing circuit, 3,33 interpolation filter, 4,34 sample rate converter,
5,35 signal processing circuit, 6,36 IEC958 standard output terminal, 7,37 D / A converter, 11,
41 first oscillation circuit, 12, 42 microcomputer, 13, 43, 44 deinterleave circuit,
14, 47 control signal demodulation circuit, 15, 16, 1
7, 19, 22, 23, 24, 25, 49, 50, 5
1,52,53,54,55,59 divider, 18,5
8 phase comparator, 20, 60 voltage controlled oscillator, 2
1,61 integrating circuit, 26,56 second oscillating circuit,
48 3-1 stereo processing circuit

[Procedure amendment 7]

[Document name to be amended] Drawing

[Correction target item name] Fig. 1

[Correction method] Change

[Correction contents]

FIG.

[Procedure amendment 8]

[Document name to be amended] Drawing

[Correction target item name] Figure 2

[Correction method] Change

[Correction contents]

FIG. 2

[Procedure amendment 9]

[Document name to be amended] Drawing

[Correction target item name] Fig. 5

[Correction method] Change

[Correction contents]

FIG. 5

[Procedure amendment 10]

[Document name to be amended] Drawing

[Correction target item name] Fig. 6

[Correction method] Change

[Correction contents]

FIG. 6

[Procedure amendment 11]

[Document name to be amended] Drawing

[Correction target item name] FIG.

[Correction method] Change

[Correction contents]

FIG. 10

Claims (6)

[Claims] 1. A digital signal conversion apparatus for converting a digital signal of a first format conforming to a first signal transmission standard into a digital signal of a second format conforming to a second signal transmission standard, A first oscillating unit that oscillates within a first allowable frequency deviation allowed as a sampling frequency of the digital signal of the first format; and a second oscillating unit allowed as the sampling frequency of the digital signal of the second format. A second oscillating unit that oscillates within an allowable frequency deviation, a first clock signal from the first oscillating unit, and a second clock signal from the second oscillating unit.
Digital sample rate conversion means for converting the sampling rate of the digital signal of the first format into the sampling rate of the digital signal of the second format; and a digital sample rate converted by the digital sample rate conversion means. A digital signal converter, comprising: a format converter for converting a signal format into the second format. 2. The first format and the second format each include a plurality of modes corresponding to a plurality of sampling frequencies, respectively, and the first oscillating means includes a highest sampling rate among the plurality of modes. High-frequency clock signal generating means for generating a high-frequency clock signal corresponding to a frequency mode;
Low-frequency clock signal generating means for dividing the high-frequency clock signal to generate a low-frequency clock signal corresponding to another mode, wherein either the high-frequency clock signal or the low-frequency clock signal High frequency clock signal generating means for generating a high frequency clock signal corresponding to a mode having the highest sampling frequency among the plurality of modes;
Low-frequency clock signal generating means for dividing the high-frequency clock signal to generate a low-frequency clock signal corresponding to another mode, wherein either the high-frequency clock signal or the low-frequency clock signal 2. The digital signal converter according to claim 1, wherein the digital signal is output as a second clock signal. 3. The format conversion means according to claim 1, wherein:
Of the digital signal of the format
Code information generating means for generating second code information to be added to the digital signal in the second format based on the code information of the second format, and a digital signal having a sampling rate converted by the digital sample rate converting means. 2. The digital signal converter according to claim 1, further comprising: code information adding means for adding the second code information. 4. The apparatus according to claim 1, further comprising channel conversion means for converting the digital signals of the plurality of channels in the first format into digital signals of the number of channels usable in the second format. Digital signal converter. 5. The channel converting means includes a channel switching means for selecting any one of a plurality of channels, a channel mixing means for mixing a plurality of channels, and a channel generating means for generating a predetermined number of channels from the plurality of channels. 5. The digital signal converter according to claim 4, wherein: 6. The first signal transmission standard is IEEE13.
2. The digital signal conversion device according to claim 1, wherein the 94th standard and the second signal transmission standard are IEC958 standards, and the first and second digital signals are digital audio signals.