JPH1094259A - Parallel control device for inverter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the unbalance of the output current of every inverter by a method wherein the ON-pulse width of a PWM control signal to be applied to a switching element is controlled to be short in such a way that the deviation between the mean value of output currents of a plurality of parallel-connected inverters and respective values of the output currents becomes zero. SOLUTION: In a plurality of parallel-connected inverters 101, 201, the deviation (the unbalanced current value) between the mean value of output currents of the respective inverters 101, 201 and respective values of the output currents is detected directly by current transformers 122, 222. Then, pulse-width correction circuits 161, 261 and pulse-width correction circuits 162. 262 control On-pulse widths of a PWM control signal 7 and a PWM control signal 8 to be applied to switching elements 151, 251 and to switching elements 152, 252 to be short in such a way that the deviation becomes zero. Thereby, the unbalance of the output currents of the respective inverters 101, 201 can be suppressed, output reactors 102, 202 can be miniaturized, and it is possible to prevent an output capacity from being dropped.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter parallel control device for providing an output current imbalance suppression control function for increasing the capacity of an inverter, and for connecting and operating a plurality of inverters in parallel. Things.

[0002]

2. Description of the Related Art FIG. 3 shows the configuration of a conventional inverter parallel control device. That is, a plurality of inverters 101, 201, to n01 (where n is a natural number of 2 or more) are connected to a common input power supply 1 and outputs of the inverters are connected in parallel via reactors 102, 202, to n02. Connected. And multiple inverters connected in parallel 1
Any one of 01, 201, ..., n01,
For example, the inverter 101 is provided with a PWM control signal generator 6 for generating a PWM control signal, and its output, PWM
The positive switching elements 151, 251, ..., n51 and the negative switching elements 15 of the inverters 101, 201, ..., n01 connected in parallel by the control signal 7 and the PWM control signal 8
2, 252, ..., n52 were driven respectively, and the inverters were operated in parallel. With the above configuration, each of the switching elements 151, 251,.
And the output current imbalance between the inverters, which is caused by the variations in the characteristics of the switching elements 152, 252, ..., n52, such as the turn-on time, turn-off time, and on-resistance, to the output reactors 102, 202, ..., n02. And to increase the output capacity of the inverter by several times the number of inverters in parallel.

[0003]

Since the output reactor is, of course, an inductance component, it has the effect of suppressing unbalance only with respect to alternating current. However, in the case of an inverter for driving a motor, the inverter may be operated with low-frequency AC or DC.In order to suppress current imbalance only with the output reactor, not only does the reactor become large, but especially in DC operation. The suppression action does not work at all, and the output current sharing of each inverter is greatly disrupted, the output capacity of the parallel inverter is reduced, and in some cases, the parallel full load current flows to one inverter and the inverter may be damaged. there were. The present invention has been made to solve the above drawbacks.

[0004]

Means for Solving the Problems The outputs of a plurality of inverters 101, 201,..., N01 (where n is a natural number of 2 or more) having a common input power supply 1 are reactors 102, 20.
In the inverter device connected in parallel through 2,..., N02, when a current flows from the inverter in the direction of the output to the respective inverters, a secondary current flows through terminals 112, 212,
, And current transformers 111, 211, ..., n11 flowing out from terminals 113, 213, ..., n13 flowing out from n12.
211, ~, (n-1) 11 terminals 113, 213, ..., (n-1) 13 and current transformers 211, 311, ..., n11 terminals 212, 312, ..., n1
Are connected by short-circuit wires 12, 23, ..., (n-1) n.
Terminal 112 of the current transformer n11 and the terminal n13 of the current transformer n11 are connected by a short-circuit line n1, and the terminals 112, 21 of the current transformers 111, 211,.
A resistor 12 is connected between 2, 12, and n12 and terminals 113, 213, and n13.
1, 221, ..., n21, and current transformers 122, 222, ..., n22 for detecting the current flowing through the resistor, and the current flowing through the resistor by amplifying the current detected by the current transformer. Of the current transformers 111, 211, ..., n11 terminals 112, 212,
Current / voltage conversion amplifier that outputs a voltage with a negative polarity when the direction is from ~, n12 to terminals 113, 213, ~, n13 1
31, 231 to n31, and one of the inverters, for example, the inverter 101, includes a current transformer 2 for detecting a current flowing through the short-circuit line n1, and an output of the current transformer 2 connected to the inverter. A multiplier 3 for multiplying the total number of
A subtractor 5 for subtracting the result of the multiplication by the multiplier 3 from the reference current command value 4;
A PWM control signal generator 6 for generating a control signal is provided.

Further, there are provided polarity discriminators 141, 241,..., N41 for discriminating between the positive and negative polarities of the output value of the current / voltage conversion amplifier and switching the output destination according to the polarity. , ..., n31, if the output value is negative, the positive switching element 151, 251,
, N61, and a pulse width correction circuit 161 to reduce the on-pulse width of the PWM control signal applied to the n51 according to the output amount of the current / voltage conversion amplifier. Then, pulse width correction circuits 162, 262,... For shortening the ON pulse width of the PWM control signal applied to the negative switching elements 152, 252,. , N6
2 is provided. The present invention is an inverter parallel control device having the above configuration.

According to the inverter parallel control device of the present invention, a plurality of inverters 101, 201,
, And n01, the deviation (unbalanced current value) between the output current average value of each inverter and each output current value (unbalanced current value) can be directly detected by the current transformers 122, 222, ..., n22. Switching element 1 so that its value) becomes zero.
51, 251, ..., n51 and switching elements 152, 252,
, N52 and the pulse width correction circuits 162, 2 are controlled by the pulse width correction circuits 161, 261,..., N61 to reduce the on-pulse width of the PWM control signal 7 and the PWM control signal 8 applied to the n52.
Automatically performed at steps 62, 62, and n62, the output current imbalance of each inverter can be suppressed, the output reactor can be reduced in size, and the output capacity can be prevented from lowering.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an application example of the present invention in which n inverters are connected in parallel, and the operation thereof will be described in detail for the case of two parallels shown in FIG. As shown in FIG. 2, two inverters 101 and 201 are connected to a common input power supply 1, and the outputs of the inverters are connected in parallel via reactors 102 and 202. Each inverter has a current flowing in the direction from the inverter to the output. When the secondary current flows out of the terminals 112 and 212,
Current transformers 111 and 211 flowing from terminals 113 and 213,
Connect the terminal 113 of the current transformer 111 to the terminal 212 of the current transformer 211 with the short-circuit line 12, and further connect the terminal 112 of the current transformer 111 to the current transformer.
The terminals 213 of 211 are connected by the short-circuit line 21. That is,
The secondary sides of the current transformers 111 and 211 are connected in series in a ring shape.

Further, terminals 112, 212 of current transformers 111, 211
Connect the resistors 121 and 221 between the
Current transformers 122 and 222 for detecting the current flowing through 1, 221 (ie, the average value of the output current of each inverter and the deviation (unbalanced current value) of each output current value);
Amplify the current detected at 2, 222 and add the resistors 121, 22
The direction of the current flowing in 1 is the terminal 112 of the current transformer 111, 211,
A current / voltage conversion amplifier 131, 231 that outputs a voltage with a negative polarity when the direction is from 212 to terminals 113, 213, and one of two inverters 101, 201 connected in parallel, for example, an inverter. 101, a current transformer 2 for detecting the current flowing through the short-circuit line 21, ie, the average value of the output current of each inverter, and the output of the current transformer 2 multiplied by the number of inverters (doubled) to obtain the total output current value of each inverter. , A subtracter 5 that subtracts the result of the multiplication by the multiplier 3 from a reference current command value 4 and outputs a deviation amount of the total output current, and a total output that is a subtraction result of the subtractor 5. A PWM control signal generator 6 that generates a PWM control signal based on the current deviation amount is provided.

Further, current / voltage conversion amplifiers 131 and 231
Polarity discriminators 141 and 241 for discriminating the positive and negative polarities of the output values of the inverters and switching the output destination according to the polarity. If the output values of the current / voltage conversion amplifiers 131 and 231 are negative, the positive side switching element of the inverter PWM applied to 151, 251
The ON pulse width of the control signal 7 is changed by the current / voltage conversion amplifier 13
1, pulse width correction circuit to shorten according to the output amount of 231 16
If the output value of the current / voltage conversion amplifiers 131 and 231 is positive, the negative side switching element of the inverter
Pulse width correction circuits 162 and 262 for shortening the ON pulse width of the PWM control signal 8 applied to 52 and 252 in accordance with the output amount of the current / voltage conversion amplifiers 131 and 231.

With the above-described configuration, the deviation (unbalanced current value) between the average output current value of the two inverters and each output current value in each of the two inverters 101 and 201 is changed. The deviation is directly detected by the detectors 122 and 222, and the deviation is amplified by the current / voltage conversion amplifiers 131 and 231. Using the output results of the current / voltage conversion amplifiers 131 and 231, output current imbalance suppression control is performed to reduce the deviation of the output current value to zero. Hereinafter, the details of the output current imbalance suppression control will be described focusing on the inverter 101.

In a mode in which the output current flows from the inverter 101 to the load side, a current flows through one of the freewheeling diodes connected in parallel with the positive switching element 151 or the negative switching element 152. Here, when the output value of the current / voltage conversion amplifier 131 installed in the inverter 101 is negative, the output current value of the inverter 101 is larger than the average output current value of the two inverters 101 and 201. When a current is flowing through the positive switching element 151, the PW applied to the positive switching element 151
If the ON pulse width of the M control signal 7 is shortened, the inverter 1
Output current imbalance is eliminated because the output current of 01 can be reduced.

When a current is flowing through the freewheeling diode connected in parallel with the negative switching element 152, even if the PWM control signal 7 and the PWM control signal 8 are operated, there is no change in the output current. Conversely, when the output value of the current / voltage conversion amplifier 131 installed in the inverter 101 is positive, the output current value of the inverter 101 is smaller than the average output current value of the two inverters 101 and 201. If the on-pulse width of the PWM control signal 7 applied to the positive side switching element 151 while the current is flowing through the positive side switching element 151 is reduced, the output current of the inverter 101 is further reduced. It becomes even larger. When a current is flowing through the freewheel diode connected in parallel with the negative switching element 152, the output current does not change at all even if the PWM control signal 7 and the PWM control signal 8 are operated. Therefore, when the output value of the current / voltage conversion amplifier 131 is positive, the PWM control signal 7 applied to the positive switching element 151 is not operated.

On the other hand, the output current is controlled by the inverter 1 from the load side.
In the mode flowing to 01, a current is flowing to either the negative switching element 152 or the freewheeling diode connected in parallel with the positive switching element 151. here,
Current / voltage conversion amplifier installed in inverter 101 1
When the output value of 31 is positive, two inverters 101,
In the case where the output current value of the inverter 101 is larger than the average output current value of 201, when the current flows through the negative switching element 152, the on-pulse width of the PWM control signal 8 applied to the negative switching element 152 is shortened. Then, since the output current of the inverter 101 can be reduced, the output current imbalance is eliminated.

When a current is flowing through the freewheel diode connected in parallel with the positive switching element 151, the output current does not change at all even if the PWM control signal 7 and the PWM control signal 8 are operated. Conversely, when the output value of the current / voltage conversion amplifier 131 installed in the inverter 101 is negative, the output current value of the inverter 101 is smaller than the average output current value of the two inverters 101 and 201. If the on-pulse width of the PWM control signal 8 applied to the negative switching element 152 while the current is flowing through the negative switching element 152 is reduced, the output current of the inverter 101 is further reduced. It becomes even larger. When a current is flowing through the freewheeling diode connected in parallel with the positive switching element 151, the output current does not change at all even if the PWM control signal 7 and the PWM control signal 8 are operated. Therefore, when the output value of the current / voltage conversion amplifier 131 is negative, the PWM control signal 8 applied to the negative switching element 152 is not operated.

As described above, by automatically controlling the on-pulse width of the PWM control signal applied to the switching element by the pulse width correction circuit, the output current imbalance of each inverter can be suppressed, and the output reactor can be controlled. Can be downsized, and the output capacity can be prevented from lowering.

[0016]

As described above, according to the present invention, in each of a plurality of inverters connected in parallel, the deviation (unbalanced current value) of each output current value from the average output current value of each inverter is determined. The pulse width correction circuit can automatically perform control to detect and reduce the on-pulse width of the PWM control signal applied to the switching element so that the deviation becomes zero. In particular, according to the present invention, the deviation (unbalanced current value) of each output current value from the average output current value of each inverter is directly detected by the current transformer, so that the deviation is determined by the addition / subtraction circuit using an operational amplifier or the like. The detection error can be made very small as compared with the method of detecting, and the circuit configuration becomes extremely simple.

By the operation of the unbalance current suppression control described above, the output current unbalance of each inverter can be suppressed, and the output reactor can be reduced in size. In particular, in the case of DC operation, the output current imbalance suppression action by the output reactor does not work at all, so the output current imbalance suppression control according to the present invention is extremely effective, and the output current sharing of each inverter is greatly reduced, and the output capacity of the parallel inverter is reduced. Is reduced, and in some cases, a parallel full load current flows through one inverter and the inverter is not damaged. As a result, the output capacity of the inverter can be made several times the number of inverters in parallel, and the capacity of the inverter can be increased.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention.

FIG. 2 is an embodiment of the present invention when two inverters are arranged in parallel.

FIG. 5 is a configuration diagram in the case of a conventional inverter parallel connection.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input power supply 2 Current transformer 3 Multiplier 4 Current command value 5 Subtractor 6 PWM control signal generator 7 PWM control signal 8 PWM control signal 12- (n-1) n Short-circuit line n1 Short-circuit line 101-n01 Inverter 102- n02 Reactor 111-n11 Current transformer 112-n12 Secondary terminal of current transformer 113-n13 Secondary terminal of current transformer 121-n21 Resistance 122-n22 Current transformer 131-n31 Current / voltage conversion amplifier 141- n41 Polarity discriminator 151-n51 Positive side switching element 152-n52 Negative side switching element 161-n61 Pulse width correction circuit 162-n62 Pulse width correction circuit

Claims (1)

[Claims] An output of a plurality of inverters (101, 201,..., N01) (where n is a natural number of 2 or more) having a common input power supply (1) is supplied to reactors (102, 202,.
2) In the parallel control device of the inverters connected in parallel via the second), when a current flows from the inverter to the output in each of the inverters (101, 201, to n01), a secondary current is supplied to the terminals (112, 212). , ..., n12) and current transformers (111, 211, ..., n11) flowing in from terminals (113, 213, ..., n13).
211, ~, (n-1) 11) terminals (113, 213, ~,
(N-1) 13) and a short-circuit wire (12, 23, ..., n12) between the terminals (212, 312, ..., n12) of the current transformer (211, 311, ..., n11).
, (N-1) n) and the terminal (112) of the current transformer (111) and the terminal (n13) of the current transformer (n11) are connected by a short-circuit line (n1). , The current transformers (111, 211, ..., n
11) terminals (112, 212, ..., n12) and terminals (113, 2
, N13), and a current transformer (122, 222, ...) for detecting a current flowing through the resistance (121, 221, ..., n21). , N22) and the currents detected by the current transformers (122, 222,..., N22) are amplified and the direction of the current flowing through the resistors (121, 221,. 211, ..., n11) terminals (11
2, 212, ~, n12) to terminal (113, 213, ~, n13)
Current / voltage conversion amplifiers (131, 231,..., N31) for outputting a voltage with a negative polarity when the direction is the same as that of the inverter (101, 201,..., N01).
A current transformer (2) for detecting a current of the short-circuit line connected to the inverter; and a current transformer (2).
A multiplier (3) for multiplying the output of the inverter by the total number of inverters,
A subtracter (5) for subtracting the result of the multiplication by the multiplier (3) from a reference current command value (4), and a PWM for generating a PWM control signal based on the result of the subtraction by the subtracter (5).
A polarity discriminator (1) for determining whether the output value of the current / voltage conversion amplifiers (131, 231, ..., n31) is positive or negative and switching the output destination according to the polarity;
41, 241, ..., n41), and if the output value of the current / voltage conversion amplifier (131, 231, ..., n31) is negative, the positive switching element (151, 251, ..., n) of the inverter is provided.
n51) and the on-pulse width of the PWM control signal (7) applied to the current / voltage conversion amplifiers (131, 231, ..., n3).
Pulse width correction circuit (16) that shortens according to the output amount of (1)
1, 261, ..., n61) and the current / voltage conversion amplifier (
If the output value of 131, 231, ..., n31) is positive, the negative side switching element (152, 252, ..., n5) of the inverter is concerned.
2) The on-pulse width of the PWM control signal (8) applied to the current / voltage conversion amplifier (131, 231, ..., n31)
Pulse width correction circuit (162, 2
62, ..., n62), a parallel control device for an inverter.