JPH1092179A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device which enables the quick recovery of a bit line. SOLUTION: A column selection gate control signal CSGC is generated in accordance with a data transition detection signal DTD and a column decoding signal CD. A precharge signal PC is generated in accordance with the data transition detection signal DTD and an internal writing enable signal/WEi. If the internal writing enable signal/WEi is inactivated, the precharge signal is activated and the precharge of a bit line is started. Further, in response to the column selection gate control signal CSGC, even after a writing cycle is finished, a column selection gate is continuously in an open state for a period Δt by a writing circuit and the precharge of the bit line is continued.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a circuit for precharging the potential of a bit line.

[0002]

2. Description of the Related Art FIG. 23 is a circuit diagram showing a column selection gate control signal generation circuit 2300 for generating a column selection gate control signal in a conventional semiconductor memory device.

Referring to FIG. 23, a column selection gate control signal generating circuit 2300 includes a NAND gate 701 and an N gate.
And an inverter 703 connected to the output node of the AND gate 701.

A data transition detection signal DTD is inputted to one input node of the NAND gate 701, and a column decode signal for selecting a bit line is inputted to the other input node. Here, the data transition detection signal DTD
Is a signal that is activated by detecting a transition of data input from the outside.

[0005] The output signal from NAND gate 701 is inverted by inverter 703, and a column selection gate control signal CSGC is output.

FIG. 24 is a circuit diagram showing a peripheral portion of a bit line pair 20, column select gates 27a and 27b, and a precharge circuit 601 in a conventional semiconductor memory device.

Referring to FIG. 24, bit line pair 20 includes a bit line 20a and a bit line 20b.

In a data write circuit, a bit line pair 20
a is connected to the column selection gate 27a, and the bit line pair 20b is connected to the column selection gate 27b.

The precharge circuit 601 includes NMOS transistors 25a and 25b each having a source / drain electrode supplied with a power supply voltage. The NMOS transistors 25a and 25b are bit line loads, and the other source / drain electrode of the NMOS transistor 25a is the bit line 2
0a, and the other source / drain electrode of the NMOS transistor 25b is connected to the bit line 20b.

The column selection gate control signal CSG shown in FIG.
C is input to the gate electrodes of the column selection gates 27a and 27b. The inverted signal / CSGC of the column selection gate control signal inverted by the inverter 2101 is used as the precharge signal PC for the column selection gates 27a and 27b formed of NMOS transistors. Input to the gate electrode. FIG. 25 shows bit lines 20a, 20a in a normal state.
6 is a timing chart showing a state of recovery of a voltage b.

Referring to FIG. 25, in a write cycle, an internal write enable signal / WEi is generated based on an externally input write enable signal / WE, and at the same time, externally input data is transferred. Write data WD is originally generated.

Based on these, bit lines 27a, 27b
Data signals DATA, / DATA to be supplied to
Is generated and applied to column select gates 27a and 27b from a write circuit (not shown). The column decode signal CD is activated at H level until the column address changes.
The data transition detection signal DTD is activated at the H level during the write cycle, and is activated for a predetermined period of time upon detecting the transition of the externally input data and the internal write enable signal / WEi to attain the H level. In response to data transition detection signal DTD, write column decode signal generation circuit 2300 activates H level in response to data transition detection signal DTD and column decode signal CD, and deactivates transition detection signal DTD to L level. Then, in response thereto, a column selection gate control signal CSGC inactivated to L level is generated and applied to the gate electrodes of column selection gates 27a and 27b.

Therefore, in the normal state, it is the data transition detection signal DTD that determines the transmission of data to the bit line. When the pulse of the data transition detection signal ends, the data transmission to the bit line is stopped. Then, the recovery of the bit line is started. In the normal state, the pulse of the data transition detection signal DTD falls sufficiently faster than the change of the external address signal when shifting from the write cycle to the read cycle, so that the bit line recovery is completed before the next address is selected. I do. Therefore, it does not affect the next address access or the like.

Here, the normal state means that the power supply voltage Vcc =
5 V means that the write operation is completed in the write cycle before the external address signal changes.

[0015]

However, in the case where the write operation is completed simultaneously with the change of the external address signal and the data changes during the write cycle, the power supply voltage Vcc is low (3 [ V], the pulse of the data transition detection signal DTD is inactivated after the change of the external address signal, unlike the case of the normal state.

FIG. 26 is a timing chart showing how bit lines are recovered when power supply voltage Vcc is low.

Referring to FIG. 26, data transition detection signal D
TD is at the H level during the period Δt from the time when the external address signal changes.

Therefore, column select gate control signal C
The precharge signal PC, which is an inverted signal of the SGC, goes to the H level with a delay of time Δt from the change of the external address signal.

Due to the precharge signal PC, the bit line loads 25a and 25b remain off for a period Δt even after the external address signal enters a read cycle.
There is a problem that the precharge of the bit line is delayed.

That is, when power supply voltage Vcc is low, transmission of data to bit lines is determined differently from the case of normal state, not by data transition detection signal DTD, but by internal write signal / WEi. Becomes Since internal write signal / WEi is inactivated and rises to H level simultaneously with the change of the external address signal, the recovery of the bit line is started at this timing. Therefore, unlike the case of the normal state, the recovery of the bit line extends to the next read cycle, causing a delay in address access, garbled data, and the like.

In order to prevent such a failure due to the recovery, it is conceivable to employ a method of increasing the size of the bit line load or increasing the bit line equalization. However, any of these methods causes an increase in the chip area. was there.

Japanese Patent Application Laid-Open No. 3-29189 discloses the following method to solve the above-mentioned problems.

FIGS. 27 and 28 are circuit diagrams showing a conventional static random access memory disclosed in Japanese Patent Application Laid-Open No. 3-29189.

FIG. 29 is a timing chart showing how the bit line is precharged by the static random access memory shown in FIGS.

Referring to FIGS. 27 to 29, this static random access memory includes a delay circuit 1, a write circuit 2, and NMOS Trs (column selection gates) 4, 5.
, NMOS Trs (bit line loads) 29 and 30, bit lines BL and / BL, write circuit output control terminal 11,
L (1 to n) is the main configuration. The write control input WE is input to the delay circuit 1.

In this static random access memory, after completion of writing, precharging is performed by writing circuit 2 of FIG. 27 for a predetermined time (D) during a period in which precharging is performed by the circuit shown in FIG. It is.

However, the precharge signal PC for controlling precharge by the circuit of FIG.
7, since there is no relation between the delay of the write control signal WE for controlling the NMOS Trs 4 and 5 in the write circuit 2 and its generation, it is difficult to control the precharge time D by the write circuit 2. Was.

The present invention has been made to solve the above problems, and provides a semiconductor memory device capable of improving bit line voltage recovery without increasing the chip area. This is the first object.

A second object of the present invention is to provide a semiconductor memory device capable of easily controlling a precharge time by a precharge circuit and a write circuit.

[0030]

According to a first aspect of the present invention, there is provided a semiconductor memory device, comprising: a memory cell; a bit line connected to the memory cell; and data written to the memory cell in response to a first signal. Data writing means, precharge means for precharging a bit line after completion of data writing by the data writing means in response to the second signal, and data writing means based on the write enable signal. A first signal which is activated at the time of data writing and is continuously activated for a predetermined time after the data writing is completed, and a second signal which is activated after the data writing by the data writing means is completed. And a signal generating means for outputting.

A semiconductor memory device according to a second aspect of the present invention is the semiconductor memory device according to the first aspect, further comprising a data transition detecting means for detecting a transition of externally input data and outputting a data transition detection signal. Provided
A write buffer for outputting data to be written to the memory cell to the data writing means, a column selection gate connected between the write buffer and the bit line and turned on / off in response to a first signal; And a precharge means is provided with a bit line load connected between the bit line and the power supply for supplying a precharge voltage in response to a second signal, and the signal generation means is provided with a bit line at one input node. , A data selection detection signal is input to the other input node, and a first AN that outputs a first signal is input.
A D gate and a second AND gate that receives a write enable signal at one input node, receives a data transition detection signal at the other input node, and outputs a second signal are provided.

According to a third aspect of the present invention, in the semiconductor memory device of the first aspect, the semiconductor memory device further comprises a data transition detecting means for detecting a transition of externally input data and outputting a data transition detection signal. Provided
A write buffer for outputting data to be written to the memory cell to the data writing means, a column selection gate connected between the write buffer and the bit line and turned on / off in response to a first signal; And a bit line load connected between the bit line and the power supply for supplying a precharge voltage in response to the second signal is provided in the precharge means, and the write enable signal is delayed in the signal generation means. A delay means for generating a delay signal of a write enable signal, and a column selection signal for selecting a bit line to one input node,
A first AND gate to which a delay signal of the write enable signal is input to the other input node and which outputs a first signal;
A write enable signal is input to one input node, a delay signal of the write enable signal is input to the other input node, and a second AND gate that outputs a second signal is provided.

According to a fourth aspect of the present invention, there is provided the semiconductor memory device according to the first aspect, wherein the write buffer for outputting data to be written to the memory cell to the data writing means, and the write buffer. A column selection gate connected between the bit line and a power supply, the column selection gate being turned on / off in response to a first signal, provided between the bit line and a power supply. A bit line load for supplying a precharge voltage, a column selection signal for selecting a bit line is input to one input node to the signal generation means, and a data transition detection signal is input to the other input node, An AND gate that outputs a second signal; and a delay unit that delays the second signal to generate a first signal, detects a transition of data input from the outside, and outputs a data transition detection signal. You It is obtained by further providing a data transition detection means.

According to a fifth aspect of the present invention, in the semiconductor memory device of the first aspect, a write buffer for outputting data to be written to the memory cell to the data writing means, and a write buffer. A column selection gate connected between the bit line and a power supply, the column selection gate being turned on / off in response to a first signal, provided between the bit line and a power supply. A bit line load for supplying a precharge voltage, a column selection signal for selecting a bit line is input to one input node to the signal generation means, a write enable signal is input to the other input node, An AND gate for outputting a second signal and delay means for delaying the second signal to generate the first signal are provided.

[0035]

Embodiments of the present invention will be described below with reference to the drawings.

The same reference numerals in the drawings denote the same or corresponding parts. (1) First Embodiment FIG. 1 shows a semiconductor memory device 100 according to a first embodiment of the present invention.
FIG. 3 is a block diagram showing the configuration of FIG.

The semiconductor memory device 100 includes a row address signal input terminal 101, a row address buffer 102 for amplifying or inverting the input row address signal, and a row address signal applied to the row address signal input terminal 101. A row decoder for decoding, a column address signal input terminal 104, a column address buffer 105 for amplifying or inverting the input column address signal, and a column address signal applied to the column address signal input terminal 104 A column decoder 106 for decoding, a memory cell array 107 in which a plurality of memory cells storing data are arranged in a matrix, a multiplexer 108, a sense amplifier 109 for sensing and amplifying a small amplitude read voltage, and a sense amplifier Level for further taking out the output of the semiconductor memory device 100 Output data buffer 110 for amplifying the read data, read data output terminal 111 for outputting read data, write data input terminal 112 for inputting write data, and write data input terminal 112. Write circuit 11 for amplifying read data
3, a chip selection signal input terminal 114, a read / write control input terminal 115, and a sense amplifier 109, a data output buffer 110, and a write data buffer 113 according to chip selection / non-selection and data read / write mode. Read / write control circuit 116 that controls
And

The row address signal input terminal 101 is connected to a row address buffer 102. The row address buffer 102 is connected to a row decoder 103. The row decoder 103 is connected to a plurality of word lines (not shown) in the memory cell array 107.

The column address signal input node 104 is connected to a column address buffer 105. The column address buffer 105 is connected to a column decoder 106. The column decoder 106 is connected to the multiplexer 108. The multiplexer 108 is connected to a plurality of bit lines (not shown) in the memory cell array 107.

The sense amplifier 109 is connected to the multiplexer 10
8 and its output is connected to the output data buffer 110. An output node of the output buffer 110 is provided with a data output terminal 111.

A data input terminal 112 is provided at an input node of the data buffer 113, and an output node is connected to the multiplexer 108.

The read / write control circuit 115 is provided with a chip select input terminal 114 and a read / write control input terminal 115, the outputs of which are sense amplifier 109, output data buffer 110, and write data buffer 113 And connected to.

Data input from the data input terminal 112 is input to the input data buffer 113 and the multiplexer 108.
Are written to the memory cells in the memory cell array 107 via Data read from a memory cell in memory cell array 107 is amplified by sense amplifier 109 via multiplexer 108 and read from data output terminal 111 via output data buffer 110.

At this time, a memory cell to be written or read is selected based on a row address signal input from row address signal 101 and a column address signal input from column address signal input terminal 104. The memory cell connected to the selected word line and bit line is selected.

FIG. 2 is a circuit diagram showing the inside and peripheral portions of memory cell array 107 of FIG.

Here, for simplicity, a configuration having two rows and two columns is shown. Referring to FIG. 2, memory cell array 107 includes word line 2 connected to row decoder 103.
2, 23, a bit line pair 20, 21 and a memory cell 24.
a, 24b, 24c, 24d.

Bit line pair 20 includes bit lines 20a and 20a.
b. The bit line pair 21 includes bit lines 21a and 21b.
including.

A peripheral portion of the memory cell array 107 includes a precharge circuit 601, a multiplexer 108, and an input / output line pair 29.

The precharge circuit 601 includes bit line loads 25a, 25b, 26a, 26b. The multiplexer 108 includes column selection gates 27a, 27b, 28
a, 28b. The input / output line pair 29 is
a, 29b.

Word line 2 connected to row decoder 103
2 is connected to the memory cells 24a and 24b.
Similarly, the word line 23 connected to the row decoder 103
Are connected to the memory cells 24c and 24d.

The multiplexer 108 includes column selection gates 27a, 27b, 28a, 28b.

One input / output line 29a of the input / output line pair is connected to one bit line pair 20a of the bit line pair 20 via a column selection gate 27a.
Is connected to one of the bit lines 21a of the bit line pair 21. The other input / output line 29b of the input / output line pair 29
Is connected to the other bit line 20b of the bit line 20 via a column selection gate 27b.
b, it is connected to the other bit line 21b of the bit line pair 21. The column selection gates 27a and 27b are commonly connected, and the column selection gates 28a and 28b are commonly connected and both are connected to the column decoder 106.

The bit line loads 25a, 25b, 26a and 26b in the precharge circuit 601 are NMOS transistors, one of which has a source / drain electrode and a gate electrode connected to a power supply. The other source / drain electrode of bit line load 25a is connected to bit line 20a, the other source / drain electrode of bit line load 25b is connected to bit line 20b, and the other source / drain electrode of bit line load 26a is connected to bit line 21a. , The other source / drain electrode of the bit line load 26b is connected to the bit line 21b.

In FIG. 8, write data input from data input terminal 112 is supplied to input lines 29a and 29b of input / output line pair 29 as complementary signals by data input buffer 113. And the column decoder 10
The data is stored in one of the memory cells 24a, 24b connected to the word line 22 or 23 selected by the row decoder 103 via the column selection gates 27a, 27b or 28a, 28b turned on by 6.

FIG. 3 shows the memory cells 24a to 24d of FIG.
FIG. 2 is a circuit diagram showing a high-resistance load type NMOS memory cell as an example of FIG.

FIG. 4 shows the memory cells 24a to 24d of FIG.
FIG. 3 is a circuit diagram showing a CMOS type memory cell as an example of FIG.

Referring to FIG. 3, high resistance load type NMOS memory cell 300 includes N-channel driver transistors 41a and 41b, N-channel access transistors 42a and 42b, and load resistors 43a and 43b.

N-channel driver transistor 41
In a and 41b, one source / drain electrode is connected to the storage nodes 45a and 45b, the other source / drain electrode is connected, and the gate electrode is connected to one of the source / drain electrodes. N-channel access transistors 42a and 42b have one source / drain electrode connected to storage nodes 45a and 45b and the other source / drain electrode connected to bit lines 20a (21a) and 20b (21b), and a gate electrode connected to a word line. 22 (23). The load resistors 43a and 43b have one ends connected to the power supply and the other ends connected to the storage nodes 45a and 45b.

Referring to FIG. 4, CMOS memory cell 4
00 is a high resistance load type NMOS memory cell 300 of FIG.
, The load resistors 43a and 43b are respectively connected to the PMO
It is replaced with S transistors 44a and 44b.

The gate electrode of the PMOS transistor 44a is connected to the gate electrode of the N-channel driver transistor 41a, and further connected to the storage node 45b. The gate electrode of the PMOS transistor 44b is connected to the gate electrode of the N-channel access transistor 41b, and further connected to the storage node 45a.

FIG. 5 is a timing chart for explaining the operation of the circuits shown in FIGS. In FIG. 5, Ai
n indicates an address signal input, Aout indicates an address buffer output, WL indicates a word line, I / O indicates an input / output line, SAout indicates a sense amplifier output, and Dout indicates a data output.

When the memory cell 24a is selected,
A row address signal corresponding to the row in which memory cell 24a to be selected is located is input from row address signal input node 104, and word line 22 connected to memory cell 24a attains a selected level (for example, H level). Word line 23 is at a non-selected level (for example, L level).

Similarly, when selecting a bit line, a column address signal corresponding to the column where bit line pair 20 to which memory cell 24a to be selected is connected is input from column address input terminal 104, and the bit line pair is input. Transfer gate 27 connected to 20 bit lines 20a, 20b
a and 27b conduct, so that the selected bit line 2
The input / output lines 29a, 29 of the input / output line pair 29 only for 0a, 20b
9b, the other bit line pair 21 is deselected and disconnected from the input / output line pair 29.

Next, a read operation from the selected memory cell 24a will be described. Now, in FIG. 4, it is assumed that storage node 45a of the memory cell is at H level and storage node 45b is at L level.

At this time, one driver transistor 41a of memory cell 24a is off, and the other driver transistor 41b is on. Since the word line 22 is selected at the H level, the access transistors 42a and 42b of the memory cell 24a are selected.
Are both conductive.

Therefore, power supply Vcc → bit line load 2
5b → bit line 20b → access transistor 42b →
A direct current is generated on the path from the driver transistor 41b to the ground GND.

However, the power supply (Vc
c) → the bit line load 25a → the bit line 20a → the access transistor 42a → the driver transistor 41a → the driver transistor 41a in the path of ground (GND)
Is in a non-conducting state, no DC current flows. At this time, the potential of the bit line 20a through which no DC current flows is changed by the bit line load transistors 25a, 25b, 26a, 26b.
Is assumed to be Vth (power supply potential Vcc−
(Threshold voltage Vth). Further, the potential of the bit line 20a through which the DC current flows depends on the driver transistor 41
b, access transistor 42b and bit line load 25b
Are divided by the conduction resistance between the two, and the potential drops by ΔV from (power supply potential Vcc−threshold voltage Vth) to (power supply potential Vcc−threshold voltage Vth−ΔV).

Here, ΔV is called a bit line amplitude, which is usually about 50 mV to 500 mV, and is adjusted according to the magnitude of the bit line load. This bit line amplitude appears on the input / output lines 29a and 29b of the input / output line pair 29 via the transfer gates 27a and 27b.
9 and further amplified by the output buffer 110 and read out from the data output terminal 111. In the case of reading, the input / output buffer 29 is not driven by the read / write control circuit 116 in the input data buffer 113. In the case of writing, writing is performed by forcibly lowering the potential of the bit line on which L-level data is written to a low potential and raising the potential of the other bit line to a high potential.

For example, to write inverted data in memory cell 24a, one input / output line 29a is set to L level and the other input / output line 29b is set to H level by data input buffer 113, and one bit line 20a is set. To L level,
The other bit line 20b is set to the H level, and a write operation is performed.

FIG. 6 is a circuit diagram showing bit line pair 20, precharge circuit 601, and column select gates 25a and 25b.

Referring to FIG. 6, precharge circuit 601
Includes bit line loads 27a and 27b.

One source / drain electrode of the bit line load 25a is connected to a power supply, and the other source / drain electrode is connected to one bit line 20a of the bit line pair 20. One source / drain electrode of the bit line load 25b is connected to a power supply, and the other source / drain electrode is connected to the other bit line 20b of the bit line pair 20. The gate electrodes of the bit line loads 25a and 25b are connected to each other, and are supplied with a precharge signal PC.

Data signal DAT is applied to bit line 20a from write circuit 113 via column select gate 27a.
A is given. The write circuit 113 is connected to the bit line 20b.
From the data signal DA via the column selection gate 27b.
Data signal / DATA complementary to TA is applied. The gate electrodes of the column selection gates 27a and 27b are connected to each other, and supplied with a column selection gate control signal CSGC from the signal generation circuit 201.

FIG. 7 is a circuit diagram showing a signal generation circuit 700 which is an example of the signal generation circuit 201 for generating the column selection gate control signal CSGC and the precharge signal PC of FIG.

Referring to FIG. 7, signal generation circuit 700 includes:
NAND gates 701 and 702 and an inverter 703
704.

One input node of NAND circuit 701 receives column decode signal CD, and the other input node receives data transition detection signal DTD. NAN
An inverter 703 is connected to an output node of D gate 701, and a column selection gate control signal CSGC is output from the output node.

Data transition detection signal DTD is input to one input node of NAND circuit 702. Inverter 704 receives an internal write enable signal / WEi, and has an output node connected to the other input node of NAND circuit 702.

Precharge signal PC is output from the output node of NAND gate 702.

FIG. 8 shows data signals DATA, / D of FIG.
FIG. 3 is a circuit diagram showing a write circuit 113 that outputs ATA.

The write circuit 113 includes a NAND gate 80
1, 802 and inverters 803 to 805.

Write data signal WD is applied to one input node of NAND gate 801 via inverters 803 and 804, and inverter 8 is applied to the other input node.
05 through the inverted signal / WE of the internal write enable signal
i from the output node, and a data signal / DA
TA is output.

One input node of NAND gate 802 is supplied with write data signal WD via inverter 803, and the other input node is supplied with inverted signal / WEi of internal write enable signal WEi. A data signal DATA is output from the output node.

FIG. 9 shows the data transition detection signal DTD of FIG.
FIG. 9 is a circuit diagram showing a data detection circuit 900 that generates the data.

A data transition detection circuit (hereinafter referred to as a DTD circuit) 900 includes a write enable buffer 901, a local DTD buffer 902, and a data input buffer 1
13, a local DTD buffer 904, an OR gate 905, and a delay circuit 906.

Write enable signal W input from outside
E indicates the write enable buffer 901 and the local DTD
The signal is supplied to one input node of OR gate 905 via buffer 902. The data signal input from the outside is supplied to the data input buffer 113 and the local DTD.
The signal is supplied to the other input node of the OR gate 905 via the buffer 904. An output node of the OR gate 905 is connected to the delay circuit 906, and the data transition detection signal DTD is output from the delay circuit 906.

That is, the data transition detection signal DTD is generated based on the write enable signal WE.

FIG. 10 is a timing chart showing signals in DTD circuit 900 of FIG.

NA, NB and NC are DTD circuits 9 respectively.
The node at 00 is shown. It is assumed that a certain level of data signal / DATA is input from the outside, and then a different level of data signal DATA is input.

At this time, when write enable signal / WE input from the outside falls, a pulse is generated at node NA. When the data signal DATA is externally input, a pulse is generated at the node NB. The data transition detection signal DTD is output based on these pulses.

FIG. 11 is a timing chart for explaining precharging of bit lines by the circuits of FIGS.

At time t0, an address signal is externally input, and a write cycle starts. At time t1, a data signal of write data is input from outside. Then, at time t2
In response, a write enable signal / WE input from the outside is activated and falls, a write data signal is generated in response to the fall, and an internal write enable signal is generated based on write enable signal / WE. The signal / WEi is also generated. Then, data signal DATA is generated in response to internal write enable signal / WEi.

As described above, in the normal state where the operating voltage is high, the data transition detection signal DTD goes to L level earlier than the timing when the internal write enable signal / WEi is inactivated and rises to H level. However, when the operating voltage is low, the data transition detection signal DTD falls later than the rise of the internal write enable signal / WEi. At this time, the waveform of column select gate control signal CSGC is determined by data transition detection signal DTD, and the waveform of precharge signal PC is determined by internal write enable signal / WEi.

Therefore, internal write enable signal / WE
During the period Δt between the rise time t3 of i and the fall time t3 of the data transition detection signal DTD, both the column selection gate control signal CSGC and the precharge signal PC are at H level.
Level, and the bit line loads 25a, 25b and the column selection gates 25a, 25b are both on. The column select gates 25a and 25b are connected to the input / output line 2
9, the internal write enable signal / WEi is inactivated and rises to the H level, so that the output data signals DATA, /
DATA is at H level. Therefore, Δ
During the period t, the bit lines 20a and 20b
It is precharged by both the precharge circuit 601 including 7a and 27b and the write circuit 113.

As described above, according to the semiconductor memory device of the first embodiment of the present invention, the bit line is precharged by both the precharge circuit including the bit line load and the write circuit. It is possible to quickly recover the line voltage.

Further, since column select gate control signal CSGC and precharge signal PC are generated using data transition detection signal DTD, the column select gate is turned on after the precharge circuit starts operating, and the write operation is performed. The time for the circuit to precharge the bit line can be easily adjusted by controlling the data transition detection signal DTD.

(2) Second Embodiment A semiconductor memory device according to a second embodiment of the present invention has the same configuration as that of the semiconductor memory device according to the first embodiment in FIG.

FIG. 12 is a circuit diagram showing the inside and peripheral portions of memory cell array 107 of FIG. 1 of the semiconductor memory device according to the second embodiment of the present invention.

Referring to FIG. 12, Embodiment 2 of the present invention
In the semiconductor memory device of FIG.
3 is replaced with a signal generation circuit 1300 shown in FIG.

Signal generation circuit 700 of FIG. 7 of the first embodiment
Has been input with the internal write enable signal / WEi and the data transition detection signal DTD.
In 00, since internal write enable delay signal WEi-d obtained by delaying internal write enable signal / WEi is used, read / write circuit 113 sends internal write enable signal / WEi instead of data transition detection signal DTD. Only WEi is input.

FIG. 13 shows the signal generation circuit 1300 of FIG.
FIG. Referring to FIG. 13, in signal generation circuit 700 of FIG. 7, NAND gate 9 is provided at the other input node of NAND gate 901 and one end of NAND gate 902 instead of data transition detection signal DTD.
01 and one end of a NAND gate 902, an internal write enable delay signal WEi-d obtained by delaying the internal write enable signal / WEi is input.

FIG. 14 shows the delay signal generation circuit 14 of FIG.
It is a circuit diagram which shows 00. Referring to FIG. 14, delay signal generation circuit 1400 includes delay circuit 1303 and inverter 1
305.

Delay circuit 1303 and inverter 1305 are connected in series, and externally input write enable signal WE is supplied to write buffer 1 in read / write circuit 116.
The internal write enable signal / WEi is output via the signal generation circuit 1400 and the internal write enable delay signal WEi-d is output from the delay signal generation circuit 1400.
300 has been entered.

FIG. 15 is a timing chart for explaining precharging of bit lines by the circuits of FIGS.

Referring to FIG. 15, internal write enable signal / WEi falls in response to the fall of write enable signal WE input from the outside, and further, in response thereto, write enable delay signal WEi- d rises.

After a predetermined time, external write enable signal WE
Rises, internal write enable signal / WEi rises in response to internal write enable signal / WEi.
Δt after the rise of the internal write enable delay signal WEi-d falls.

By these signals, the precharge signal P
Even after C is activated, the column selection gate is kept conductive for a further Δt2 time. Therefore, during this Δt2, the bit line is precharged by the write circuit 113 in addition to the precharge circuit 601.

As described above, according to the semiconductor memory device of the second aspect of the present invention, similarly to the effect of the semiconductor memory device of the first aspect, both the precharge circuit including the bit line load and the write circuit are provided. Thereby, the bit line is precharged, so that the voltage of the bit line can be quickly recovered.

Since column selection gate control signal CSGC and precharge signal PC are generated using internal write enable signal / WEi, the column selection gate is turned on after the precharge circuit starts operating. By controlling the internal write enable signal / WEi, the time during which the write circuit precharges the bit line can be easily adjusted. In FIG. 13, except for the inverter 704, the same effect can be obtained by inputting to the other input node of the NAND gate 704.

(3) Third Embodiment A semiconductor memory device according to a third embodiment of the present invention has a configuration similar to that of the semiconductor memory device according to the first embodiment shown in FIG.

FIG. 16 is a circuit diagram showing the inside and peripheral portion of memory cell array 107 of FIG. 1 of the semiconductor memory device according to the third embodiment of the present invention.

Referring to FIG. 16, Embodiment 3 of the present invention
In the semiconductor memory device of FIG.
7 is replaced with a signal generation circuit 1700 shown in FIG.

Signal generation circuit 700 of FIG. 7 of the first embodiment
Has been input with the internal write enable signal / WEi and the data transition detection signal DTD.
00, only the data transition detection signal DTD is input.

FIG. 17 shows the signal generation circuit 1700 of FIG.
FIG. Referring to FIG. 17, signal generation circuit 1700 includes a NAND gate 701 and an inverter 70.
3, 1703 and a delay circuit 1701.

A column decode signal is input to one input node of NAND gate 701, a data transition detection signal DTD is input to the other input node, and its output node is connected to precharge signal PC via inverters 703 and 1703. Is output. Further, a delay circuit 1701 is connected to an output node of the inverter 703, and the delay circuit 1701
Outputs a column selection gate control signal CSGC1701.

FIG. 18 shows the signal generation circuit 1700 of FIG.
FIG. 3 is a circuit diagram showing a state in which is connected to bit lines 20a and 20b.

FIG. 19 is a timing chart for explaining the precharging of the bit lines by the circuits of FIGS.

In the write cycle period, internal write enable signal / WEi is inactivated and data transition detection signal DT
This can be applied to the case where D falls to the L level by the end of the write cycle. The data transition detection signal DTD is input to the precharge circuit 601 as the precharge signal PC, and the data transition is performed. The delay signal of the detection signal DTD is applied to the gate electrodes of the column selection gates 25a and 25b, and after writing is completed, the bit line 20 is precharged by the write circuit 113 for a predetermined period in addition to the precharge circuit.

As described above, according to the semiconductor memory device of the third aspect of the present invention, similarly to the effect of the semiconductor memory device of the first aspect, both the precharge circuit including the bit line load and the write circuit are provided. Thereby, the bit line is precharged, so that the voltage of the bit line can be quickly recovered.

Since the column selection gate control signal CSGC and the precharge signal PC are generated using the data transition detection signal DTD, the column selection gate becomes conductive after the precharge circuit starts operating, By controlling the data transition detection signal DTD, the time during which the write circuit precharges the bit line can be easily adjusted.

(4) Fourth Embodiment A semiconductor memory device according to a fourth embodiment of the present invention has the same configuration as that of the semiconductor memory device according to the first embodiment shown in FIG.

FIG. 20 is a circuit diagram showing the inside and peripheral portions of memory cell array 107 of FIG. 1 of the semiconductor memory device according to the fourth embodiment of the present invention.

The semiconductor memory device of the fourth embodiment differs from the semiconductor memory device of the third embodiment in that the signal generation circuit 1700 of FIG. 17 is replaced by a signal generation circuit 2100 of FIG.
Is replaced by

FIG. 21 is a circuit diagram showing a signal generation circuit 2100 in the semiconductor memory device according to the fourth embodiment of the present invention.

Referring to FIG. 21, signal generation circuit 2100
In the signal generation circuit 1700 of FIG. 17, the data transition detection signal DTD and the write enable signal WE input from the outside are written in the write buffer (not shown) included in the read / write control circuit 116 of FIG. ) Is replaced with the internal write enable signal WEi obtained by inputting the signal.

FIG. 22 shows the signal generation circuit 2100 of FIG.
4 is a timing chart for explaining precharging of a bit line due to the following.

Similar to the timing chart of FIG. 19 of the third embodiment, bit line load 2
Since bit line 20 is precharged by precharge circuit 601 including write circuits 7a and 27b and write circuit 113, the voltage of the bit line is quickly recovered.

As described above, according to the semiconductor memory device of the fourth aspect of the present invention, similarly to the effect of the semiconductor memory device of the third aspect, both the precharge circuit including the bit line load and the write circuit are provided. Thereby, the bit line is precharged, so that the voltage of the bit line can be quickly recovered.

Further, since column select gate control signal CSGC and precharge signal PC are generated using internal write enable signal WEi, the column select gate is turned on after the precharge circuit starts operating, and the write operation is started. By controlling the internal write enable signal WEi, the time during which the input circuit precharges the bit line can be easily adjusted.

In the first to fourth embodiments, the bit line can be adapted to the input / output line.

At this time, by precharging the input / output lines by the precharge circuit and the write circuit, the voltage of the input / output lines can be quickly recovered.

[0131]

According to the semiconductor memory device of the first aspect of the present invention, the first signal and the second signal are generated based on the write enable signal, and the second signal is generated after the end of the write cycle. The signal starts the precharging of the bit line by the precharging means, and at the same time, the precharging by the data writing means is performed for a predetermined time by the first signal, so that the bit line voltage can be quickly recovered. In addition to the above, the predetermined time during which the writing means precharges the bit line can be easily adjusted by controlling the write enable signal.

According to the semiconductor memory device of the second aspect of the present invention, in addition to the effects of the semiconductor memory device of the first aspect, based on the write enable signal and the data transition detection signal, the first and second semiconductor memory devices are provided. First and second from the AND gate
Are generated, the column selection gate is controlled by the first signal, the bit line load is controlled by the second signal, and the bit line is precharged.

According to the semiconductor memory device of the third aspect of the present invention, in addition to the effect of the semiconductor memory device of the first aspect, the first memory device can be configured based on a write enable signal and its delay signal.
And a second signal are generated. The first signal controls the column selection gate, the second signal controls the bit line load, and precharges the bit line.

According to the semiconductor memory device of the fourth aspect of the present invention, in addition to the effect of the semiconductor memory device of the first aspect, the first and the second signals are based on the data transition detection signal and its delay signal. A signal is generated, a column select gate is controlled by a first signal, and a bit line load is controlled by a second signal, thereby precharging the bit line.

According to the semiconductor memory device of the fifth aspect of the present invention, in addition to the effect of the semiconductor memory device of the first aspect, in addition to the first effect based on the write enable signal and its delay signal,
And a second signal are generated. The first signal controls the column selection gate, the second signal controls the bit line load, and precharges the bit line.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to first to fourth embodiments of the present invention.

FIG. 2 is a circuit diagram showing the inside and peripheral portions of the memory cell array of FIG. 1 according to the first embodiment of the present invention;

FIG. 3 is a circuit diagram showing a high resistance load type NMOS memory cell which is an example of the memory cell of FIG. 2;

FIG. 4 is a circuit diagram showing a CMOS memory cell as an example of the memory cell of FIG. 2;

FIG. 5 is a timing chart for explaining the operation of the circuits of FIGS.

FIG. 6 is a circuit diagram showing a bit line pair, a precharge circuit, and a column selection gate of FIG. 2;

7 is a circuit diagram showing an example of a signal generation circuit for generating a column selection gate control signal and a precharge signal of FIG.

8 is a circuit diagram showing a write circuit that outputs data signals DATA and / DATA of FIG.

FIG. 9 is a circuit diagram illustrating a data transition detection circuit that generates the data transition detection signal of FIG. 7;

FIG. 10 is a timing chart showing signals in the data transition detection circuit of FIG. 9;

FIG. 11 is a timing chart for explaining precharging of bit lines by the circuits of FIGS.

FIG. 12 is a circuit diagram showing the inside and peripheral portions of the memory cell array of FIG. 1 according to the second embodiment of the present invention;

FIG. 13 is a circuit diagram showing the signal generation circuit of FIG.

FIG. 14 is a circuit diagram showing a delay signal generation circuit of FIG.

FIG. 15 is a timing chart for explaining precharging of bit lines by the circuits of FIGS.

FIG. 16 is a circuit diagram showing the inside and peripheral portions of the memory cell array of FIG. 1 according to the third embodiment of the present invention;

FIG. 17 is a circuit diagram illustrating the signal generation circuit of FIG. 16;

18 is a circuit diagram showing a state where the signal generation circuit of FIG. 17 is connected to a bit line.

FIG. 19 is a timing chart for explaining precharging of a bit line by the circuits of FIGS. 17 and 18;

FIG. 20 is a circuit diagram showing the inside and peripheral portions of the memory cell array of FIG. 1 according to the fourth embodiment of the present invention;

21 is a circuit diagram illustrating the signal generation circuit of FIG.

FIG. 22 is a timing chart for explaining precharging of bit lines by the circuit of FIG. 21;

FIG. 23 is a circuit diagram showing a signal generation circuit for generating a column selection gate control signal in a conventional semiconductor memory device.

FIG. 24 is a circuit diagram showing peripheral portions of a precharge circuit, a column selection gate, and a precharge circuit in a conventional semiconductor memory device.

FIG. 25 shows bit lines 20a and 20b in a normal state.
6 is a timing chart showing a state of voltage recovery.

FIG. 26 is a timing chart showing how bit lines are recovered when the operating voltage is low.

FIG. 27 is a circuit diagram showing a conventional static random access memory disclosed in Japanese Patent Laying-Open No. 3-29189.

FIG. 28 is a circuit diagram showing a conventional static random access memory disclosed in Japanese Patent Application Laid-Open No. 3-29189.

FIG. 29 is a timing chart showing how a bit line is precharged by the static random access memories of FIGS. 27 and 28.

[Explanation of symbols]

100 semiconductor memory device, 113 writing circuit, 25a,
25b, 26a, 26b column select gate, 20a,
20b, 21a, 21b bit lines, 27a, 27b,
28a, 28b bit line load, 700, 1300, 1
700, 2100 signal generation circuit, 601 precharge circuit.

Claims (5)

[Claims] A memory cell; a bit line connected to the memory cell; data writing means for writing data to the memory cell in response to a first signal; and a data writing means in response to a second signal. A precharging means for precharging the bit line after the data writing by the data writing means is completed; and a data writing means activated when the data writing means writes data based on a write enable signal. Signal generating means for generating and outputting a first signal that is activated for a predetermined time continuously after the data writing is completed and a second signal that is activated after the data writing by the data writing means is completed. , Semiconductor storage devices. 2. A data transition detecting means for detecting a transition of data inputted from outside and outputting a data transition detecting signal, wherein said data writing means writes data for writing to said memory cell. A write buffer to be output; and a column selection gate connected between the write buffer and the bit line and turned on / off in response to the first signal. A bit line load connected between the power supply line and a power supply for supplying a precharge voltage in response to the second signal, wherein the signal generation means includes a first input node for selecting the bit line. A first AND gate that receives a column selection signal, receives the data transition detection signal at the other input node, and outputs the first signal; and a write enable at one input node. Le signal is input, the data transition detection signal to the other input node is input, and a second AND gate for outputting the second signal, the semiconductor memory device according to claim 1. 3. A data transition detecting means for detecting a transition of data inputted from outside and outputting a data transition detecting signal, wherein said data writing means outputs data for writing to said memory cell. And a column selection gate connected between the write buffer and the bit line and turned on / off in response to the first signal. A bit line load connected to a power supply for supplying a precharge voltage in response to the second signal, wherein the signal generating means delays the write enable signal and delays the write enable signal And a column selection signal for selecting the bit line is input to one input node, and a delay signal of the write enable signal is input to the other input node. A first AND gate that outputs the first signal; a write enable signal input to one input node; a delay signal of the write enable signal input to the other input node; 2 which outputs the second signal
2. The semiconductor memory device according to claim 1, further comprising a D gate. 4. A data transition detecting means for detecting a transition of data inputted from outside and outputting a data transition detecting signal, wherein said data writing means outputs data to be written to said memory cell. A write buffer, and a column selection gate connected between the write buffer and the bit line, which is turned on / off in response to the first signal, wherein the precharge means comprises: A bit line load connected between the power supply and a second signal to supply a precharge voltage in response to the second signal, wherein the signal generation means includes a column selection signal for selecting the bit line at one input node. A, which receives the data transition detection signal at the other input node and outputs the second signal
2. The semiconductor memory device according to claim 1, further comprising: an ND gate; and a delay unit that delays the second signal to generate the first signal. 5. A data writing means, comprising: a write buffer for outputting data to be written to the memory cell; and a data buffer connected between the write buffer and the bit line and responsive to the first signal. And a column selection gate that is turned on / off in response to the second signal. The precharge means includes a bit line load connected between the bit line and a power supply for supplying a precharge voltage in response to the second signal. The signal generating means includes a column selection signal for selecting the bit line input to one input node, the write enable signal input to the other input node, and an output of the second signal.
2. The semiconductor memory device according to claim 1, further comprising: an ND gate; and a delay unit that delays the second signal to generate the first signal.