JPH1091594A - Multiprocessor data processor and its method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To carry out the processing of continuously transferred data at high speed in parallel with plural processors while sharing a load always equally among them, by storing data of respective blocks, which are divided an allocated, in a local memory so as to process them in a desired processor. SOLUTION: In a picture processing board 104, a correlation operation with standard pictures g1 and g2 are allocated to the stored detection pictures and the correlation operation with a picture g3 is allocated to a picture processing board 105 and the correlation operation with a picture g4 to a picture processing board 106. In scheduling for deciding allocation to the respective processors in a host computer 108, not only the allocation of the processing of a detection picture 109 immediately after but also the allocation of all the processings of detection pictures 109-112 are executed. Data which are continuously acquired are divided into the plural blocks based on the characters of data and data of the respective blocks, which are allocated, are stored in the local memory in the desired processor and they are processed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus for simultaneously processing a large amount of data such as a measurement result of a high-speed measuring instrument and an image while processing the data at a high speed. Assigned to multiple processors, each processor performs data processing in parallel,
The present invention relates to a multiprocessor data processing device and method for realizing high-speed data processing.

[0002]

2. Description of the Related Art Data processing for simultaneously processing a large amount of data, such as measurement results and images of a measuring instrument, at the same time as high-speed data is described in, for example, Literature, Takanori Ninomiya: "Green Sheet Pattern High-Speed Inspection System", 1990 As in the IEICE Spring National Convention, parts requiring high speed were processed by hardware logic. Other methods include, for example, Literature, Hiroada Ueda, et al .: "Multiprocessor for Image Processing Connected by Ring Bus", 1986 IEICE General Conference,
There is a system in which a plurality of processors for performing data processing are provided and these are operated in parallel, such as a system in which a plurality of processors are connected by a ring-type shift register and operated in parallel to perform high-speed processing. The "multiprocessor for image processing connected by a ring bus" has a large number of images to be processed, and a plurality of data modes for distributing a plurality of images used for sequentially performing the same processing to different processing units. There is provided a function division mode in which the same image used for obtaining a large number of feature amounts for one image is broadcast to a plurality of processors, and each processor obtains different types of feature amounts from the same image.

[0003]

However, the technology achieved by the above-described conventional hardware logic performs processing by the hardware logic, and thus it has been difficult to flexibly cope with various processing algorithms. Generally, the data processing algorithm must be changed for each adaptation target. However, in the above-described conventional method, it is necessary to change the hardware logic every time the algorithm is changed. Was needed. Further, since a series of data includes data of various attributes, it is not possible to process each of them by a different algorithm unless a very large hardware logic is configured. Further, in an apparatus in which a plurality of processors are connected by a ring bus and operated in parallel, it is necessary to distribute the processing so that the load of each processor is equalized in order to maximize the throughput. If the processing is performed while sequentially taking in the load, it is difficult to optimize the load distribution. Conventional methods for load distribution include a static load distribution method and a dynamic load distribution method.
The static load distribution method is a method of allocating an optimum processor at the time of compiling a program. However, in this method, the types of acquired data are various, and it is not possible to cope with a case where the load varies depending on the characteristics of each data. The dynamic load distribution method includes a centralized control method and a distributed control method. In the centralized control method, there is a processor that manages the entire system, and when assigning processing based on the processor load, the physical processor is determined.This method considers the time required for the allocation processing. And it is difficult to adapt when it is essential to continuously process large amounts of data in real time. In addition, when multiple processes are continuously performed on a large amount of data, the time required for processing is generally unknown, so is it efficient to distribute multiple data blocks to different processing units? Or distribute the same data block to multiple processing units,
It has been difficult to determine whether it is better to perform different types of processing for each. For this reason, it has not been conventionally performed to optimize by dynamically changing the number of processors that process one data block by combining the above two. In the distributed control method, a random method, a threshold method,
A traveling system is known. The random method is a method of randomly assigning processes to processors, and it cannot be expected that optimal assignment can be performed. The threshold method is a method of allocating processing to a processor whose load found first is equal to or less than a certain threshold. Since this is originally an optimal method of allocating to the processor with the smallest load, it is impossible to perform optimal allocation. The cyclic method assigns a number to a processor, assigns a process to a certain processor, and then assigns a process to a processor of a number obtained by adding a certain value to the number of the processor.
This method is good when all the processing is the same and the detection of the processing data is always constant, but otherwise, the load varies and optimization cannot be achieved. As described above, it is impossible to perform load distribution optimally by the conventional method, and it is not possible to obtain performance in proportion to the number of processors.

[0004] An object of the present invention is to solve the above problems.
It is an object of the present invention to provide a multiprocessor data processing device and a method thereof, in which continuously transferred data can always be processed in parallel at high speed by a plurality of processors with the same load.

Another object of the present invention is to perform high-speed image processing in parallel on image data obtained from an object to be inspected and continuously transferred by always applying the same load to a plurality of processors. It is an object of the present invention to provide an inspection device and a method thereof that can be performed.

[0006]

In order to achieve the above object, the present invention has a plurality of processors each having a local memory, and performs processing while continuously acquiring data. In the multiprocessor data processing device, processing of each block is performed to a desired processor such that load distribution of processing in each processor is optimized for each block obtained by dividing data to be acquired into a plurality of blocks based on the nature of the data. Allocating means for allocating; dividing means for dividing continuously obtained data into a plurality of blocks based on the nature of the data; and dividing the data of each block divided by the dividing means and allocated by the allocating means into the desired data. Multiprocessor data processing apparatus storing and processing in a local memory in a processor It is. Further, the present invention provides a multiprocessor data processing device which has a plurality of processors each having a local memory and continuously processes data while acquiring the data. Processing for each block based on the expected value of the processing time required for each of the parallelizable parts in the processing on each of the blocks divided based on the plurality of blocks and the expected value of the processing time of the unprocessed data of each processor. Allocating means for allocating to a desired processor,
Dividing means for dividing continuously obtained data into a plurality of blocks on the basis of the nature of the data; and dividing the data of each block divided by the dividing means and assigned by the assigning means into a local memory in the desired processor. And a multiprocessor data processing device for processing.

According to the present invention, there is provided a multiprocessor data processing apparatus which has a plurality of processors each having a local memory and performs data processing while continuously acquiring data. The expected value of the processing time required for each of the parallelizable parts in the processing of each block divided into a plurality of blocks based on the property of the above, the expected value of the processing time of the unprocessed data of each processor, and the number of processors to be allocated Allocating means for allocating a process for each block to a desired processor based on the above, dividing means for dividing continuously obtained data into a plurality of blocks based on the nature of the data, divided by the dividing means, The data of each block allocated by the allocation means is stored in a local memory in the desired processor. Making the process Te is a multi-processor data processing apparatus according to claim. Further, the present invention is characterized in that in the multiprocessor data processing device, when allocating a process for each block to a desired processor, the allocating unit is configured to perform the process using history information of the process for each block in the processor. And Further, the present invention provides the multiprocessor data processing device, wherein the expected value of the processing time required for each of the plurality of processes that can be executed in parallel is stored in the data processing device.
The calculation is performed based on the parameters stored in the next storage device. The present invention also provides the multiprocessor data processing device, wherein the expected value of the processing time required for each of the plurality of processes that can be executed in parallel is calculated as the processing time required for processing data having the same attribute as the data to be processed in advance. It is characterized by estimating based on

The present invention also provides a multiprocessor data processing method for continuously acquiring and processing data using a plurality of processors each having a local memory. A process for each block is allocated to a desired processor so that a load distribution of a process in each processor for each block divided into a plurality of blocks based on the property is optimized, and data of each allocated block is allocated to the desired processor. A multiprocessor data processing method characterized in that a processor stores and processes in a local memory. The present invention also provides a multiprocessor data processing method for continuously acquiring and processing data using a plurality of processors each having a local memory. The processing for each block is performed based on the expected value of the processing time required for each of the parts that can be parallelized in the processing for each of the divided blocks and the expected value of the processing time of the unprocessed data of each processor. A multiprocessor data processing method, wherein the data is allocated to a desired processor, and the data of each allocated block is stored in a local memory and processed in the desired processor.

Further, the present invention provides a multiprocessor data processing method for continuously acquiring data using a plurality of processors each having a local memory and performing the processing on the acquired data. Each block based on the expected value of the processing time required for each of the parallelizable parts in the processing of each block divided into a plurality based on the property and the expected value of the processing time of the unprocessed data of each processor. Is assigned to a desired processor, and the data of each assigned block is stored in a local memory in the desired processor for processing. Further, the present invention is characterized in that, in the multiprocessor data processing method, when allocating a process for each block to a desired processor, the process is performed using history information of a process for each block in the processor. Further, the present invention provides a multiprocessor data processing device that has a local memory in each processor and performs data processing while continuously acquiring data. Calculated based on the hardware configuration and the nature of the data and the algorithm for processing the data, the time required until the end of the data processing being executed by each processor at the start of acquiring the data of the block, A part that can be parallelized in the processing on the block is specified, and an expected value of the processing time of the unprocessed data of each processor and an expected value of the processing time of each of the parts that can be parallelized in the processing on the block are also calculated. Assigning the processing of the block to a plurality or one processor, and starting the acquisition of the data of the block; To the data already characterized in that it is simultaneously transferred to the local memory of the plurality or one processor assignment of the process it has been determined.

According to the present invention, there is provided a multiprocessor data processing apparatus which continuously acquires data using a plurality of processors each having a local memory and processes the acquired data. The expected data is divided into a plurality of blocks, the expected value of the processing time required for each of the plurality of parallel executable processes to be performed on each block, and the time required for the process assigned to each processor is completed. For each of the blocks, the calculation and specification of the number of processors to which the processing is assigned is determined by the expected value of the processing time required for each of the processes that can be executed in parallel, or by the immediately preceding block. Is determined by the processing assigned to each processor and the expected value of the time required for that processing, or the hardware configuration. Dynamically calculating according to the type of data based on one or some combination of waiting times for memory access contention of the processor, which is increased by storing data in the local memory, A multiprocessor data processing apparatus, characterized in that at the same time as acquisition of data of a block is started, the data is simultaneously stored in local memories of the plurality or one of the processors for which the assignment of the processing has already been determined.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to FIGS. FIG. 1 shows an example of the overall configuration of the present invention. FIG. 1 is an overall configuration diagram of a data processing apparatus for checking whether or not a plurality of predetermined patterns exist in a detected image, and determining the positions of the patterns if they exist.
101 is an image detection sensor. Image detection sensor 1
01 is detected by the A / D converter 102
After being converted into a digital signal by the above, the digital signal is stored in the buffer 103. The digital data stored in the buffer 103 is transferred to all of the data processing processor boards 104, 105, and 106 arranged in parallel.
Each data processing processor board 104, 105, 106
Is notified from the host computer 108 via the bus 107 in advance which detection image is to be stored. Each data processing processor board 104, 105,
The image transferred to the memory 106 is stored in the memory M mounted on the boards 104, 105, and 106 only when the image has been notified from the host computer 108 to store the image in the memory M. P1, P2 in each data processing processor board 104, 105, 106
P3 indicates a processor.

Now, consider a case in which the image detection sensor 101 detects the images shown continuously 109 to 112. Each of 109 to 112 is one image,
When the detection is performed by the sensor 101, the detection is performed at a constant rate without any interruption at the boundary of the image. Each data processing processor board 104, 10
One or all of these images are stored in the local memory M on the reference numerals 5 and 106. A secondary storage device 113 is connected to the host computer 108, in which a reference pattern 114 of a detected pattern is stored.
To 117 are stored. This normative pattern 114 ~
117 is transferred to the local memory M on the data processing processor boards 104 to 106 via the bus 107 before the start of image detection. Each data processing processor board 10
4, 105, and 106, the processors P1, P
2, P3, the reference patterns (gj) 114 to 11 for each detected image (fi) stored in the local memory M.
7 is performed. When the calculations in all the data processing processor boards are combined, each detected image (fi) 109-112
, A correlation operation is performed once with reference patterns (gj) 114 to 117, respectively. Detection image 1
The images 09-112 are designated as f1, f2, f3, f4, respectively, and the reference patterns 114-117 are designated as g1, g2,
If g3 and g4 are set, each grayscale correlation operation in the processors P1 to P3 is represented by the following (Equation 1).

[0013]

(Equation 1)

Fi (x, y) indicates the gray value of the detected image at the (x, y) coordinates. Therefore, for an area (screen) where one pattern exists, x and y are changed in pixel units. fi (xm, yn) is (x,
y) Indicates the gray value of the detected image that is shifted by m pixels in the X direction and n pixels in the Y direction from the coordinates. That is, since there is a displacement between the detected image and the reference image, X
The gray-scale correlation that is most matched by shifting the pixel by m pixels in the direction and by n pixels in the Y direction is obtained by equation (1). If fi contains the same pattern as gj, the calculation result of Expression (1) becomes large. Therefore, when the grayscale correlation calculation is performed for all the reference patterns gj on the detected image fi, the maximum correlation is shown. By obtaining the reference pattern, the type of the reference pattern in the detected image can be specified. In each of the data processing processor boards 104, 105, and 106, since a correlation operation is not performed with all of the reference patterns 114 to 117, the reference pattern in the detected image cannot be specified. For this reason, each data processing processor board 104, 105, 106
After completion of the shading calculation, an identifier of a reference pattern type obtained by performing a correlation calculation on the host computer via the bus 107;
The maximum value and the coordinates at which the maximum value was obtained are notified. The host computer 108 compares, for each detected image fi, the maximum value obtained by the grayscale correlation operation with each reference pattern notified by each data processing processor board, and determines the same pattern as the reference pattern having the maximum correlation. It recognizes that it is in the image, and writes this pattern identifier and its position in the secondary storage device 113.

In order to perform high-speed data processing in the configuration shown in FIG. 1, it is necessary to optimize the assignment of the grayscale correlation calculation to the data processors P1, P2, and P3. In order to realize high-speed processing in an apparatus having a plurality of processors, it is necessary to allocate operations to the respective processors P1 to P3 so that the amount of operation in the processors becomes equal. FIG. 2 is a timing chart in the case where allocation is determined using a cyclic method that has been conventionally used. The grayscale correlation calculation with all the reference patterns of the detected image is performed with respect to the detected image 109.
The detected image 110 is stored in the image processing board 105, and the detected image 111 is stored in the image processing board 106.
In addition, the detected image 112 is assigned to the image processing board 104. As a result, the processor P2 does not perform the processing until the detection of the detection image 110 indicated by 202 ends, and the processor P3 performs the detection image 111 indicated by 203.
The processing cannot be performed until the detection of is completed. The processor P2
After completing the processing of 205 and 206 in the processor P3, the processor P1
No processing is performed while the detected image is being processed. As described above, the processing of the processor greatly varies particularly near the start of image detection and near the end of image detection, and high-speed data processing cannot be realized.

In order to avoid this, the same detected image is stored in the local memories M1 to M3 of the plurality of data processing processor boards 104 to 106, and in each of the processors P1 to P3, a gray level correlation with a different reference pattern is obtained. An operation may be performed. However, ordinary DRAM
When the local memory of the processor is configured with, the writing of the image to the memory and the reading of the image cannot be performed at the same time. The time required for processing the image is longer by that much. That is, if image processing is unnecessarily assigned to many processors, much time is required, and high-speed data processing cannot be realized.

In order to avoid these problems and to speed up data processing, it is not necessary to uniquely determine the assignment of data processing, but to assign data processing to each processor based on the data amount and processing algorithm. Needs to be optimized. This will be described with reference to FIG. 3 with respect to a timing chart when the allocation of data processing is optimized. Reference numerals 210 to 212 indicate storage of the detected image 109. Since 109 is the first image, the image processing boards 104 to 106 are not performing data processing at first. That is, even if images are stored in the local memories M1 to M3 of all the processors P1 to P3, no memory access conflict occurs and the image processing time does not increase. The image processing board 104 allocates a correlation calculation between the reference images g1 and g2 to the stored detected image, the image processing board 105 allocates a correlation calculation with g3, and the image processing board 106 allocates a correlation calculation with g4. . Since the processing in the processor P1 is twice as large as the calculation amount of the processors P2 and P3, the end timing of the processing in the processor P1 is different from the timing of the processing in the processors P2 and P3. Even if the processors P2 and P3 perform the processing while storing the detected images 216 and 217 in the memories M2 and M3, the processing indicated by 214 and 215 near the transfer end timing of the next detected image 110 to the memories M2 and M3. Has ended. For this reason, since the processing can be started only after the transfer of the image is completed, if the processing of the detected image 110 is not assigned, the transfer of the detected image 111 is completed after the transfer of the detected image 110 is completed. Until the processing, the processors P2 and P3 do not perform any processing. Since this wasted time is longer than the processing time that is increased by storing the image, the processor P2
Even if processing is assigned to P3 and P3, and the processing time increases for storing images, no time is lost as a whole. However, as indicated by 213 in the processor P1, the processing on the detected image 109 takes place after the transfer end timing of the detected image 111, so that the image cannot be stored in a time when the processor is idle. Therefore, no process is assigned to the processor P1.

As described above, in order to optimally allocate data processing, each processor P at the start of data storage is required.
It is necessary to determine the amount of unexecuted data processing in 1 to P3 and determine the assignment based on this. However,
If the detection of the image from the sensor 101 is performed continuously and there is no time interval between the end of the detection of the image and the start of the detection of the next image, after the transfer of one image is completed, the operation is being performed at that time And the time it takes to complete it, and then determine the assignment of processing to each processor,
There is a possibility that the allocation decision cannot be made in time for the start of the transfer of the next image. For this reason, the host computer 10
In the scheduling 209 for determining the assignment to each processor in 8, not only the assignment of the process of the detected image 109 immediately after that, but also the assignment of all the processes of the detected images 109 to 112 is performed. In order to perform scheduling in advance, it is necessary to obtain an expected value of a time expected for processing already assigned by each processor at the start of transfer of each detected image based on the type of data and algorithm. Here, since the processing performed in each processor is all grayscale correlation, the processing time can be estimated from the product of the processing time required for grayscale correlation with one reference pattern and the number of reference patterns assigned to each processor. It is also possible to estimate the data processing time which is increased due to contention for access to the memory when the transfer to the memory is performed by the hardware configuration.

FIG. 4 shows an assignment algorithm executed by the host computer 108. First, the amount of unexecuted processing of the processor at the start of transfer of the target image i is checked. .., Ptn, and the results obtained by sorting the estimated values of the time required to execute the processing already allocated in each processor in ascending order are Ptmin1, Ptmin2,. ,
Ptminn. That is, “mini” indicates the number of the processor that is expected to end the already assigned process at the i-th position. Next, the process of the image i is decomposed into a plurality of processes that can be executed in parallel.
1, C2,..., Cl. Next, when the expected value Dti of the time required for the processor P to transfer the image i to the memory M is subtracted from the expected storage end time of the image i + 1, it is expected that all the data processing is completed. Processors Pmin1, Pmin2,.
· Find Pminm. If the image i is the last captured image, m = n is set. And C1, C2, ...,
For all combinations that are divided into sets of the number m of processors that are candidates for assigning the Cl process, the combinations of this set are represented by (F1, min1, F1, min2,..., F1, minm), (F2, min1, F2 , min2, ..., F2, minm), ...
, (Fc, min1, Fc, min2,..., Fc, minm), and the variable h is determined so that the maximum value of the following expected value when the variable k is changed is minimized. (Fh, min
, Fh, min2,..., Fh, minm) are assigned to the processors min1, min2,. Here, k is an integer from 1 to m, and h is an integer from 1 to c. Next, is there a processor that is expected to complete all data processing? And all the processing
Assign to min1. The above-described decomposition into the processes that can be executed in parallel and the calculation of the expected value of the processing time do not need to be performed at the time of performing the scheduling in particular.
It may be stored in the secondary storage device 113.

In the case of the embodiment shown in FIG. 1, the number of processors n is 3, and the processing of each detected image is considered to be capable of decomposing the gray-scale correlation operation for each reference pattern. l becomes 4. The expected value of the processing time is set to C since the expected values of the processing time are the same because the same grayscale calculation is performed. The images are referred to as image 1, image 2,... In the order of detection. Detection image 1
09, that is, at the transfer start timing of image 1, there is no process performed before that, so that Pt1 = Pt2 = P
t3 = 0. The time required until the processing of the image 1 performed by each processor at the transfer start timing of the image 2 is calculated by the following Expressions (2) and (3).

Pt1 = 2C (Equation 2) Pt2 = Pt3 = C (Equation 3) Next, the image i is stored in the memory at the estimated end time of the process being executed already allocated at the time of starting the storage of the image i. In this case, the timing obtained by adding the processing time increased due to the contention of the memory access is compared with the image storage end timing of the image i + 1. If the former timing is earlier, it is determined as a candidate for the processor to which the processing of the image i is assigned. That is, if the former timing is earlier, the time estimated that the processor does not perform any processing when the image i is not allocated exceeds the processing time increased by storing the image. Can be executed more efficiently. This is shown in FIG.
This will be described with reference to FIG. The processing to be performed up to the image i-1 is shown by 901 in the timing chart of FIG. Image i +
The process 1 can be started after the transfer of the image i + 1 is completed, as shown at 902. Therefore, a section in which the processor does not perform processing when the processing of the image i is not assigned to this processor is indicated by 903. Next, considering the case where the processing of the image i is assigned, the image processing is performed during the transfer of the image i, and the processing time 904 that increases due to memory access competition that occurs when the image is stored in the memory is considered. There is a need. 903 hours and 9
If the time of 903 is longer than the time of 04,
Image i +, which is the start timing of the processing of image i + 1
Since the storage of the image i and the start of the processing can be performed before the transfer end timing of 1, the processing time can be reduced. However, if i is the last image, it is impossible to assign the next image, so all processors are candidates for assignment. The processing time that increases due to memory access competition is Dt, and the time from the start of transfer of one image to the end of transfer is Tr. In the first embodiment, when determining the assignment of the processing of the detected image 110, that is, the image 2, the comparison between the processors is as follows.

The reference of each timing is defined as a transfer start timing 219 of 110 (Equation 4) shown below.
Equation 5 is obtained. P1: 2C + Dt> 2Tr (Equation 4) P2, P3: C + Dt <2Tr (Equation 5) Therefore, P2 and P3 are selected as the allocation candidates for the processing of the image 2.

Next, it is determined which process is to be assigned to a processor which is a candidate for assigning an image process. M is the number of processors that are candidates for assigning processing.
Then, a combination that divides the processes that can be divided into one or a plurality to form a group of m is obtained. This j-th combination is represented by (F (j, min1), F (j, min
2),..., F (j, min m)) and F (j, mi)
Let n k) be a candidate for a group of processes to be assigned to the processor min k. When the processing which is an element of F (j, min k) is assigned to the processor min k, the time required for the processing to be completed is obtained. It is estimated. This is performed for all the combinations, the combination whose processing is completed earliest is obtained, and the processing of the image indicated by this combination is assigned. FIG.
In the allocation of the detected image 110 in the embodiment, m = 2 because only P2 and P3 are candidates to be allocated. At the start of the transfer of the detected image 110, Pt2 and Pt3 are equal, but here, for convenience of explanation, it is assumed that min1 = 2 and min2 = 3. Since the processing is decomposed into four, it is determined whether each of the four processings is processed by P2 or P3.
As you can imagine. Now, the reference patterns 114 and 11
5, 116, and 117 as processing 1, processing 2, processing 3, and processing 4, respectively, as F (1,
2) Assume that F (1,3) is determined.

F (1, 2) = {Process 1, Process 2, Process 3} F (1, 3) = {Process 4} At this time, the time required for the process of F (1, 2) is 3C, F
The time required for the processing of (1, 3) is C. Detection image 1
The value obtained by adding this to Pt2 and Pt3 at the transfer start time of No. 10 is the time required for each processor to complete the processing when this allocation is performed, and is expressed by the following equations (6) and (7). It becomes the relation of the expression. P2: 4C (Equation 6) P3: 2C (Equation 7) Accordingly, the detected image 11 in the first combination is obtained.
The end timing of the process of 0 is 4C based on the transfer start timing of the detected image 110. Next, F (2,
Suppose that 2) and F (2,3) are as follows. F (2,2) = {Process 1, Process 2} F (2,3) = {Process 3, Process 4} At this time, the time required for the end of the process for both P2 and P3 is 3C, and the end timing is the first. Faster than combination.

FIG. 5 is a block diagram showing a specific embodiment of the data processor boards 104 to 106 shown in FIG. The processor board is configured by 402 to 406. Reference numeral 401 denotes a buffer.
Same as 3. The buffer 401 has a capacity of one line of an image, and when an image of one line is transferred from the sensor, each of the processor boards 104 to
A signal indicating buffer full is sent to 6. The processor boards 104 to 106 read data transferred from the buffer 401 by the DMA 402 mounted on the board and store the data in the local memory 403 only when the processor board 104 to 106 is assigned to process the image data. C
The PU 404 accesses the local memory 403 via the cache 404. For this reason, the CPU does not always need to access the memory 403.
Even while the image is stored in the memory 403, the CPU
Data processing at 405 is not significantly affected.
Reference numeral 406 denotes a dual port memory, which is used to exchange data with the host computer 108 via the bus 407. By using the dual port memory 406, access competition between the CPU 404 and the host computer 406 can be reduced.

FIG. 6 is a timing chart in the case of adapting to an image of a type different from that shown in FIG. The images 501 to 504 are images to be detected. A plurality of patterns exist in one image, and the approximate position of each pattern and the type of the pattern are known in advance.
In order to identify the position of each pattern in the image, the processor sets an image processing window, which is an area where image processing is performed, based on the approximate position of the pattern, and calculates a gray level correlation with a reference pattern already known in this area. I do. Therefore, it is not necessary to perform a correlation operation on a single pattern with a plurality of reference patterns, and it is impossible to decompose the pattern into a plurality of parallel processes such as the process in FIG. The processing of the plurality of image processing windows therein can be assigned to different processors. The timing chart at this time is shown in FIG.
Shown in

The same scheduling algorithm 601 as that shown in FIG. 4 is used. Although the image processing operation used here is represented by the above (Equation 1), unlike the embodiment shown in FIG. 1, the correlation operation only needs to be performed with the image in the image processing window. , Processing time is reduced. Since the image processing windows are not always the same, the calculation time differs for each image processing window. Even in such a case, in order to accurately estimate the processing time, the processing algorithm stored in the secondary storage device 113 describes only the time required for the correlation operation of a certain unit image. Based on the stored time, the size of the image processing window, and the size of the reference pattern, the processing time required for each assigned process is calculated. After the first scheduling, the detection of the image is started. The image 501 is stored in the local memories of P1 and P2, and the correlation calculation of the square pattern is performed at P1 and the correlation calculation with the triangular pattern is performed at P2. Since each of the subsequent images 502 to 504 has three patterns in one image, the images are stored in the local memory 403 of all the processors P1 to P3, and each processor has one pattern. Perform correlation calculation.

In the timing chart shown in FIG. 7, all scheduling is performed before the start of continuous image detection, but the processing performed by the processor does not always match the expected value. Therefore, the difference between the actual processing time and the expected value is required before the end of image processing being executed in each processor at the start of image storage after many continuous image detections have been performed. The estimated time can be very different from the actual one. FIG. 8 is a timing chart for avoiding this. Here, processor assignment scheduling is performed not only before the start of detection of continuous data but also after the start of detection. Each processor checks which line of the image is being transferred at the time when the processing assigned to each processor is completed, and writes the image and the assigned processing identifier into the dual port memory 406. Scheduling is performed by the host computer 108.
Based on this, the end timing of the processing already allocated is calculated, the time required for the end of the processing being executed by each processor at the start of storing the target image is estimated, and the allocation is determined based on this. I do. If this scheduling is performed immediately after the storage of the image immediately before the target image is completed, the scheduling is not completed before the transfer of the image is started. Therefore, the scheduling is performed after the transfer of the image two before is completed.

Based on the end timing of the process written in the dual port memory 406, the time required for the process can be calculated. The obtained time can be used for the subsequent scheduling decision, so that appropriate scheduling can be performed.
Also, by storing this in the secondary storage for each type of processing, this is stored, and more appropriate scheduling can be performed for different image patterns, or the operator has performed appropriate scheduling. It is possible to make it easy to check whether or not.

Next, a description will be given of scheduling in a case where a plurality of image groups detected at similar timings are repeatedly processed. Again, as shown in FIG. 3, a case is considered in which scheduling is performed on all continuously detected images immediately before the start of continuous image detection. The reference patterns 114 to 117 shown in FIG.
1 to 804 are continuously processed in the same manner as 109 to 113 shown in FIG. 1, and after a long interval, 805 to 808 are detected. Although the order in which the patterns appear in 801 to 804 and 805 to 808 is different, the same number of images are processed. At this time, the optimal scheduling when processing 801 to 804 is also the optimal scheduling when processing 805 to 808. As described above, when it is known that the detection and processing of the image at the same timing are repeated and the processing is performed a very large number of times, when the allocation of the processing is calculated for each image, 20 shown in FIG.
9, the processing time is unnecessarily long. In such a case, scheduling is performed in advance, and the secondary storage device 113 shown in FIG. 1 stores the identifier of the processor assigned to the processing of each image. By using the stored assignment result, it is not necessary to perform scheduling every time, and the processing time can be reduced.

[0031]

According to the present invention, it is possible to always apply the same load to all the processors under the constraint that the processing is performed in real time in the multi-processing data processor. It is possible to construct a system that maximizes the performance of the system.

[Brief description of the drawings]

FIG. 1 is a simplified configuration diagram of a main part showing an embodiment of a multiprocessor data processing device according to the present invention.

FIG. 2 is a diagram showing a timing chart in a case where processing assignment is determined for each detected image according to the present invention.

FIG. 3 is a diagram showing a timing chart when optimizing the allocation of processing according to the present invention.

FIG. 4 is a diagram showing one embodiment of a scheduling algorithm in the multiprocessor data processing device according to the present invention.

FIG. 5 is a simplified configuration diagram of a main part showing an embodiment of a processing unit in the multiprocessor data processing device according to the present invention.

FIG. 6 is a diagram showing an example of an image to be processed in the multiprocessor data processing device according to the present invention.

FIG. 7 is a diagram showing one embodiment of a timing chart in the multiprocessor data processing device according to the present invention.

FIG. 8 is a diagram showing another embodiment of the timing chart in the multiprocessor data processing device according to the present invention.

FIG. 9 is a diagram showing an image pattern different from that of FIG. 1 processed in the multiprocessor data processing device according to the present invention.

FIG. 10 is a diagram showing a timing chart in which a processing time is reduced in the multiprocessor data processing device according to the present invention.

[Explanation of symbols]

101: Image detection sensor, 102: A / D converter, 103, 401: Buffer, 104: Processing unit 1, 105: Processing unit 2, 1
06 processing units 3, 107, 407 bus, 108 host computer, 109 first detected image, 110 second detected image, 111 third detected image, 112 fourth image Detection image, 113 secondary storage device, 114 reference pattern 1, 115 reference pattern 2, 116 reference pattern 3, 117 reference pattern 4, 402 DMA, 403, M1 to M3 local memory, 404 cache , 405 ... CPU, 406 ...
Dual port memory, P1 to P3 ... Processor

Claims (8)

[Claims] 1. A multiprocessor data processing device having a plurality of processors each having a local memory and performing data processing while continuously acquiring data, wherein the data to be acquired is adapted to the nature of the data. Allocating means for allocating processing to each block to a desired processor so that load distribution of processing in each processor to each of the blocks divided into a plurality of blocks is optimized, Dividing means for dividing the data into a plurality of blocks based on the data, and storing the data of each block divided by the dividing means and assigned by the assigning means in a local memory in the desired processor for processing. Multiprocessor data processing device. 2. A multiprocessor data processing apparatus having a plurality of processors each having a local memory and performing data processing while continuously acquiring data. Processing for each block based on the expected value of the processing time required for each of the parallelizable parts in the processing on each of the blocks divided based on the plurality of blocks and the expected value of the processing time of the unprocessed data of each processor. Allocating means for allocating to a desired processor, and dividing means for dividing continuously obtained data into a plurality of blocks based on the nature of the data,
A multiprocessor data processing apparatus, wherein the data of each block divided by the dividing means and allocated by the allocating means is stored in a local memory and processed in the desired processor. 3. A multiprocessor data processing apparatus having a plurality of processors each having a local memory and performing data processing while continuously acquiring data, wherein the data to be acquired is adapted to the nature of the data. Based on the expected value of the processing time required for each of the parts that can be parallelized in the processing of each of the blocks divided based on the plurality of blocks, the expected value of the processing time of the unprocessed data of each processor, and the number of processors to be allocated. Allocating means for allocating the processing for each block to a desired processor, dividing means for dividing continuously obtained data into a plurality of blocks based on the nature of the data, The data of each block allocated by (1) is stored in a local memory in the desired processor and processed. A multiprocessor data processing device, characterized in that: 4. The processor according to claim 2, wherein the assigning means assigns a process to each block to a desired processor by using history information of the process to each block in the processor. Multiprocessor data processing device. 5. A multiprocessor data processing method for continuously acquiring data using a plurality of processors each having a local memory and processing the acquired data, wherein the data to be acquired is determined based on the nature of the data. The processing for each block is allocated to a desired processor so that the load distribution of the processing in each processor for each of the divided blocks is optimized, and the data of each allocated block is locally stored in the desired processor. A multiprocessor data processing method, wherein the method is stored in a memory and processed. 6. A multiprocessor data processing method for continuously acquiring data using a plurality of processors each having a local memory and processing the acquired data, wherein the data to be acquired is based on the nature of the data. The processing for each block is performed based on the expected value of the processing time required for each of the parts that can be parallelized in the processing for each of the divided blocks and the expected value of the processing time of the unprocessed data of each processor. A multiprocessor data processing method, wherein data is allocated to a desired processor, and the data of each allocated block is stored in a local memory in the desired processor for processing. 7. A multiprocessor data processing method for continuously acquiring data using a plurality of processors each having a local memory and processing the acquired data. The processing for each block is performed based on the expected value of the processing time required for each of the parts that can be parallelized in the processing for each of the divided blocks and the expected value of the processing time of the unprocessed data of each processor. A multiprocessor data processing method, wherein data is allocated to a desired processor, and the data of each allocated block is stored in a local memory in the desired processor for processing. 8. The multiprocessor data processing method according to claim 6, wherein when assigning the processing for each block to a desired processor, the processing is performed using history information of the processing for each block in the processor.