JPH1083971A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the junction leaking current when a CoSix film is used for an electrode, by depositing a cobalt layer on a substrate having a silicon- exposed region, forming a cobalt silicide film by heating to a specified temperature, and converting the film into the cobalt silicide film comprising the second phase by heating the film to the second temperature. SOLUTION: A gate insulating film on a source/drain diffusing layer 28 having an LDD structure is etched, and the source/drain diffusing layer 28 is exposed. A Co film 30 and a TiN film 32 are continuously formed. Thereafter, heat treatment is performed under the temperature condition of 300 deg.-390 deg.C. A CoSix film 34 is formed on the interface of Co/Si on the exposed source/drain diffusing layer 28 and on a gate electrode. Then, the heat treatment in the short time is performed under the temperature condition of, e.g. 500 deg.-900 deg.C. The selectively formed CoSix film is converted from a Co2 Si phase to a CoSi2 phase under the uniform state, so as to obtain the CoSi2 film having the specific resistance sufficient for use for electrode material.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for forming an electrode in a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device using CoSi _x (cobalt silicide) as an electrode material.

[0002]

2. Description of the Related Art Refractory metal silicides are widely used as contact materials for semiconductor devices, gate electrodes, wirings and the like. In particular, CoSi _x (cobalt silicide) has been used more frequently than before because it has a low resistivity at room temperature of 15 to 30 μΩcm and is thermally and chemically stable.

A typical manufacturing process of a semiconductor device using CoSi _X is a so-called salicide (self-aligned silicide: self-aligned silicide) in which a silicide film is selectively formed on a gate electrode and a source / drain diffusion layer of a MOSFET.
Self-Aligned Silicide) processes are known. Hereinafter, a conventional salicide process using CoSi _X will be described.

First, a MOS transistor having a source / drain diffusion layer and a gate electrode, with the side wall of the gate electrode covered by a side wall, is formed in the same manner as in a normal MOS transistor manufacturing method. Next, a Co (cobalt) film and a TiN (titanium nitride) film are successively deposited on the entire surface. In a region where the element isolation film and the side wall are not formed, the gate electrode and the source / drain diffusion layers come into direct contact with the Co film.

Subsequently, short-time annealing is performed at a temperature of about 550 ° C. for about 30 seconds. By this annealing, a silicidation reaction occurs on the gate electrode and the source / drain diffusion layers where silicon is exposed, but no silicidation reaction occurs on the element isolation film made of a silicon oxide film and the sidewalls. A CoSi _x film is selectively formed only on the gate electrode and the source / drain diffusion layers.

Thereafter, the unreacted Co film and TiN film are removed.
On the gate electrode and the source / drain diffusion layer.
Only CoSi_XLeave the membrane. Then, at a temperature of about 830 ° C
Short annealing for about 30 seconds is performed, and CoSi _XLow membrane
Resistance. Thus, on the gate electrode and on the source
/ CoSi selectively only on the diffusion layer_XFilm formed
It had been.

[0007]

However, in the above-described conventional method for manufacturing a semiconductor device, the junction leakage current at the pn junction below the source / drain diffusion layers may increase, and the transistor characteristics may be degraded. The mechanism by which the junction leakage current increases at the pn junction immediately below the CoSi _X film has not been elucidated, and a method of manufacturing a semiconductor device capable of reducing the leakage current has been desired.

An object of the present invention is to provide a method of manufacturing a semiconductor device using a CoSi _X film as an electrode material, which can reduce junction leakage current.

[0009]

The object of the present invention is to provide a cobalt film depositing step of depositing a cobalt film on a base substrate having a region where silicon is exposed, and a method of forming a first base film having a temperature higher than 300 ° C. and lower than 390 ° C. A first heat treatment step of forming a first cobalt silicide film of a first phase by heating at a temperature of 2 to cause the silicon and the cobalt film to react with each other; A second heat treatment step of heating at a temperature and transferring to a second cobalt silicide film composed of a second phase. By manufacturing a semiconductor device in this manner, spikes can be prevented from occurring during the silicidation reaction process, so that the junction leakage current does not increase even when a pn junction is formed immediately below the cobalt silicide film. .

In the above-described method for manufacturing a semiconductor device, it is preferable that the first heat treatment step is performed to increase the temperature to the first temperature at a rate lower than 100 ° C./min. When the semiconductor device is manufactured in this manner, the silicidation reaction can be made uniform, so that a cobalt silicide film can be formed without increasing the junction leakage current.

In the above-described method of manufacturing a semiconductor device, it is preferable that in the first heat treatment step, heat treatment is performed at the first temperature for 1 to 3 hours. In the method for manufacturing a semiconductor device, the second temperature may be 5
Desirably, the temperature is between 00 and 900C. When the semiconductor device is manufactured in this manner, the phase can be transferred to the low-resistance cobalt silicide without increasing the junction leak current.

In the above-described method for manufacturing a semiconductor device, it is preferable that in the second heat treatment step, the temperature is raised to the second temperature at a speed higher than 50 ° C./sec.
When the semiconductor device is manufactured in this manner, no spike occurs in the silicidation reaction process, so that the cobalt silicide film can be formed without increasing the junction leak current.

[0013]

Embodiments of the present invention will be described below in detail. As described above, in the conventional method for manufacturing a semiconductor device, a CoSi _x film is selectively formed by a two-stage heat treatment. In the first-stage annealing, it is necessary to cause a silicidation reaction only on the gate electrode and the source / drain diffusion layers, and not to cause a silicidation reaction on the element isolation film and the sidewall. For this reason, the first-stage annealing has been performed at a relatively low temperature at which the silicon oxide film and the cobalt film constituting the element isolation film and the sidewall do not react with each other.

However, Co formed at a low temperature in this manner.
Si _X has a high specific resistance, undesirable as an electrode material of a semiconductor device. Therefore, performing a second-stage high-temperature annealing after selectively forming the CoSi _X film, CoSi _X
Resistance was reduced. Conventionally, a CoSi _X film was formed in a self-aligned manner by such a method, but the electrical characteristics of a pn junction using the CoSi _X film as an electrode were not desirable.

The electrical characteristics of an n ⁺ p junction using a CoSi _X film formed under conventional typical annealing conditions as an electrode are as follows:
This will be described with reference to FIGS. 9 and 10 (see Comparative Example 4). FIG. 9 and FIG. 10 are plots of the reverse leakage current when a voltage is applied to the n ⁺ p junction formed immediately below the CoSi _x film using the cumulative distribution function. The cumulative distribution function is a method often used for reliability evaluation, and indicates that the characteristics are more stable as the slope of the plot is larger and the variation is smaller.

FIG. 9 shows I- after the first stage annealing.
FIG. 10 is a cumulative distribution function showing the IV characteristic after the second stage annealing. In each diagram (a), when a voltage of 2 V is applied,
(B) is a case where a voltage of 5V is applied. In the drawing, the mark ○ indicates the case where the electrode area is 80 × 80 μm ² , the mark □ indicates the case where the electrode area is 320 × 320 μm ² , and the mark Δ indicates the case where the electrode area is 1280 × 1280 μm ² .

As shown in the figure, although the leakage current is slightly reduced by the annealing in the second stage, the variation in the current value is large in any case, and the IV of the n ⁺ p junction immediately below the CoSi _x film is large. It turns out that the characteristic is bad. Such characteristics are not desirable for use as a source / drain diffusion layer of a MOS transistor because the current value is required to be substantially constant and the leakage current is small.

The present inventors conducted a first-stage annealing to remove the unreacted cobalt film and the TiN film in order to investigate the cause of the variation in the pn junction current immediately below the CoSi _x film. And the pattern of the CoSi _X film after the annealing in the second stage is performed by a transmission electron microscope (TE).
M: Transmission Electron Microscope).

As a result, icicle-like spikes having a length of about 50 to 100 nm and a thickness of about 10 nm were observed in some places in the sample after the first stage annealing. Although almost no spike was observed in the sample after the second stage annealing, the improvement of the leak characteristics was not sufficient, and it is considered that the spike caused the leak current at the junction.
Next, the cause of spike generation will be considered.

CoSi _X includes Co ₂ Si, CoSi, C
There are three phases of oSi ₂ . In the Co / Si solid phase reaction process, first, Co ₂ Si is formed, and then CoS is formed.
i, followed by a phase transition to the final phase, CoSi ₂ . Among these phase transition processes, Co is the main diffusion species in the reaction process of transition from Co to Co ₂ Si and the reaction process of transition from Co ₂ Si to CoSi, and Si is the main diffusion species in the reaction process of transition from CoSi to CoSi _2. It is a diffuse species.

In general, in the Co / Si-based solid-state reaction process when the Co film is relatively thick, for example, about 0.1 μm or more, and the heating rate is as slow as 100 ° C./min or less, first, Co / Si is used.
Co ₂ Si is formed in a layer at the Si interface and grows almost uniformly, then CoSi is formed in a layer at the Co ₂ Si / Si interface and grows almost uniformly, and then CoSi ₂ is formed at the CoSi / Si interface. It is formed in layers and grows almost uniformly.
Therefore, no spike occurs at the CoSi _x / Si interface, and good electrical characteristics can be obtained.

However, in a normal salicide process, short-time annealing at a high temperature rising rate is generally used, and the thickness of the Co film is as thin as about 10 nm.
The reaction mode is different from the case where the Co film is thick. As a result, in the first heat treatment, Co ₂ Si and Co
Si will be mixed without being formed in a layered form. As a result of intensive studies by the present inventors, Co ₂ Si and CoS
It has been found that the occurrence of spikes is caused by the fact that i is mixed without being layered, especially when the CoSi phase occupies the silicide layer. CoSi
It is not clear why spikes are likely to occur when the phase occupies the silicide layer, but the diffusion species in the silicidation reaction when the CoSi phase is formed is C
It is thought to be related to being o.

From the above observation, it is important to suppress the formation of a CoSi phase which has a strong correlation with the occurrence of spikes in the first-stage annealing, and it is necessary to form a reaction layer in which the Co ₂ Si phase is dominant. It turned out that there was. In order to obtain such a reaction layer, the temperature is raised sufficiently and the annealing temperature is further lowered to form a layer of Co ₂ Si at the Co / Si interface, and the reaction proceeds almost uniformly. It is desirable.

Specifically, it is desirable to raise the temperature at a rate lower than 100 ° C. per minute and to anneal at a temperature higher than 300 ° C. and lower than 390 ° C. Heating rate of 100 ℃ per minute
When the annealing temperature is set higher than 390 ° C., Co ₂ Si and CoSi are mixed in the reaction layer, which is not desirable (see Comparative Example 2). When the annealing temperature is set lower than 300 ° C., Co and Si do not react. This is because (see Comparative Example 1). The annealing time is desirably set to about 1 to 3 hours.

On the other hand, in the second stage annealing, Co ₂ S
During the transition process from the i-phase to the CoSi ₂ phase, CoSi
It is desirable to minimize the time through the phases. By doing so, the generation of spikes at the interface can be reduced. Therefore, short-time annealing at a high temperature is suitable for the second-stage annealing (see Comparative Example 3).
Specifically, it is desirable to perform short-time annealing at a rate of temperature rise of 50 ° C./sec or more and a heat treatment temperature of about 500 to 900 ° C.

By such two-step annealing, Co
By forming the Si _x film, it is possible to prevent spikes from occurring in the silicidation reaction process, so that the junction leakage current does not increase even when there is a pn junction immediately below the silicide layer. Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS.

FIGS. 1 and 2 are sectional views showing the steps of the method for fabricating the semiconductor device according to the present embodiment. In this embodiment, an N-channel MOSFET including a salicide process is used.
An example in which the method for manufacturing a semiconductor device according to the present invention is applied to the method for manufacturing a semiconductor device described above. First, the p-type silicon substrate 10 is thermally oxidized to form a pad oxide film 12 having a thickness of about 3 nm on the surface.

Next, a CVD is performed on the pad oxide film 12.
A silicon nitride film 14 having a thickness of about 100 nm is deposited by a (Chemical Vapor Deposition) method.
Subsequently, the silicon nitride film 14 is patterned so as to leave the silicon nitride film 14 in a region where an element is to be formed (FIG. 1A). Thereafter, the silicon substrate 10 is thermally oxidized using the silicon nitride film 14 as a mask to form an element isolation film 16 having a thickness of about 250 nm.

Next, after the silicon nitride film 14 and the pad oxide film 12 are removed by etching, the surface is thermally oxidized again to form a gate insulating film 18 having a thickness of about 5 nm in the device region defined by the device isolation film 16. (Figure 1
(B)). Subsequently, an amorphous silicon film having a thickness of about 200 nm is deposited on the gate insulating film 18 by the CVD method.

Thereafter, P is added to the amorphous silicon film.
(Phosphorus) ions at an acceleration energy of 20 keV and a dose of 4
Ion implantation is performed under the condition of × 10 ¹⁵ cm ^-2 . Next, the amorphous silicon film doped with P is patterned to form a gate electrode 20 made of the amorphous silicon film. Subsequently, ion implantation is performed using the gate electrode 20 as a mask to form a high resistance region 22 having an LDD (Lightly Doped Drain) structure. For example, As (arsenic) ions are accelerated at an energy of 10 keV and a dose of 3 × 10 ¹³ cm.
Ion implantation is performed under the condition of ^-2 .

Thereafter, the film thickness is about 150 nm by the CVD method.
Is deposited. For example, a film is formed by using SiH ₂ Cl ₂ and N ₂ O as source gases and setting the substrate temperature to 800 ° C. Next, the silicon oxide film is anisotropically etched by RIE (Reactive Ion Etching) to form a sidewall 24 on the side wall of the gate electrode 20.

Subsequently, ion implantation is performed using the gate electrode 20 and the side walls 24 as a mask to form a low resistance region 26 having an LDD structure. For example, As ions are implanted under the conditions of an acceleration energy of 40 keV and a dose of 2 × 10 ¹⁵ cm ⁻² (FIG. 1D). Thereafter, a rapid heat treatment at 1000 ° C. for 10 seconds is performed in a nitrogen atmosphere to activate the ion-implanted As, thereby forming a source / drain diffusion layer 28 having an LDD structure.

Next, the gate insulating film 18 extending on the source / drain diffusion layer 28 is etched to expose the source / drain diffusion layer 28 on the surface. Then, about 1
0 nm Co film 30 and TiN film 32 having a thickness of about 30 nm
Are continuously formed in the same chamber. Co film 3
The 0 and TiN films 32 are deposited by, for example, a sputtering method (FIG. 2A).

Thereafter, a first stage heat treatment for forming a CoSi _X film is performed. For example, the temperature is increased at a rate of 2 ° C./min, and annealing is performed at a temperature of 350 ° C. for 2 hours. In the first stage heat treatment, it is desirable to set the heating rate to 100 ° C./min or less, set the heat treatment temperature to a temperature higher than 300 ° C. and lower than 390, and perform annealing for 1 to 3 hours.

By this heat treatment, Co / Si on the exposed source / drain diffusion layer 28 and on the gate electrode 20 is removed.
A silicidation reaction occurs at the interface, and a CoSi _x film 34 is selectively formed in this region (FIG. 2B). The CoSi _X film 34 thus formed has a uniform Co ₂ Si phase. Next, the Co film and the TiN film that have not reacted in the first stage heat treatment are removed by wet etching. For example, etching is performed at a liquid temperature of 70 ° C. for 20 minutes using an etching solution in which H ₂ SO ₄ and H ₂ O ₂ are mixed at a ratio of 3: 1.

Subsequently, a second heat treatment for forming a CoSi _X film is performed. For example, short-time annealing at 830 ° C. for 30 seconds is performed in an Ar (argon) atmosphere (FIG. 2).
(C)). In the heat treatment of the second stage, the temperature raising rate is 50 ° C.
It is desirable to set the heat treatment temperature to a temperature of about 500 to 900 ° C. at a rate of not less than / sec. By this heat treatment, the selectively formed CoSi _X film undergoes a phase transition from the Co ₂ Si phase to the CoSi ₂ phase while remaining uniform, and becomes a CoSi ₂ film having a specific resistance sufficient for use as an electrode material. By forming a CoSi _X film by a two-stage heat treatment, no spikes are generated in the silicidation reaction process.
Even when a CoSi _X film is formed on the junction, the junction leakage current does not increase.

As described above, according to the present embodiment, the CoS is formed under the condition that no spike occurs in the silicidation reaction process.
Since forming the i _X film, it is possible to prevent an increase in junction leakage current in a semiconductor device having a pn junction just below the silicide layer. In the above embodiment, CoSi
_Although the case where the _X film is formed by the salicide process has been described, the present invention is not limited to the above embodiment. The present invention provides a solid-phase reaction between Si and Co.
The present invention can be widely applied to a method of manufacturing a semiconductor device for forming an Si _x film.

In the above embodiment, the N-channel MOS
Although the FET has been described as an example, the present invention can be similarly applied to a P-channel MOSFET.

[0039]

The method of manufacturing a semiconductor device according to the present invention will now be described in detail with reference to examples and comparative examples. [Embodiment] An element isolation film was formed on the main surface of a p-type silicon substrate, and the film was 80 × 80 μm ² , 320 × 320 μm ² and 128
An element region having an opening area of 0 × 1280 μm ² was formed.

Next, ions are formed using the device isolation film as a mask.
Implantation was performed, and As ions were implanted into the element region. here
The acceleration energy is 40 keV and the dose is 2 × 10
^Fifteencm ^-2Set to. Subsequently, in a nitrogen atmosphere at 1000
As-implanted for 10 seconds at 10 ° C and ion-implanted
Is activated, and n is⁺A p-junction was formed.

After removing the through oxide film having a thickness of about 5 nm on the diffusion layer, a Co film having a thickness of about 10 nm and a film having a thickness of about 30 n
m of TiN film were continuously formed in the same chamber. Next, a first-stage heat treatment for forming a CoSi _X film was performed to selectively form a CoSi _X film on the element region. In the present embodiment, the heating rate is 12 ° C./min,
Furnace annealing was performed at 350 ° C. for 2 hours.

Subsequently, the Co film and the TiN film which did not react in the first heat treatment were removed by wet etching. Here, etching was performed at a liquid temperature of 70 ° C. for 20 minutes using an etching solution in which H ₂ SO ₄ and H ₂ O ₂ were mixed at a ratio of 3: 1. Thereafter, a second stage heat treatment for forming a CoSi _X film was performed to lower the resistance of the CoSi _X film. In the present embodiment, the heating rate is 80 ° C./sec,
Short-time annealing for 0 seconds was performed.

A reverse bias was applied to the n ⁺ p junction thus formed, and the junction leakage current was measured. FIG.
4 and FIG. 4 show the results of plotting the reverse leakage current when a voltage is applied to the n ⁺ p junction immediately below the CoSi _x film using the cumulative distribution function. FIG. 3 is a cumulative distribution function showing the IV characteristic after the first stage annealing, and FIG. 4 is a cumulative distribution function showing the IV characteristic after the second stage annealing. Each figure (a) shows a case where a voltage of 2V is applied, and (b) shows a case where a voltage of 5V is applied. In the figure,
A mark indicates a case where the electrode area is 80 × 80 μm ^2, a mark indicates a case where the electrode area is 320 × 320 μm ² , and a mark indicates a case where the electrode area is 1280 × 1280 μm ² .

As shown in the figure, in the sample after the first stage heat treatment, an increase in leakage current is observed in the sample of about 10 to 30% depending on the area of the electrode, but the other samples are almost uniform and good. High leakage characteristics were obtained. It is considered that the occurrence of spikes could be reduced. In the sample after the second stage heat treatment, the variation in leak current was extremely small, and almost the same leak characteristics could be obtained in 90% or more samples. [Comparative Example 1] In the above example, the same measurement was performed by changing only the heat treatment conditions for forming the CoSi _x film.

In the first stage heat treatment, the rate of temperature rise is 10
C./min., Furnace annealing was performed at 300.degree. C. for 2 hours. In the heat treatment of the second stage, the temperature was raised at a rate of 80 ° C./sec, and annealing was performed at 830 ° C. for 30 seconds. FIG. 5 shows the result of measuring the junction leak current by applying a reverse bias to the n ⁺ p junction formed in this manner.

As shown in the figure, the dispersion of the leakage current was small and good IV characteristics could be obtained. But,
As a result of measuring the sheet resistance of the surface, the value was as high as 100 Ω / □, and it was found that the surface was not silicided. [Comparative Example 2] In the above example, the same measurement was performed by changing only the heat treatment conditions for forming the CoSi _x film.

In the first stage heat treatment, the rate of temperature rise is 10
C./min., Furnace annealing was performed at 390.degree. C. for 2 hours. In the heat treatment of the second stage, the temperature was raised at a rate of 80 ° C./sec, and annealing was performed at 830 ° C. for 30 seconds. FIG. 6 shows the result of measuring the junction leak current by applying a reverse bias to the n ⁺ p junction thus formed.

As shown in the figure, the variation in the leak current was very large, and good IV characteristics could not be obtained. [Comparative Example 3] In the above-described example, the same measurement was performed by changing only the heat treatment conditions for forming the CoSi _x film.

In the first stage heat treatment, the rate of temperature rise is 10
C./min., Furnace annealing was performed at 350.degree. C. for 2 hours. In the heat treatment of the second stage, the temperature raising rate is 20 ° C./mi.
n, furnace annealing was performed at 550 ° C. for 2 hours. FIGS. 7 and 8 show the results of measuring the junction leak current by applying a reverse bias to the n ⁺ p junction thus formed. FIG. 7 is a cumulative degree distribution function showing the IV characteristic after the first stage annealing, and FIG. 8 is a cumulative degree distribution function showing the IV characteristic after the second stage annealing.
In each figure (a), when a voltage of 2 V is applied, (b) is 5 V
Is applied.

As shown in the drawing, after the first heat treatment, good IV characteristics with small variations were obtained.
By performing the heat treatment in the second stage, the variation in leak current increased rapidly, and the IV characteristics deteriorated. [Comparative Example 4] In the above example, the same measurement was performed by changing only the heat treatment conditions for forming the CoSi _x film.

In the first stage heat treatment, the heating rate is set to 50
C./sec., And short-time annealing was performed at 550.degree. C. for 30 seconds. In the heat treatment of the second stage, the temperature was raised at a rate of 80 ° C./sec, and annealing was performed at 830 ° C. for 30 seconds.
FIGS. 9 and 10 show the results of measuring the junction leak current by applying a reverse bias to the n ⁺ p junction thus formed. FIG. 9 shows I- after the first stage annealing.
FIG. 10 is a cumulative distribution function showing the IV characteristic after the second stage annealing. In each diagram (a), when a voltage of 2 V is applied,
(B) is a case where a voltage of 5V is applied.

As shown in the figure, the variation in leakage current after the first stage heat treatment is very large. By performing the heat treatment in the second stage, the leak current was reduced and the variation was slightly reduced, but the improvement of the IV characteristics was not sufficient.

[0053]

As described above, according to the present invention, a cobalt film deposition step of depositing a cobalt film on an underlying substrate having a region where silicon is exposed, and a step of depositing the underlying substrate at a temperature higher than 300 ° C. and lower than 390 ° C. A first heat treatment step of heating at a temperature of 1 to react the silicon and the cobalt film to form a first cobalt silicide film of the first phase;
Is heated at a second temperature, and the second cobalt silicide film is transformed into a second cobalt silicide film comprising a second phase.
By manufacturing a semiconductor device by the heat treatment step, the occurrence of spikes in the silicidation reaction process can be prevented, so that the junction leakage current does not increase even when a pn junction is formed immediately below cobalt silicide. .

In the first heat treatment step, 100
If the temperature is raised to the first temperature at a rate lower than ° C./min, the silicidation reaction can be made uniform, so that a cobalt silicide film can be formed without increasing the junction leakage current. Also, at the first temperature, 1 to 3
If the heat treatment is performed for a long time, a cobalt silicide film can be formed without increasing the junction leakage current.

In the method of manufacturing a semiconductor device, if the second temperature is set to a temperature between 500 ° C. and 900 ° C., the phase transfer to the low-resistance cobalt silicide without increasing the junction leakage current. Can be. Also, the second
Forming a cobalt silicide film without increasing the junction leakage current, since spikes do not occur during the silicidation reaction if the temperature is raised to the second temperature at a rate higher than 50 ° C./sec in the heat treatment step of Can be.

[Brief description of the drawings]

FIG. 1 is a process cross-sectional view (part 1) illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention;

FIG. 2 is a process cross-sectional view (part 2) illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention;

FIG. 3 is a graph (part 1) showing IV characteristics of a semiconductor device formed by a method of manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 4 is a graph (part 2) showing IV characteristics of a semiconductor device formed by a method of manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 5 is a graph showing IV characteristics of a semiconductor device formed by a method of manufacturing a semiconductor device according to Comparative Example 1.

FIG. 6 is a graph showing IV characteristics of a semiconductor device formed by a method for manufacturing a semiconductor device according to Comparative Example 2.

FIG. 7 is a graph (part 1) showing IV characteristics of a semiconductor device formed by a method of manufacturing a semiconductor device according to Comparative Example 3.

FIG. 8 is a graph (part 2) showing IV characteristics of a semiconductor device formed by the semiconductor device manufacturing method according to Comparative Example 3.

FIG. 9 is a graph (part 1) showing IV characteristics of a semiconductor device formed by a method of manufacturing a semiconductor device according to Comparative Example 4.

FIG. 10 is a graph (part 2) showing IV characteristics of a semiconductor device formed by a method of manufacturing a semiconductor device according to Comparative Example 4.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Silicon substrate 12 ... Pad oxide film 14 ... Silicon nitride film 16 ... Element isolation film 18 ... Gate insulating film 20 ... Gate electrode 22 ... High resistance area 24 ... Side wall 26 ... Low resistance area 28 ... Source / drain diffusion layer 30 ... Co film 32 ... TiN film 34 ... CoSi _X film

Claims (5)

[Claims] A step of depositing a cobalt film on a base substrate having a region where silicon is exposed; and a step of heating the base substrate at a first temperature higher than 300 ° C. and lower than 390 ° C. A first heat treatment step of forming a first cobalt silicide film made of a first phase by reacting the first cobalt silicide film with a second phase by heating the first cobalt silicide film at a second temperature. A second heat treatment step of transferring to a second cobalt silicide film made of a phase. 2. The semiconductor device manufacturing method according to claim 1, wherein in the first heat treatment step, the temperature is raised to the first temperature at a rate lower than 100 ° C./min. Device manufacturing method. 3. The method for manufacturing a semiconductor device according to claim 1, wherein in the first heat treatment step, the first temperature is set to 1 at the first temperature.
A method for manufacturing a semiconductor device, comprising performing heat treatment for up to 3 hours. 4. The method of manufacturing a semiconductor device according to claim 1, wherein said second temperature is a temperature between 500 and 900 ° C. . 5. The method for manufacturing a semiconductor device according to claim 1, wherein in the second heat treatment step, the temperature is raised to the second temperature at a speed higher than 50 ° C./sec. A method for manufacturing a semiconductor device, comprising: