JPH1083627A - Digital data processor and method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify a circuit configuration without necessitating decoding and averaging functions of an N-channel amt. of sample number information and to output a 1/4-thinning data while keeping the sequence of a 48kHz-lock mode. SOLUTION: Four channels of digital audio data having a period of five frames in AF(audio frame) size are simultaneously read out by a data read-out part 20. The AF size of the 1st channel out of the four channels read out by the data read-out part 20 is decoded by an AF size decoder 30. A sampling clock is generated by a sampling clock generating circuit 40 based on the AF size of the 1st channel detected by the AF size decoder 30. The 1/4-thinning data at the quadruple-speed reproduction is detected by a data output part 50 using the sampling clock from the sampling clock generating circuit 40.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital data processing apparatus and method for performing N-times speed reproduction processing on digital data based on an information signal.

[0002]

2. Description of the Related Art A television signal is converted into digital data, a track is formed and recorded on a magnetic tape at an angle in the longitudinal direction, and a digital signal is read from the oblique track. Video tape recorders (digital VTRs) have been put to practical use. Regarding this digital VTR, for example, "Nikkei Electronics" issued by Nikkei BP
(10-11 1993 (NO. 592), paragraphs 115 to 122).

In such a digital VTR, for example, each frame of a television signal is a recording unit. FIG. 6 shows the relationship between one frame of a television signal and a recording track on a magnetic tape on which the television signal is recorded. Digital data obtained by subjecting one frame of a television signal to analog / digital conversion (A / D conversion) is distributed to and recorded on ten adjacent inclined tracks TK sequentially arranged on a magnetic tape TP. Is done. Such recording is performed by scanning the magnetic tape TP supplied with digital data on the magnetic tape TP running in the direction of arrow DY in the direction of arrow DH.

[0004] Each of a large number of inclined tracks TK arranged and formed on the magnetic tape TP represents a data structure in the inclined recording track TK from the starting end to the ending side. An area IT in which data serving as a reference is recorded, an area AD in which audio information data representing the content of an audio signal in a television signal is recorded, and video information data representing the content of a video signal in a television signal are recorded. An area VD and an area SC in which time code data representing time information are recorded.

[0005] Among such digital VTRs, there is a type in which data is read out in parallel by four systems (channels) and then processed in order to read data without loss and transfer the data at, for example, four times the speed. .

[0006]

In the above-mentioned digital VTR, the audio signal is sampled at a sampling frequency F _S (=
(48 KHz), so that audio data is 59.94 with 525 scanning lines per frame, for example.
If the field (hereinafter, 525 lines / 59.94 shield) is equally divided for each frame, the number of audio data samples allocated per video frame is 1
601.6 samples / frame.

Considering the audio data of 5 frames of 1601.6 samples / frame, that is, 8008 samples of audio data, which is an integer, for example, once every 1600 samples / frame in a 5-frame cycle,
1600 → 1602 which becomes sample / frame
→ 1602 → 1602 → 1602 → 1600 → 1602
.. Using a 5-frame sequence of 1601.5 samples / frame or 1 averaging four channels
The sampling clock was generated based on 602 samples / frame.

However, as described above, 1600 → 16
02 → 1602 → 1602 → 1602 → 1600 → 16
When generating a sampling clock by averaging four channels of a five-frame sequence of 02..., The number of samples information such as 1600 and 1602 is decoded for four channels, and the average value is obtained. Since it has been used, four decoders and one arithmetic circuit for averaging are required, the circuit scale becomes large, and the sequence in the 48 kHz lock mode cannot be observed.

Therefore, the present invention has been made in view of the above-mentioned circumstances, and it is possible to simplify the circuit by eliminating the decoding and averaging of N channels of sample number information, and to maintain the sequence of the 48 kHz lock mode. 1
It is an object of the present invention to provide a digital data processing apparatus and method capable of outputting / 4 thinned data.

[0010]

In order to solve the above problems, a digital data processing apparatus according to the present invention uses a clock based on information on the number of samples of one system of digital data detected by a detecting means. Since the output means outputs 1 / N thinned data at the time of N-times speed reproduction, decoding and averaging of N channels of sample number information can be eliminated.

Further, in order to solve the above-mentioned problems, the digital data processing method according to the present invention uses a clock generated based on the number-of-samples information for one system and uses 1 / N thinned-out data during N-times speed reproduction. Is output, the decoding and averaging of N channels of the sample number information are not required.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a digital data processing apparatus and method according to the present invention will be described below with reference to the drawings.

This embodiment is a digital video tape which reads digital composite data from a tape-shaped recording medium on which digital composite data representing a television signal is recorded, and reproduces a television signal based on the read digital composite data. The recorder is a recorder (digital VTR) that, for example, at the time of quadruple speed reproduction, decimates the audio signal by １ ／ and reproduces four frames of sound as one frame of sound.

As shown in FIG. 1, in this digital VTR, the number of in-frame audio samples, which is the number of samples in each frame, that is, the audio frame size (AUDIO FRAME SIZE, hereinafter referred to as AFSIZE) is 5.
Digital audio data with a period of 4 frames
Data readout unit 2 for simultaneously reading the system (channel)
0, an AFSIZE decoder 30 for decoding the AFSIZE of the first channel among the four channels read by the data reading unit 20, and an AFSIZE decoder 3
0 generates a sampling clock based on the detected AFSIZE of the first channel, and uses the sampling clock from the sampling clock generation circuit 40 to generate 1/100 of the 4 × speed reproduction.
And a data output unit 50 for outputting four thinned data.

The data reading section 20 has four reading rotary magnetic heads 11 _a , 11 _b , 11 for the first, second, third and fourth channels.
_c and _11d , and read out by the reproduction amplifiers _12a , _12b , 1
Is amplified by 2 _b and 12 _d, the equalizer unit 13 _a, 13 _b,
Digital data DF ₁ , DF ₂ , DF ₃ and DF ₄ that have been amplified by 13 _c and 13 _d and rearranged by the data rearrangement unit 14 are supplied.

The rotary magnetic head for four read 11 _a to 11 _d
As shown in FIG. 2, four successively adjacent ones of a large number of inclined recording tracks TK formed on a magnetic tape TP are scanned substantially simultaneously, and the four inclined recording tracks TK are respectively scanned. The digital composite data recorded on the track TK is read substantially simultaneously. Thus, the digital composite data DT _a , read from the read rotary magnetic heads 11 _{a to} 11 _d on the four inclined recording tracks TK,
DT _b, DT _c and DT _d is obtained.

[0017] These digital composite data DT _a to D
Each of _Td includes video information data, audio information data, and other data. The audio information data includes audio data, synchronization data, and an ID code which are configured by an array of data segments subjected to an interleaving process. , And auxiliary information data for audio data such as audio auxiliary data.

The reading rotary magnetic head 11 _a to 11 digital composite data obtained respectively from _d DT _{a ~DT d,} respectively, are amplified by the reproduction amplifier section 12 _a, 12 _b, 12 _c and 12 _d, the equalizer unit 13 _a, through 13 _b, 13 _c and 13 _d, are supplied to the data parallel section 14. In data parallel section 14, the digital composite data DT _a to DT
_d are consecutively recorded on 10 successively inclined recording tracks TK on the magnetic tape TP, each being recorded on the successively 40 successively inclined recording tracks TK. Digital data DF ₁ , DF ₂ , D
Reordered to form a F ₃ and DF _4.

The digital data DF _{1 to} DF ₄ output from the data rearranging section 14 are supplied to a data reading section 20.

The data reading section 20 comprises coding sections 21 _a , 21 _b , 21 _c and 21 for the first, second, third and fourth channels.
_d and error correction / time axis correction units 22 _a , 22 _b , 22 _c and 22 _d .

The digital data DF ₁ , DF ₂ , DF
₃ and DF ₄ are the coding units 21 _a , 21 _b , 21
_c and 21 _d , each of which is coded as required to form one channel of independent data, and is coded digital data DC ₁ , DC ₂ , D
Is a C ₃ and DC _4, they are respectively supplied to an error correction and time axis correction unit 22 _a, 22 _b, 22 _c and 22 _d.

Error correction / time axis correction units 22 _a , 22 _b ,
22 In _c and 22 _d, code Secluded digital data D
For each of the video information data and audio information data included in each of C ₁ , DC ₂ , DC ₃ and DC ₄ ,
The error correction process and the time axis correction for the code error detected by the inner parity and the outer parity included in the video information data are performed, and the video information data and the audio information data are separated. Then, from the error correction and time axis correction unit 22 _a, together with the video information data error correction processing and time axis correction is performed is derived, the audio information data DA ₁ which error correction processing has been performed is derived, an error from correction, time axis correction unit 22 _b, together with the video information data error correction processing and time axis correction is performed is derived, the audio information data DA ₂ which error correction processing has been performed is derived, error correction and time The video information data on which the error correction processing and the time axis correction have been performed are derived from the axis correction unit _22c , and the audio information data D on which the error correction processing has been performed.
A ₃ is derived, and the error correction / time axis correction unit 2
From 2 _d, together with the video information data error correction processing and time axis correction is performed is derived, the audio information data DA ₄ which error correction processing has been performed is derived.

The video information data obtained respectively from the error correction and time axis correction unit 22 _a through 22 _d are supplied to the video information data processing unit illustrated is omitted in FIG.

On the other hand, error correction / time axis correction units 22 _a to 22 _a
22 _d audio information obtained respectively data from DA ₁ to D
A ₄ is supplied to the data output unit 50.

The audio information data DA ₁ output from the error correction / time axis correction section 22 _a is supplied to the AFSIZE decoder 30.

[0026] AFSIZE decoder 30 decodes the 5-frame sequence AFSIZE of 48KHz lock mode from the audio information data DA ₁ of the first channel.
That is, for example, by reading the AFSIZE that AFSIZE decoder 30 is represented by 6 bits from 5 byte audio auxiliary data as shown in FIG. 3 included in the audio information data DA ₁ that the output of the error correction and time axis correction portion 22 _a The use of the 5-frame sequence in the 48 kHz lock mode is determined, and the lock mode is configured.

The audio auxiliary data shown in FIG.
5 packs PC ₀ , PC ₁ , PC ₂ , PC _{3 of} 1 byte each
And PC ₄ . Pack PC ₀ is a header. The pack PC ₁ has a 1-bit locked mode flag LF (LOCKED MODE FLAG) and a 6-bit AFSIZE
Is written. Pack PC ₂ has 3 bit audio channel mode CH (AUDIO CHANNEL MODE)
In addition, a 1-bit pair bit PA (PAIR BIT) and a 4-bit audio mode (AUDIO MODE) are written. Since the data written in the packs PC ₃ and PC ₄ have little relation to the present invention, the description is omitted.

As the 5-frame sequence, for example, 5
One frame rate is 1600 samples / frame once, and the others are 1602 samples / frame.
600 → 1602 → 1602 → 1602 → 1602 → 1
Use 600 → 1602 ...

FIG. 4 shows a sequence of AFSIZE when 48 KHz lock mode data is reproduced at 4 × speed. S _{0 for} the first 1600 samples / frame in the sequence, S _{1 for} the next 1602 samples / frame, S _{2 for} the next 1602 samples / frame, S ₃ for the next 1602 samples / frame, and 1602 samples / frame for the last the frame and S _4. The continuity of sound between frames is as follows: first channel → second channel → third channel → fourth channel → first channel → second channel → third channel → fourth channel → first channel... There with AFSIZE only the first channel as _{SQ 1, SQ 2, SQ 3} ···, SQ 1, S
Q _2, SQ ₃ ··· is _{(S 0, S 4, S} 3, S 2, S 1) maintain the sequence of the next lock mode.

In the digital VTR according to the embodiment shown in FIG. 1, the AFSIZE for only the first channel is used, but the AFSIZE for one of the second, third and fourth channels is used. do it.

The sampling clock generation circuit 4
At 0, a sampling clock is generated using the clock signal from the PLL 41 and the AFSIZE sequence as shown in FIG.

This sampling clock is supplied to a read address data controller 55 constituting the data output unit 50. The read address data controller 55 generates a read address in synchronization with the sampling clock. And finally, the data output unit 5
0 outputs, for example, 1/4 thinned-out data at the time of quadruple speed reproduction.

The data output section 50 includes a 1/3 decimation processing circuit 51 for performing deinterleaving processing on the audio information data DA _{1 to} DA ₄ which have been interleaved and then performing 1/3 decimation processing. A write address and a write address data controller 52 for outputting write data for temporarily writing the thinned output from the / 3 thinning processing circuit 51 to a memory 54 described later.
And the write address and write data from the write address data controller 52,
Memory 54 by address / data controller 55
To control writing and reading of data to / from
With the read address / data controller 53, the write data is written based on the write address,
A memory 54 from which read data is read based on a read address, and a read address controller 5 for receiving read data from the memory 54 based on the read address
5 and an operation for reducing the amount of data read via the read address data controller 55 to 3/4
4 thinning operation circuit 56.

The 1/3 thinning-out process circuit 51, for example, the first inclined recording track in the audio information data DA _1, i.e., the inclined recording track TK on the magnetic tape TP
Audio information data D recorded in the area AD at
As shown in FIG. 5, the synchronization block number i of the nine data synchronization blocks (data synchronization blocks 2 to 10) constituting A _{1 and} having synchronization block numbers i of 2 to 10 is 2
４4 are detected (data synchronization blocks 2 to 4).

Similarly, the 1/3 thinning-out processing circuit 51 outputs _three of the nine data synchronization blocks 2 to 10 constituting one tilt recording track in the audio information data DA ₂ , DA ₃ and DA ₄ . Data synchronization blocks 2 to 4 are detected, respectively.

FIG. 5 shows one inclined recording track TK.
2 shows a coding format of audio information data recorded in the area AD in FIG. The data synchronization block section is a main part, and a preamble section and a postamble section are arranged before and after the data synchronization block section. In this coding format,
The data synchronization block includes 14 data synchronization blocks whose synchronization block numbers i are 2 to 15, and each data synchronization block is formed of 90 bytes whose byte position numbers j are 0 to 89.

In each of the nine data synchronization blocks whose synchronization block numbers i are 2 to 10, the first 2 bytes (byte position numbers j are 0 and 1) are used as synchronization data, and the next 3 bytes ( Byte position number j is 2
4) is an ID code, the next 5 bytes (byte position number j is 5 to 9) are audio auxiliary data, and the subsequent 72 bytes (byte position number j is 10 to 81) are audio data. The audio data is constructed by adding an inner parity of 8 bytes (byte position number j is 82 to 89). The ID code represents information about a recording mode, a synchronous block number i, and the like regarding the tilted recording track, and the audio auxiliary data represents information about recording conditions of audio data including the number of constituent bits and the like.

In each of the five data synchronization blocks whose synchronization block numbers i are 11 to 15, the first two bytes (byte position numbers j are 0 and 1) are used as synchronization data, and the next 3 bytes are used. Byte (byte position number j is 2
To 4) are used as an ID code, and 77 bytes (byte position number j is 5 to 81) following it are used as outer parity, and an inter parity of 8 bytes (byte position number j is 82 to 89) is added to the outer parity. It is configured. Therefore, the audio data exists within the range hatched in FIG. 5 in which the synchronization block number is 2 to 10 and the byte position number j is 10 to 81.

Here, Table 1 shows the ten tracks TK ₀ , TK ₁ , TK ₂ , T ₁ constituting one frame in order to explain the 1/3 thinning processing in the 1/3 thinning processing circuit 51.
The audio data D _{0 to} D ₁₆₁₉ on K ₃ , TK ₄ , TK ₅ , TK ₆ , TK ₇ , TK ₈ and TK ₉ are shown.

[0040]

[Table 1]

The 1/3 thinning-out process circuit 51, nine data synchronization, for example synchronization block number i constituting the audio information data recorded in the audio area AD of the inclined track TK ₀ or TK ₅ is 2 to 10 The audio data in three data synchronization blocks (data synchronization blocks 2 to 4) whose synchronization block numbers i are 2 to 4 are thinned out from the audio data in the blocks (data synchronization blocks 2 to 10) and output. That is, the output is performed after performing the 1/3 thinning process.

In the 1/3 thinning-out processing circuit 51, three data synchronizations in which the synchronization block numbers i obtained from the audio information data DA ₁ , DA ₂ , DA ₃ and DA ₄ are 2-4. Block (data synchronization block 2
Deinterleave processing is also applied to each of the audio data of 4).

Further, the 1/3 thinning-out processing circuit 51 converts the audio data in the three data synchronization blocks having the deinterleaved synchronization block numbers i of 2 to 4 into addresses and data. I do. These addresses and data are supplied to the write address data controller 52.

Write address data controller 5
2 converts the address and data from the 1/3 thinning processing circuit 51 into a write address and write data for the memory 54.

The write address and the write data are supplied to the memory 54 via the write / read address / data controller 53, and the write data is written to a location based on the write address.

Read / address data controller 55
Is the sampling clock generation circuit 40 as described above.
A read address is generated in synchronization with the sampling clock supplied from the memory, and is supplied to the memory via the write / read address data controller 53. In accordance with the read address, read data is sequentially read from the memory 54 and supplied to the 3/4 thinning-out operation circuit 56.

The 3/4 decimation operation circuit 56 performs a decimation operation to reduce the data amount to 3/4 on the read data sequentially supplied from the read / address data controller 55. Therefore, as the data output unit 50, the audio information data D supplied from the data read unit 20 is output.
A ₁ , DA ₂ , DA ₃ and DA ₄ are subjected to 1/4 thinning processing, and finally 1/4 thinned data reproduced at quadruple speed is output as continuous one frame of audio data.

For this reason, the audio signal is decimated by １ ／ at the time of, for example, quadruple speed reproduction by this digital VTR, and
When reproducing the sound frames as the sound of one frame, the average need only decode the audio auxiliary data from the audio information DA ₁ only one channel among with four channels, as in the conventional four channels Since an arithmetic circuit and a decoder for three channels are not required, the circuit can be simplified and the sequence of the 48 kHz lock mode can be maintained.

The digital VTR according to the above embodiment is
In the above, the number N of channels simultaneously read by the data reading unit 20 is set to 4. However, if the number is an integer excluding a multiple of 5, 4 is set.
However, the present invention is not limited to this.

The number of channels N and the number of rotary magnetic heads for reading need not be the same.

[0051]

According to the digital signal processing apparatus of the present invention, the data output means uses a clock based on the sample number information of one system of digital data detected by the detection means, and the data output means performs 1 / N thinning at the time of N-times speed reproduction. Since the data is output, the circuit can be simplified without decoding and averaging for N channels of the sample number information, and, for example, 1/4 thinned-out data can be output while maintaining the 48 kHz lock mode sequence.

In the digital signal processing method according to the present invention, 1 / N thinned data at the time of N-times speed reproduction is output using a clock generated based on the sample number information for one system. The decoding and averaging for N channels are unnecessary, the circuit scale is simplified, and the sequence of the 48 kHz lock mode is maintained.
For example, 1/4 thinned data can be output.

[Brief description of the drawings]

FIG. 1 is a block diagram of a digital VTR as an embodiment of a digital data processing device and method according to the present invention.

FIG. 2 is a block diagram of a digital VTR shown in FIG.
FIG. 7 is a diagram illustrating a state in which four reading rotary magnetic heads simultaneously scan four inclined recording tracks of a plurality of inclined tracks on a magnetic tape to simultaneously read digital composite data.

FIG. 3 is an AFSI used by the digital VTR shown in FIG.
It is a format diagram of audio auxiliary data in which ZE is written.

FIG. 4 is a diagram showing an AFSIZE sequence when data in a 48 kHz lock mode is reproduced at 4 × speed.

FIG. 5 shows an area AD in one inclined recording track TK.
FIG. 3 is a diagram illustrating a coding format of audio information data recorded in a.

FIG. 6 is a recording format diagram of a magnetic tape used with a digital VTR.

[Explanation of symbols]

Reference Signs List 20 data readout unit, 30 audio frame size (AFSIZE) decoder, 40 sampling clock generation circuit, 50 data output circuit, 51 1/3 thinning processing circuit, 54 memory, 55 read / address data controller, 56 3/4 thinning operation circuit

Claims (8)

[Claims] 1. A reading means for simultaneously reading N systems of digital data in which the number of samples of each frame is M frames and a period, and the sample number information of digital data of one of the N systems read out by the reading means. Detecting means for detecting; clock generating means for generating a clock based on the one-system sample number information detected by the detecting means; 1 / N at the time of N-times speed reproduction using a clock from the clock generating means; A digital data processing device comprising: data output means for outputting thinned data. 2. The digital data processing apparatus according to claim 1, wherein said digital data is audio data, and said sample number information is information on the number of audio samples in a frame. 3. The digital data processing device according to claim 1, wherein said M is 5 and said N is an integer excluding a multiple of 5. 4. The digital data processing device according to claim 1, wherein said M is 5 and said N is 4. 5. A system for simultaneously reading N channels of digital data in which the number-of-samples information of each frame is M frames and having a cycle, and using a clock generated based on the number-of-samples information of one of the channels, performs N-times playback. A digital data processing method, wherein 1 / N thinned data is output. 6. The digital data processing method according to claim 5, wherein said digital data is audio data, and said sample number information is information on the number of audio samples in a frame. 7. The digital data processing method according to claim 5, wherein said M is 5 and said N is an integer excluding a multiple of 5. 8. The digital data processing method according to claim 5, wherein said M is 5 and said N is 4.