JPH1079736A - Atm communication system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the opportunity of abort of valid cell data due to buffer overflow in the cell buffer of an asynchronous transfer mode (ATM) receiver. SOLUTION: An unassigned cell is inserted to an ATM cell in a rate adjustment circuit 104 to adjust a transmission rate and an idle cell insert circuit 106 inserts an idle cell to the ATM cell after the rate adjustment by the rate adjustment circuit 104 to interpolate transmission frame data and the inserted unassigned cell is given to an idle cell processing circuit 201, in which the cell is converted into an idle cell and transmitted. Thus, it is prevented that an invalid unassigned cell is written to a receiver side ATM cell buffer 113 with valid cells simultaneously and the opportunity of occurrence of the overflowed buffer 113 is reduced and then the opportunity of occurrence of abort of valid cells is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to an ATM (Async).
More particularly, the present invention relates to an ATM communication system in which idle cells, which are invalid cells for interpolating transmission frame data, are inserted on a transmission side and deleted on a reception side.

[0002]

2. Description of the Related Art Conventionally, this type of ATM communication system has
TM-FORUM UNI3.1 and ANSI T1E
It is described in standards such as 1002R2. Physical (PHY) related to ATM communication equipment described in this standard
FIG. 5 shows the data transfer portion between the layers and the ATM layer. First, the operation of the transmission unit 10 will be described with reference to FIG. The packet data transmitted from the upper layer is divided by the ATM cell construction circuit 103 into ATM cells having valid data. Further, in the speed adjusting circuit 104 in the ATM layer 101, an unassigned cell, which is an undefined cell, is inserted in order to adjust the transmission speed of the effective cell. This data is input via an ATM cell buffer 105 in the PHY layer 102 to an idle cell insertion circuit 106 for inserting an idle cell which is an invalid cell for interpolating transmission frame data. Thereafter, this data is assembled into continuous transmission frame data in the remaining blocks (not shown) in the PHY layer 102 and transmitted.

Next, the operation of the receiving section 11 will be described. The transmission frame data output from the transmission unit 10 is converted into an ATM cell stream including idle cells, unassigned cells, and valid cells in a preceding block (not shown) in the PHY layer 110. Further, in the idle cell deletion circuit 112 in the PHY layer 110, the idle cell is deleted,
The data is input to the unassigned cell deletion circuit 114 in the ATM layer 111 via the ATM cell buffer 113. Here, the data in which the unassigned cells have been deleted and only the valid cells are present is reproduced as packet data in the packet data reproducing circuit 115 and transmitted to the upper layer.

[0004]

In the above-described conventional system, the unassigned cell inserted for speed adjustment in the transmission unit 10 is stored in the ATM cell buffer 113 in the same manner as the valid cell. Therefore, the PHY layer 1
ATM input to the ATM cell buffer 113 in the ATM 10
When the amount of ATM cells that can be processed in the ATM layer 111 becomes smaller than the cell amount, the ATM cells are buffered in the ATM cell buffer 113 and eventually exceed the allowable amount. Then, there is a disadvantage that the overflowed ATM cells are discarded regardless of whether they are valid or not.

In Japanese Patent Application Laid-Open No. 4-372244,
Although the effective cells having the lower priority are discarded to prevent the effective cells having the higher priority from being discarded, even in this case, the above-mentioned disadvantages of the prior art cannot be solved.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks of the prior art, and has as its object to reduce the possibility that valid cell data is discarded due to buffer overflow in a cell buffer of an ATM receiver. Is to provide a system.

[0007]

An ATM communication system according to the present invention comprises an ATM (Asynchronous Tr).
transfer rate adjustment means for inserting an unassigned cell into the transfer mode cell, and inserting an idle cell for interpolating transmission frame data into the ATM cell after the rate adjustment by the rate adjustment means. An ATM transmitting apparatus including: an ATM transmitting device; a deleting unit configured to delete an idle cell among the received ATM cells;
Buffer means for holding the ATM cells from which the idle cells have been deleted up to a certain amount and discarding the amount exceeding the certain amount;
And an ATM receiving device including: an ATM transmitting device, wherein the ATM transmitting device includes a cell converting means for converting an unassigned cell inserted by the speed adjusting means into an idle cell.

[0008] In the ATM communication system of the present invention, an unassigned cell inserted for speed adjustment is converted into an idle cell on the transmitting apparatus side and then transmitted. For this reason, since the receiving side holds the idle cells after deleting them in the buffer, only valid cells are held in the buffer. Therefore, it is possible to reduce the chance that valid cell data is discarded due to buffer overflow.

[0009]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an ATM communication system according to the present invention, and the same parts as those in FIG. 5 are denoted by the same reference numerals. The ATM communication system of FIG. 1 differs from the system of FIG. 5 in that an idle cell conversion circuit 201 for converting an unassigned cell into an idle cell is inserted between the ATM cell buffer 105 and the idle cell insertion circuit 106. Is a point. Other parts perform the same operation as in FIG.

In this configuration, as in the conventional example of FIG. 5, the ATM cell buffer 105 in the PHY layer 102 stores and outputs valid cells and unassigned cells for speed adjustment. This data is input to the unassigned cell unassigned cell circuit 201. The unassigned cell conversion circuit 2 converts the unassigned cells into idle cells. Then, the idle cell insertion circuit 106 assembles the transmission frame data after the idle cells are further inserted in order to interpolate the transmission frame data.

The transmission frame obtained in this manner has no unassigned cells, and is composed of valid cells and idle cells. When the transmission frame data is input to the receiving unit 11, the idle cell deleting circuit 11
2 deletes idle cells. For this reason, AT
In the M cell buffer 113, only valid cells are stored,
Will be output.

Therefore, as compared with the conventional example shown in FIG.
ATM stored in the ATM cell buffer 113 in the PHY layer 110 of the receiving unit 11 by the capacity of the unassigned cell
The number of cells can be reduced. For this reason, it is possible to reduce the chance that valid cells are discarded due to buffer overflow.

FIG. 2 is a block diagram showing another embodiment of the present invention. The difference from the case of FIG. 1 is that the idle cell conversion circuit 201 of the unassigned cell is arranged at the subsequent stage of the idle cell insertion circuit 106.

In this configuration, as in the case of the embodiment of FIG. 1, the frame data output from the transmission unit 10 can be composed of valid cells and idle cells. Exactly the same effect can be obtained.

FIG. 3 is a block diagram showing still another embodiment of the present invention. It differs from the case of FIG. 1 in that the unassigned cell idle cell conversion circuit 201 is arranged at the preceding stage of the ATM cell buffer 105. It is obvious that the present embodiment can obtain exactly the same effects as the embodiment of FIGS.

FIG. 4 is a block diagram showing a detailed internal configuration of the unassigned cell idle cell conversion circuit 201 in the embodiment of FIG. The cell data output from the ATM cell buffer 105 is checked by the unassigned cell header collation circuit 2011 as to whether or not the cell data is an unassigned cell. As a result, when it is recognized that the cell is an unassigned cell, the idle cell output from the idle cell generator 2012 is selected by the selector 2013, and the idle cell insertion circuit 1
06.

When it is recognized that the cell is not an unassigned cell, valid data output from the ATM cell buffer 105 is selected by the selector 2013 and input to the idle cell insertion circuit 106.

In short, in the idle cell circuit 201,
It is determined whether or not an ATM cell is an unassigned cell. When the result of the determination indicates that the ATM cell is an unassigned cell, an idle cell is transmitted instead of the ATM cell.

Here, in the unassigned cell header collation circuit 2011, the above determination is made by comparing the header of the ATM cell with the header of the unassigned cell. That is, generally, the header part of an unassigned cell has a CLP (Cell) used for priority indication for cell discard.
All bits including “Loss Priority” are “0”, and HEC used for header error detection is used.
The value of (Header Error Control) is 55 [H]. Therefore, when all bits except the HEC in the header portion are “0”, it can be determined that the cell is an unassigned cell. The unassigned cell header matching circuit 2011 makes this determination.

In the case of an idle cell, the header portion has a CLP value of "1" and all other bits are "0". Then, the value of HEC is 52 [H]. Also, the payload portion of the idle cell is all 6 A
[H]. Therefore, the unassigned cell header collation circuit 2011 can determine the unassigned cell and the idle cell without error.

The above is the description of the idle cell circuit 201 in FIG.
However, it is apparent that the idle cell circuit 201 in FIGS. 2 and 3 can be similarly configured.

As described above, since the invalid unassigned cell is not written to the ATM cell buffer on the receiving side at the same time as the valid cell, the chance of the ATM cell buffer overflowing can be reduced. The chance of discarding valid cells can be reduced.

The present invention can take the following aspects in connection with the description of the claims.

(4) The judging means judges that the ATM cell is an unassigned cell when all parts other than the error control section in the header of the ATM cell are "0". The ATM communication system according to claim 2.

(5) The ATM communication according to any one of claims 1 to 4, wherein the cell conversion means converts an unassigned cell into an idle cell after the idle cell insertion processing by the idle cell insertion means. system.

[0027]

As described above, the present invention converts an unassigned cell into an idle cell so that an invalid unassigned cell is simultaneously received with a valid AT cell.
There is an effect that writing to the M cell buffer is not performed, the chance of buffer overflow occurring is reduced, and the drop of valid cell data due to buffer overflow can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an ATM communication system according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an ATM communication system according to another embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of an ATM communication system according to still another embodiment of the present invention.

FIG. 4 is a block diagram illustrating a configuration example of an idle cell conversion circuit in FIG. 1;

FIG. 5 is a block diagram showing a configuration of a conventional ATM communication system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Transmission part 11 Reception part 103 ATM cell construction circuit 104 Speed adjustment circuit 105 ATM cell buffer 106 Idle cell insertion circuit 112 Idle cell deletion circuit 113 ATM cell buffer 114 Unassigned cell deletion circuit 115 Packet data reproduction circuit 201 Idle cell generation circuit

Claims (3)

[Claims] 1. An ATM (Asynchronous T)
transfer mode), a rate adjusting means for adjusting the transmission rate by inserting an unassigned cell into the cell, and an idle cell insertion for inserting an idle cell for interpolating the transmission frame data into the ATM cell after the rate adjustment by the rate adjusting means. Means, an ATM transmitting apparatus including: an ATM transmitting apparatus comprising: an ATM cell transmitting apparatus; an erasing means for erasing an idle cell among received ATM cells; An ATM communication system comprising: a buffer means; and an ATM receiving apparatus, comprising: an ATM receiving apparatus including: a cell converting means for converting an unassigned cell inserted by the speed adjusting means into an idle cell. An ATM communication system, characterized by: 2. The cell conversion means according to claim 1, wherein said determination means determines whether said ATM cell is an unassigned cell, and said determination means indicates that said ATM cell is an unassigned cell. 2. An ATM communication system according to claim 1, further comprising means for transmitting an idle cell instead of said ATM cell. 3. The ATM communication system according to claim 2, wherein said determination means makes said determination by comparing a header of said ATM cell with a header of an unassigned cell.