JPH1074916A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device wherein, without preventing realing higher density for a memory cell, stable read-out operation is performed to a memory cell array of large variation in threshold after erasing. SOLUTION: In a reading-out operation, when a word line WL (0) is selected with positive selection electric potential (VCC), a source line SL (0) connected to a selected memory cell is taken as a ground electric potential, only a word line WL (1) connected to a selected memory cell and a memory cell sharing a source is taken a negative non-selected electric potential (-VG1), with other word line taken as a ground electric potential, and a source line of a memory cell connected to the other word line is taken as being open. Thereby, supply of negative voltage is only to the word line WL (1), so that as a negative voltage generating circuit it can be of a small scale, thus even when a memory cell having a threshold value of 0V or less at a non-selected memory cell is present, no leak current flows in a bit line, enabling normal reading-out operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash EEPROM (Electr
ically Erasable and Progr
The present invention relates to a semiconductor memory device such as an amenable read only memory (AMD).

[0002]

2. Description of the Related Art A nonvolatile storage device is a storage device capable of retaining stored information even during a power-off period. Among them, a flash EEPROM is capable of electrically writing and has a plurality of cells. By electrically erasing all at once, it is possible to increase the density of memory cells, and it is widely used as a nonvolatile semiconductor memory device.

FIG. 8 is a configuration diagram of a flash EEPROM which is a conventional semiconductor memory device. M _{0,0 to} M _{n, m} is 2
A memory cell having a double gate structure and a word line WL
(0) to WL (n) and bit lines BL (0) to BL
(M) at each intersection. Each memory cell is arranged so that the drain and the source are opposed to the memory cell facing each other in the same bit string, and the drain and the source of the opposed memory cell are configured to share a diffusion layer. The control gates of the memory cells in the same row are connected in common, and the corresponding word line WL
(0) to WL (n). The drains of the memory cells in the same column are commonly connected and connected to corresponding bit lines BL (0) to BL (m). The sources of the memory cells in the same row are connected in common, and the source lines SL (0) to
It is connected to the erase circuit 7 via SL (k).

The row decoder 2 has a row address Ra.
(0: i) and the word lines WL (0) to WL (
Select one of (n). Column decoder 4
Receives the column address Ca (0: j) and supplies a selection signal to the column switch 5. The column switch 5
Upon receiving a selection signal from the column decoder 4, the bit line BL
(0) to BL (m) are selectively connected to the data bus DB. The data bus DB is connected to a read / write circuit 8, and inputs / outputs data to / from a data input / output pin Dio via the read / write circuit 8.

In this flash EEPROM, at the time of erasing, a high voltage is applied between the control gate and the source to extract charges accumulated in the floating gate by the Fowler-Nordheim tunnel phenomenon, and at the time of writing, the voltage is applied between the source and the drain. Hot electrons are injected into the floating gate by the high voltage
Thus, the threshold voltage of the memory cell transistor is changed to store information.

[0006] Such a flash EEPROM has been applied to various products, but in recent years, low voltage and high speed operation has been demanded for applications such as portable equipment. In order to realize a low-voltage operation, the threshold value after erasing must be controlled to be lower and stable. However, in order to set the threshold value after erasing to a low value, a threshold value of 0 V or less is set. When a memory cell in an over-erased state is generated, a leak current flows through the over-erased memory cell even when the word line is in a non-selected state, and normal reading cannot be performed. For this reason, due to circuit contrivances, even when there is a memory cell having a threshold value of 0 V or less, efforts have been made to enable normal reading and to realize low-voltage operation, and some proposals have been made. ing.

For example, Japanese Patent Application Laid-Open No. 4-356797 discloses that an appropriate voltage is applied only to a source line connected to a selected memory cell, and a source line connected to a non-selected memory cell is opened. The configuration is described. With such a configuration, an appropriate voltage (usually a ground potential) is applied to only one source line during data reading.
To open other source lines.
Even when the threshold value of the memory cell connected to the open source line is 0 V or lower, no leak current flows through the bit line, so that normal reading can be performed.

However, the memory cells share the source diffusion of the memory cells facing each other in the word direction for high-density integration and are connected to the same source line. Therefore, any one of the memory cell transistors sharing the source line is used. When the threshold value becomes 0 V or less, normal reading cannot be performed. Therefore, a configuration in which the drains of the memory cell transistors sharing a source line are connected to different bit lines is also disclosed.

Japanese Patent Application Laid-Open No. 6-29498 discloses that even if the variation in the threshold value after erasure is large,
A configuration for stably performing reading in a low-voltage power supply operation is disclosed. A positive voltage X address decoder and a negative voltage X address decoder are provided. A positive voltage X decoder applies Vcc potential to a selected word line, and a negative voltage X decoder outputs -VG1 ( −
2V). With this configuration,
Even when a non-selected memory cell has a memory cell having a threshold value of 0 V or less, a normal read operation can be performed without causing a bit line leak.

[0010]

In order to perform stable reading even when the threshold variation after erasure is large, as shown in Japanese Patent Application Laid-Open No. 4-356797, unselected source lines are left open. In such a configuration, the bit lines are separated so that the drains of the memory cells sharing the source diffusion are not connected to the same bit line, or the memory cells not sharing the source diffusion are used. And the source lines must be separated. For this reason, the layout size increases, which hinders high density.

Further, as shown in Japanese Patent Application Laid-Open No. 6-29498, in a configuration in which non-selected word lines are set to a negative potential, it is necessary to set all non-selected word lines to a negative potential. When a negative potential is generated inside the chip, a negative voltage generating circuit for driving a large word line capacitance is required, and the circuit scale becomes large. This method also hinders high density memory cells.

An object of the present invention is to provide a semiconductor memory device capable of performing a stable read operation on a memory cell array having a large variation in threshold value after erasing without hindering the increase in the density of memory cells. To provide.

[0013]

According to a first aspect of the present invention, there is provided a semiconductor memory device, wherein a bit line and a drain are connected to each intersection of a plurality of bit lines and a plurality of word lines arranged orthogonally, and the word line and the control gate are connected to each other. Place the connected memory cells,
A memory cell array in which the drains are connected to the same bit line and two adjacent memory cells are paired, and the source of each set of memory cells is shared and connected to a common source line; Means for applying a high voltage between the common source line to which the cell is connected and the word line; means for applying a selection potential to a word line (selected word line) to which a memory cell selected in a read operation is connected; Means for applying a non-selection potential having a polarity opposite to the selection potential to a word line (non-selection word line) to which a memory cell sharing a source with a memory cell selected in a read operation is connected; Means for applying a ground potential to (non-selected word lines), and applying a ground potential to a common source line to which a memory cell selected in a read operation is connected. Means for obtaining, and a means to open the rest of the common source line in a read operation.

According to this structure, in the read operation, the selected word line is set to the selected potential, the common source line to which the selected memory cell is connected is set to the ground potential, and the memory cell connected to the selected word line is connected to the selected word line. Only one unselected word line to which a memory cell sharing a source is connected is set to a non-selection potential having a polarity opposite to the selection potential of the selected word line, the other non-selection word lines are set to the ground potential, and the other non-selection word lines are set to the ground potential. By opening the common source line of the memory cells connected to the selected word line, the supply of the negative voltage is only required to the selected word line or one non-selected word line. Even if memory cells having a threshold value of 0 V or less exist in unselected memory cells without reducing the density of the memory cells, the bit size can be reduced. Leakage current does not flow, it is possible to perform normal read operation.

In addition, since high-precision threshold control during the erase operation is not required, the speed of the erase operation can be increased, and the threshold value after the erase operation can be set to a low value. Thus, the ON current of the memory cell can be increased, and a high-speed read operation can be realized. According to a second aspect of the present invention, in the semiconductor memory device of the first aspect, the selection potential is a positive potential and the non-selection potential is a negative potential.

Thus, in the read operation, the negative potential needs to be supplied only to one non-selected word line connected to the memory cell sharing the source with the memory cell connected to the selected word line. A semiconductor memory device according to a third aspect is the semiconductor memory device according to the first or second aspect,
The word line connected to the memory cell selected in the erasing operation has the same potential as the non-selection potential in the reading operation.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a flash EEPROM which is a semiconductor memory device according to an embodiment of the present invention.
FIG. 3 is a configuration diagram of M. FIG. 2 is a diagram showing a circuit example of the memory cell array 1 of the flash EEPROM shown in FIG.

First, an outline of the configuration and operation of a flash EEPROM according to this embodiment will be described with reference to FIGS. Flash E shown in FIG.
The EPROM has a memory cell array 1 for storing data. As shown in FIG. 2, the memory cell array 1 includes a transistor having a double gate structure having a control gate and a floating gate as a memory cell M _0,0.
To M _{n, m,} and each memory cell M _{0,0 to} M _{n, m} is composed of word lines WL (0) to WL (n) and bit lines BL (0) to BL
It is arranged at the intersection with (m). Control gates of memory cells in the same row are connected to corresponding word lines WL (0) to WL (
(N), and the drains of the memory cells in the same column are commonly connected to the bit lines BL (0) to BL (m), respectively. Opposite sources of a pair of memory cells arranged in the same column of the memory cell array 1 are formed by common source diffusion, and the corresponding source lines (common source lines) SL (0) to SL (0) to SL (K) are commonly connected.

The word line WL (0) of the memory cell array 1
To WL (n) and source lines SL (0) to SL (k) are controlled by a row decoder 2, a source switch 3, a negative voltage decoder 6, and an erase circuit 7. Row address signal RA (0: i) is supplied to row decoder 2, and power supply voltage VC input via an external terminal is supplied to row decoder 2.
C and a power supply voltage VP formed by the voltage generation circuit 10.
1 and VP2 are supplied. Also, the row address RA (0:
i), and further supplied with a power supply voltage VCC input via an external terminal and power supply voltages -VG1, -VG2 and VP2 generated by the voltage generation circuit 10. Although not particularly limited, the power supply voltage VCC is + 3V
And the power supply voltages VP1 and VP2 are positive potentials having a relatively large absolute value, such as + 7V and + 5V, respectively. In addition, the power supply voltage −V
G1 is a negative potential having a relatively small absolute value such as -2V, and the power supply potential -VG2 is a negative potential having a relatively large absolute value such as -10V.

The row decoder 2, the source switch 3, the negative voltage decoder 6 and the erase circuit 7 are provided with a flash EEPROM.
Word lines WL (0) -WL (n) and source lines SL (0)-of memory cell array 1 according to the operation mode of OM.
The necessary potential is supplied to SL (k). Word line WL in read mode in this embodiment
The selection potentials of (0) to WL (n) are set by the row decoder 2 and set to +3 V, that is, the power supply voltage VCC, as described later. The non-selection potential is set by the row decoder 2 and the negative voltage decoder 6, and the potential of the non-selection word line connected to the opposite memory cell sharing the source with the memory cell connected to the selected word line is negative. The voltage decoder 6 supplies -2V, that is, the power supply voltage -VG1.
The potential of the other unselected word lines is set to the ground potential by the row decoder 2. The selection potential of the word lines WL (0) to WL (n) in the write mode is similarly set by the row decoder 2, and is set to + 7V, that is, the power supply voltage VP1. The non-selection potential is set by the row decoder 2 and the negative voltage decoder 6, and the potential of the non-selection word line connected to the opposite memory cell sharing the source with the memory cell connected to the selected word line is:
The negative voltage decoder 6 supplies −2V, that is, the power supply voltage −VG.
The potential of other unselected word lines is set to 1, and the row decoder 2 sets the potential to the ground potential. The potentials of the word lines WL (0) to WL (n) in the erase mode are set by the negative voltage decoder 6, and are -10V, that is, the power supply voltage -VG2.
It is said.

The source lines SL (0) to SL (k) in the read and write modes are set by the row decoder 2 and the source switch 3, and share a source with a selected memory cell. The sources of the unselected memory cells facing each other are set to the ground potential, and the sources of the other unselected memory cells are opened. Further, the source lines SL (0) to S (S) in the erase mode
L (k) is set by the erasing circuit 7, and is set to + 5V, that is, the power supply voltage VP2.

The bit line BL (0) of the memory cell array 1
To BL (m) are connected to the column switch 5, respectively.
Further, 16 designated buses are selectively connected to the data bus DB (0:15), that is, DB via the column switch 5.
(0) to DB (15). Column switch 5
Is supplied with a selection signal from the column decoder 4. The column decoder 4 has a column address signal CA
(0: j) is supplied. Column decoder 4 decodes column address signal CA (0: j) and outputs a corresponding bit line selection signal. The column switch 5 selectively connects the 16 bit lines and the data buses DB (0) to DB (15) according to a bit line selection signal from the column decoder 4.

The data buses DB (0) to DB (15)
The read / write circuit 8 is connected to the read / write circuit 8.
The write circuit 8 includes data buses DB (0) to DB (15)
And 16 write circuits and read circuits corresponding to each of them. The 16 write circuits of the read / write circuit 8 correspond to the corresponding data input / output terminals Dio (0: 1) in the write mode of the flash EEPROM.
5) That is, a predetermined write signal is formed based on the write data input via Dio (0) to Dio (15), and the memory cell array 1 is connected via the data buses DB (0) to DB (15). By applying a write potential to the selected 16 bit lines, data is written to the selected 16 memory cells. At this time, the write signal applied to the selected 16 bit lines is set to + 5V, that is, VP2, for the bit line to be written, and to the ground potential for the bit line not to be written.

On the other hand, the sixteen read circuits of the read / write circuit 8 are used to read 16 bit lines and data buses DB from the selected 16 memory cells of the memory cell array 1 in the read mode of the flash EEPROM.
(0) -Amplify the read signal output via DB (15), and input / output terminals Dio (0) -Dio (1).
Output via 5). At this time, the read circuit applies a voltage such as +1 V to the selected 16 bit lines of the memory cell array 1.

The control circuit 9 selectively forms the above-mentioned various internal control signals based on the chip enable signal NCE, the write enable signal NWE, and the output enable signal NOE, and supplies the signals to various parts of the flash EEPROM. Flash EEPROM in this embodiment
M further includes a voltage generation circuit 10 for forming the above-mentioned various power supply voltages. The voltage generation circuit 10 is configured to generate VP1, VP based on a power supply voltage VCC supplied through an external terminal.
2, -VG1 and -VG2 are formed, respectively.

Next, an outline and features of each operation mode of the flash EEPROM according to this embodiment will be described with reference to FIGS. FIG.
FIG. 4 is a diagram showing a voltage relationship in a read mode of the flash EEPROM in this embodiment, FIG. 4 is a diagram showing a voltage relationship in a write mode of the flash EEPROM, and FIG.
FIG. 5 is a diagram showing a voltage relationship in the erase mode of FIG.

In the case of FIG. 3, that is, the flash EEPR
When OM is set to the read mode, assuming that the row decoder 2 selects the word line WL (0) as a result of decoding the row address signal RA (0: i), the selected word line WL (0) is connected to the selected word line WL (0). VCC potential is output,
The unselected word line WL (1) connected to the opposite memory cell sharing the source with the memory cell connected to the selected word line WL (0) is opened, and the other unselected word line WL (1) is opened. The potential is set to the ground potential. Also,
In response to the decoding result of the row address signal RA (0: i), the source switch 3 sets the source of the selected memory cell and the opposite memory cell sharing the source with the selected memory cell to the ground potential ( Source line SL
(0) is set to 0 V), and the sources of other unselected memory cells are opened.

As a result of decoding of the row address signal RA (0: i) by the negative voltage decoder 6, the memory cell connected to the word line WL (0) selected by the row decoder 2 shares a source with the memory cell. -V is applied to the unselected word line WL (1) connected to the selected memory cell.
G1 is output. A bit line selected by the column decoder 4 and the column switch 5 is supplied with a low positive voltage of about +1 V, and the erasing circuit 7 is open to all the source lines SL (0) to SL (k). I have.

In the case of FIG.
When the word line WL (0) is selected as a decoding result of the row address signal RA (0: i) by the row decoder 2 when the OM is set to the write mode, the selected word line WL (0) is applied to the selected word line WL (0). The potential of VP1 is output, and the unselected word line WL (1) connected to the opposite memory cell sharing the source with the memory cell connected to the selected word line WL (0) is opened, and Are set to the ground potential.
Further, in response to the decoding result of the row address signal RA (0: i), the source switch 3 connects the source of the selected memory cell and the source of the opposing memory cell sharing the source with the selected memory cell to ground. The potential is set, and the sources of other unselected memory cells are opened. As a result of decoding of the row address signal RA (0: i), the negative voltage decoder 6 connects the memory cell connected to the memory cell connected to the word line WL (0) selected by the row decoder 2 to the opposite memory cell sharing the source. -VG1 is output to the selected non-selected word line WL (1). The bit line selected by the column decoder 4 and the column switch 5 has +
A positive voltage (VP2) of about 5 V is applied, and a bit for which writing is not performed is applied with a ground potential. At this time,
The erasing circuit 7 includes all the source lines SL (0) to SL (k)
Open to

In the case of FIG. 5, that is, the flash EEPR
When the OM is set to the erase mode, the output of the row decoder 2 opens all the word lines WL (0) to WL (n). The output of the source switch 3 also opens all the source lines SL (0) to SL (k). The column decoder 4 and the column switch 5 deselect all the bit lines, and all the bit lines are open. Negative voltage decoder 6 is connected to all word lines W
A negative voltage (−VG) of about −10 V is applied to L (0) to WL (n).
2), and the erase circuit 7 outputs all the source lines SL
A positive voltage (VP) of about 5 V with respect to (0) to SL (k)
Output 2).

As described above, by setting the voltage relationship in each mode as shown in FIGS. 3 to 5, in the memory cell which is not selected in the read mode, it is connected to the selected word line. Only the potential of the control gate of the unselected memory cell sharing the source with the selected memory cell is set to −VG1, and the sources of the other unselected memory cells are open. Therefore, the current flowing through the selected bit line is only the cell current of the selected memory cell, and a normal read operation can be performed even when the threshold value of the non-selected memory cell is 0 V or less. it can.

In the above description, all the memory cells are erased collectively in the erasing operation. However, block erasing for erasing only designated memory cells, that is, erasing in response to an address signal is performed. It is also possible to adopt a configuration in which an operation of designating a block and partially erasing is realized. Next, FIGS. 6 and 7 show circuit configuration examples of the row decoder 2, the source switch 3, the negative voltage decoder 6, and the erasing circuit 7 for realizing the voltage conditions in each mode shown in FIGS. I will explain while.

FIG. 6 is a diagram showing a circuit configuration example of the row decoder 2 and the source switch 3. Row decoder 2
Each source line S of the memory cells commonly connected by the diffusion layer
It has a circuit configuration including a plurality of basic circuits 600 for driving two word lines sandwiching L (0) to SL (k), and receives a row address signal RA (0: i) to receive a row address signal RA (0: i). Word line WL connected to control gate
(0) to output signals for driving WL (n).

The OR gates 601 (602) are supplied with address signals RA1 to RAi excluding the least significant bit RA0 of the input row address (RA0 to RAi), and output decoded signals of the address signals RA1 to RAi. That is, the OR gates 601 (602) are connected to the source lines SL (0) to SL of memory cells commonly connected by the diffusion layer.
A selection signal is output in units of two word lines sandwiching SL (k).

The NOR gates 604 and 605 (606)
And 607) have a common OR gate 60
1 (602) is connected to the NOR gate 604
The other input of (606) is connected to the least significant bit signal RA0 of the input row address, and the NOR gate 605 (6)
07) is connected to the inverted signal of the least significant bit signal RA0 by the inverter 603. This NOR
Gates 604 and 605 (606 and 607) form a selection signal corresponding to one word line selected by the input row address (RA0 to RAi).

The NOR gates 604, 605 (606, 6
07) output through word lines WL (0), WL (1) (WL (n-1), W (p) through p-channel depletion transistors MP1, MP2 (MP3, MP4), respectively.
L (n)). The gates of the p-channel depletion transistors MP1, MP2 (MP3, MP4) are cross-connected to their sources.

The source lines SL (0) to SL (k) are connected to an n-channel transistor MN1 whose source is grounded.
The drain of (MN2) is connected, and the n-channel transistor MN1 (MN2) is connected to the OR gate 601 (602).
Is driven by a signal inverted by the inverter 608 (209). In a read operation, a row address signal (RA0-RA) for selecting the word line WL (0).
When i) is input, only the output of the OR gate 601 has a low (low) potential, and all the outputs of the other OR gates have a high (high) potential. NOR gates 604 and 605 (6) to which the output of OR gate 601 (602) is connected.
06 and 607), only the output of the NOR gate 604 is at the high level, and the outputs of the other NOR gates corresponding to the word lines WL (1) to WL (n) are all at the low level. Therefore, p connected to NOR gate 604
The channel depletion transistor MP1 is turned on, and the p-channel depletion transistor MP2 connected to the NOR gate 605 is cut off. Further, the other p corresponding to the word lines WL (2) to WL (n)
The gate and source potentials of all the channel depletion transistors are 0 V and turned on, and the word line W
A ground potential is supplied to L (2) to WL (n).

The output of the OR gate 601 (602) is connected to the n-channel transistor MN1 (MN2) via the inverter 608 (609).
Only the n-channel transistor MN1 connected to (0) is turned on, and all the n-channel transistors connected to the other source lines SL (1) to SL (k) are cut off.

According to the circuit configuration example shown in FIG. 6, in the read operation, as shown in FIG. 3, only the selected word line WL (0) is set to the VCC potential, and the selected word line WL (0) is connected to the selected word line WL (0). The unselected word line WL (1) connected to the opposite memory cell sharing the source with the connected memory cell can be opened, and the other word line potential can be set to the ground potential.

In the write operation, the same operation as the read operation is performed, and the power supply voltage applied to the row decoder 2 is set to VP1, so that only the selected word line WL (0) has the VP1 potential as shown in FIG. And open the unselected word line WL (1) connected to the opposite memory cell sharing the source with the memory cell connected to the selected word line WL (0), and set the other word line potential Can be a ground potential.

In the erase operation, the erase signal ER
By setting ASE to a high level, the outputs of all the OR gates 601 to 602 go to a high level, and all the NOR gates 604 to 607 go to a low level. At this time, by setting the substrate potential of all the p-channel depletion transistors MP1 to MP4 to VS2, all the p-channel depletion transistors MP1 to MP4 are cut off, and as shown in FIG. The potentials of (0) to WL (n) are made open. The substrate potential of VS2 is, for example, a potential of +3 V, and is cut off by the substrate bias effect when the sources and gates of the p-channel depletion transistors MP1 to MP4 are at low level. At this time, since the outputs of the OR gates 601 and 602 are at the high level, the inverter 608
609 through n-channel transistors MN1 to MN
Since the gate potential of No. 2 is at a low level, it is cut off and the potentials of all the source lines SL (0) to SL (k) are open.

FIG. 7 shows a negative voltage decoder 6 and an erase circuit 7.
FIG. 3 is a diagram showing a circuit configuration example of FIG. The negative voltage decoder 6 is connected to each of the source lines SL of the memory cells commonly connected by the diffusion layer.
It has a circuit configuration including a plurality of basic circuits 700 for driving two word lines sandwiching (0) to SL (k).
Receiving a row address signal RA (0: i), a word line WL connected to a control gate of a memory cell transistor
(0) to output signals for driving WL (n).

The OR gates 701 and 702 receive the address signals RA1 to RAi excluding the least significant bit RA0 of the input row address (RA0 to RAi), and output signals decoded from the address signals RA1 to RAi. That is, the OR gates 701 (702) are connected to the source lines SL (0) to SL of the memory cells commonly connected by the diffusion layer.
A selection signal is output in units of two word lines sandwiching (k). OR gates 703 and 704 (705 and 7
06) is connected to one input of a common OR gate 701 (70
2), and the other input of the OR gate 703 (705) is connected to the least significant bit signal R of the input row address.
A0 is connected to the other input of the OR gate 704 (706).
The inverted signal of 0 is connected. The OR gates 703 and 704 (705 and 706) form a selection signal corresponding to one word line selected by the input row address (RA0 to RAi).

OR gates 703, 704 (705, 70
6) are output from AND gates 707 and 708 (7
09, 710) and one of the inputs
The other inputs of the gates 707 and 708 (709 and 710) are commonly connected, and the erase signal Erase is input.
The outputs of the AND gates 707 and 708 (709 and 710) are respectively connected to the negative voltage switches SW1 and SW2 (SW3 and SW3).
SW4), and when these negative voltage switches SW1 and SW2 (SW3 and SW4) are driven, a negative voltage is supplied to the word lines WL (0) to WL (n).
The erase signal Erase is a signal that is set to a high level during the read and write operations and is set to a low level during the erase operation.

In the read and write operations,
OR gates 703 and 704 (705 and 706)
, The least significant bit signal R of the input row address
When the row address signal RA (0: i) is input by A0 and the inverted signal from the inverter 711 and the row decoder 2 outputs a signal for selecting the word line WL (0), the negative voltage decoder 6 , And the output of the AND gate 708 drives the negative voltage switch SW2 to operate so that the negative voltage −VG1 is supplied to the word line WL (1).

The erase circuit 7 includes source lines SL (0) to SL
Tri-state inverter 712 connected to (k)
(713) is changed to the erase signal Erase and the inverter 71.
4 is controlled by the output. The input of the tri-state inverter 712 (713) is grounded. According to the circuit configuration example shown in FIG. 7, in the read operation, as shown in FIG. 3, when the word line WL (0) is selected by the row address signal RA (0: i), the selected word line WL Only the switch SW2 connected to the unselected word line WL (1) connected to the memory cell facing the memory cell connected to (0) and sharing the source is driven, and only the word line WL (1) is connected. A negative voltage -VG1 is supplied, and all other word lines can be left open. At this time, the operation of the erasing circuit 7 is based on the erasing signal Era.
Since se is set to the high level and the output of the inverter 714 is set to the low level, all the tri-state inverters 712 to 713 are set to the open output state, and the source lines SL (0) to SL (k) are all open. . In the write operation, the same operation as the read operation is performed.

In the erase operation, the erase signal Erase
Is at a low level, the outputs of the AND gates 707 to 710 in the negative voltage decoder 6 are all at a low level, all the negative voltage switches SW1 to SW4 are driven, and all the word lines WL (0) ~ WL (n)
Is supplied with a negative voltage -VG2. Further, all of the tri-state inverters 712 to 713 in the erasing circuit 7 are activated, and supply the power supply voltage VP2 applied to the erasing circuit 7 to the source lines SL (0) to SL (k).

As described above, the row decoder 2, source switch 3, negative voltage decoder 6 and erase circuit 7 shown in FIGS.
Can be set for the word lines WL (0) to WL (n) and the source lines SL (0) to SL (k) of the memory cell array 1 in the read, write, and erase operations shown in FIG.

According to this embodiment, in the read operation, the selected word line is set to the positive selection potential (VCC), the common source line to which the selected memory cell is connected is set to the ground potential, and the selected word line is set to the ground potential. 1 connected to a memory cell sharing a source with a memory cell connected to a line
Only the non-selected word lines are negative non-selection potentials (−VG
1), the other unselected word lines are set to the ground potential, and the common source line of the memory cells connected to the other unselected word lines is opened, so that the negative voltage is supplied to one unselected word line. Since only a small circuit is required as a circuit for generating a negative voltage, a memory cell having a threshold value of 0 V or less exists in non-selected memory cells without hindering high density of memory cells. At
No leak current flows through the bit line, and a normal read operation can be performed. As described above, it is possible to realize a semiconductor memory device capable of performing a stable read operation on a memory cell array having a large variation in threshold value after erasing without hindering the increase in the density of memory cells.

Further, since high-accuracy threshold control during the erasing operation is not required, the erasing operation can be speeded up, and the threshold value after erasing can be set to a low value. Thus, the ON current of the memory cell can be increased, and a high-speed read operation can be realized. In the above-described embodiment, the case where the memory cell is formed of an n-channel transistor has been described.
The same effect can be obtained by reversing the negative voltage relationship.

[0051]

According to the present invention, in the read operation, the selected word line is set to the selected potential, the common source line to which the selected memory cell is connected is set to the ground potential, and the memory connected to the selected word line is set. Only one non-selected word line to which a memory cell sharing a cell and a source is connected is set to a non-selection potential having a polarity opposite to the selection potential of the selected word line, the other non-selection word lines are set to a ground potential, and When the common source line of the memory cell connected to the non-selected word line is opened, the selection potential is set to the positive potential and the non-selection potential is set to the negative potential, the negative voltage is supplied to one non-selected word. Since only a single line is required, a small-scale circuit for generating a negative voltage is required, and a memory cell having a threshold value of 0 V or less can be provided to unselected memory cells without hindering high-density memory cells. Even if but present, no leakage current flows in the bit line, it is possible to perform normal read operation. As described above, it is possible to realize a semiconductor memory device capable of performing a stable read operation on a memory cell array having a large variation in threshold value after erasing without hindering the increase in the density of memory cells.

Further, it is not necessary to perform a high-precision threshold control during the erasing operation, so that the erasing operation can be sped up and the threshold value after erasing can be set to a low value. Thus, the ON current of the memory cell can be increased, and a high-speed read operation can be realized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a circuit example of a memory cell array according to the embodiment of the present invention;

FIG. 3 is a diagram showing a voltage relationship in a read operation in the embodiment of the present invention.

FIG. 4 is a diagram showing a voltage relationship in a write operation in the embodiment of the present invention.

FIG. 5 is a diagram showing a voltage relationship in an erase operation in the embodiment of the present invention.

FIG. 6 is a diagram illustrating a circuit configuration example of a row decoder and a source switch according to the embodiment of the present invention;

FIG. 7 is a diagram showing a circuit configuration example of a negative voltage decoder and an erasing circuit according to the embodiment of the present invention;

FIG. 8 is a configuration diagram of a conventional semiconductor memory device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 memory cell array 2 row decoder 3 source switch 4 column decoder 5 column switch 6 negative voltage decoder 7 erase circuit 8 read / write circuit 9 control circuit 10 voltage generation circuit 601 602 OR gate 603 608 609 inverter Inverter 604 to 607 NOR gate 701, 702 OR gate 703-706 NOR gate 707-710 AND gate 711, 714 Inverter 712, 713 Tri-state inverter WL (0) -WL (n) Word line BL (0) -BL (m) Bit line SL (0 ) To SL (k) source line

Claims (3)

[Claims] 1. A memory cell in which said bit line and drain are connected and said word line and control gate are connected at each intersection of a plurality of orthogonally arranged bit lines and a plurality of word lines. A memory cell array connected to a common source line with the source of each set of memory cells shared and a memory cell array selected in the erasing operation, with a set of two adjacent memory cells each having a drain connected to a bit line. Means for applying a high voltage between the connected common source line and the word line; means for applying a selection potential to the word line to which the memory cell selected in the read operation is connected; and means selected in the read operation Means for applying a non-selection potential having a polarity opposite to the selection potential to a word line to which a memory cell sharing a source with a memory cell is connected; Means for applying a ground potential to the remaining word lines, means for applying a ground potential to a common source line connected to a memory cell selected in the read operation, and opening the remaining common source line in the read operation. Semiconductor memory device comprising: 2. The semiconductor memory device according to claim 1, wherein the selection potential is a positive potential, and the non-selection potential is a negative potential. 3. The semiconductor memory according to claim 1, wherein the potential of the word line to which the memory cell selected in the erasing operation is connected has the same polarity as the non-selection potential in the reading operation. apparatus.