JPH1074395A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an output circuit of the semiconductor storage device, capable of outputting an output data in its stable output assurance time, irrespective of fluctuations of a power source voltage and an ambient temp. SOLUTION: A read data RD read out of a memory array 10 is outputted as an output data DQ via a data output buffer 9, and when an activation signal ϕ2 generated by an activation signal generating circuit 7 is inputted, the output data DQ is outputted by the data output buffer 9. The activation signal generating circuit 7 for generating the activation signal ϕ2 is equipped with a timing compensation circuit 14 for suppressing at least either a fluctuation of outputting timing of the activation signal due to a fluctuation of the power cource or a fluctuation of outputting timing of the activation signal ϕ2 due to a fluctuation of the ambient temp.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an output circuit of a semiconductor memory device. In semiconductor memory devices in recent years, higher integration, lower power consumption, and higher operation speed are increasingly demanded. Therefore, in such a semiconductor memory device, in order to increase the operating speed, it is necessary to realize an output circuit that operates stably irrespective of fluctuations in the power supply voltage and the ambient temperature.

[0002]

2. Description of the Related Art In a read operation of cell information in a conventional semiconductor memory device, for example, as shown in FIG. 7, when an output control signal OE bar is at an L level and a control signal CAS bar falls to an L level, Cell information is read from the storage cell selected by the input address signal.

Then, based on the fall and rise of the control signal CAS, valid output data DQv and invalid data DQu are alternately output from the output circuit. From the fall of the control signal CAS to the output of valid output data DQv, there is a difference between the delay times t1 and t2 due to fluctuations in the power supply voltage or changes in the ambient temperature.

Therefore, in order to guarantee the operation of the output data DQv1 output at the minimum delay time t1 and the output data DQv2 output at the maximum delay time t2, the operation is guaranteed. Data DQv
Of the output data DQv1, DQ
v2 is set to the time when both are output.

[0005]

In the semiconductor memory device as described above, as the fluctuation of the output delay time of the output data DQv due to the fluctuation of the power supply voltage or the fluctuation of the ambient temperature increases, the output guarantee time t3 becomes shorter.

Then, there is a problem that the data output operation becomes unstable as the output guarantee time t3 becomes shorter. An object of the present invention is to provide an output circuit of a semiconductor memory device capable of outputting output data with a stable output guarantee time regardless of changes in a power supply voltage and an ambient temperature.

[0007]

FIG. 1 is a diagram for explaining the principle of claim 1. That is, the read data RD read from the memory cell array 10 is transmitted to the data output buffer 9.
And the data output buffer 9 outputs the output data DQ when the activation signal φ2 generated by the activation signal generation circuit 7 is input. The activation signal generation circuit 7 for generating the activation signal φ2 includes at least a change in output timing of the activation signal due to a change in power supply and a change in output timing of the activation signal φ2 due to a change in ambient temperature. A timing compensation circuit 14 for suppressing either of them is provided.

According to a second aspect of the present invention, the timing compensation circuit includes a power supply circuit for supplying an internal power supply to the activation signal generation circuit based on an external power supply supplied from the outside, and the power supply circuit reduces the ambient temperature. And the internal power supply voltage is increased based on an increase in ambient temperature.

According to a third aspect of the present invention, the timing compensation circuit comprises a power supply circuit for supplying an internal power supply to the activation signal generation circuit based on an external power supply supplied from the outside, and the power supply circuit comprises the external power supply voltage. Supply the internal power with the fluctuation of the power supply suppressed.

According to a fourth aspect of the present invention, the power supply circuit comprises a first power supply circuit for generating an internal high-potential-side power supply and a second power supply circuit for generating an internal low-potential-side power supply. The power supply circuit includes a resistor and a diode-connected P-channel MOS transistor connected in series between an external high-potential power supply and an external low-potential power supply, and a gate connected to a source of the P-channel MOS transistor. A P-channel MOS transistor connected to the external high-potential-side power supply and outputting an internal high-potential-side power supply from a drain, wherein the second power supply circuit includes an external high-potential-side power supply and an external low-potential-side power supply. A diode-connected N-channel MOS transistor and a resistor connected in series between the gate and a source connected to the gate of the N-channel MOS transistor;
A source is connected to the low-potential-side external power supply, and an N-channel MOS transistor that outputs an internal low-potential-side power supply from a drain.

(Operation) According to the first aspect of the present invention, the operation of the timing compensation circuit causes at least a change in output timing of the activation signal due to a change in power supply and a change in output timing of the activation signal due to a change in ambient temperature. Either is suppressed.

According to the second and fourth aspects, when the ambient temperature decreases, the internal power supplied to the activation signal generation circuit decreases. When the ambient temperature increases, the internal power supplied to the activation signal generation circuit increases. I do.

According to the third and fourth aspects, when the external power supply voltage increases, the internal power supply supplied to the activation signal generation circuit decreases. When the external power supply voltage decreases, the internal power supply supplied to the activation signal generation circuit decreases. Rises.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) FIG. 2 shows a semiconductor memory device embodying the present invention. Control signal RA input from outside
S bar and CAS bar are clock generators 1a and 1
b.

A control signal generated by the clock generator 1a based on the control signals RAS bar and CAS bar is input to a row decoder 2 and a sense amplifier / I / O gate 3. Then, the row decoder 2 and the sense amplifier / I / O gate 3 operate based on the input control signal.

The control signal generated by the clock generator 1b is supplied to a column decoder 4, an address buffer
While being input to the predecoder 5, the control signal φ is supplied to the write clock generator 6 and the activation signal generation circuit 7.
Entered as 1.

The address buffer / predecoder 5 receives address signals A0 to An, and outputs a predecode signal based on the address signals A0 to An to the row decoder 2 and the column decoder 4. Then, a specific storage cell in the memory cell array 10 is selected by the word line selection signal output from the row decoder 2 and the column selection signal output from the column decoder 4.

The write clock generator 6 activates the data input buffer 8 during a write operation based on a write control signal WE input from the outside and the control signal φ1. The data input buffer 8
Is used to transfer write data DQ0 to DQn input from outside during a write operation to the sense amplifier / I / O gate 3.
Output to

The activation signal generation circuit 7 generates a control signal φ2 based on the control signal φ1 and an output control signal OE externally input during a read operation, and outputs the control signal φ2 to the data output buffer 9.

The data output buffer 9 has a control signal φ.
2, the read data output from the sense amplifier / I / O gate 3 during the read operation is
Output as output data DQ0-DQn.

In the semiconductor memory device configured as described above, the write operation and the read operation are set based on the control signals RAS bar, CAS bar, write control signal WE bar, and output control signal OE bar.

During a write operation, externally input write data DQ0 to DQn are supplied to the memory cell selected based on the address signals A0 to An via the data input buffer 8 and the sense amplifier / I / O gate 3. During write and read operations, address signals A0-A
Cell information read from the storage cell selected based on n is output as output data DQ0 to DQn via the sense amplifier / I / O gate 3 and the data output buffer 9.

FIGS. 3 and 4 show a specific configuration of the activation signal generation circuit 7. FIG. FIG. 3 shows the power supply circuit 14 of the activation signal generation circuit 7. The source of the P-channel MOS transistor Tr1 is connected to a power supply VDD supplied from outside via a resistor R1, and the gate and drain are
Connected to the power supply Vss, the transistor Tr1 operates as a diode.

The node N1, which is the source of the transistor Tr1, is connected to the gate of a P-channel MOS transistor Tr2, the source of which is connected to the power supply VDD, and the high-potential-side internal power supply VDDc is output from the drain.

The drain and the gate of the N-channel MOS transistor Tr3 are connected to a power supply VDD, and the source is a resistor R
2 connected to the power supply Vss through the transistor Tr3
Operates as a diode. The node N2, which is the source of the transistor Tr3, is connected to the gate of the N-channel MOS transistor Tr4. The source of the transistor Tr4 is connected to the power supply Vss, and the low-potential-side internal power supply Vssc is output from the drain.

In the power supply circuit 14 configured as described above,
When the ambient temperature decreases, the threshold value of the transistor Tr1 increases. Then, since the potential of the node N1 rises, the drain current of the transistor Tr2 decreases, and the internal power supply VDD
The voltage level of c decreases. On the other hand, when the ambient temperature increases, the threshold value of the transistor Tr1 decreases. Then, since the potential of the node N1 decreases, the drain current of the transistor Tr2 increases, and the voltage level of the internal power supply VDDc increases.

When the ambient temperature decreases, the threshold value of the transistor Tr3 increases. Then, the potential of the node N2 decreases, the drain current of the transistor Tr4 decreases, and the voltage level of the internal power supply Vssc increases. On the other hand, when the ambient temperature increases, the threshold value of the transistor Tr3 decreases. Then, the potential of the node N2 increases, the drain current of the transistor Tr4 increases, and the voltage level of the internal power supply Vssc decreases.

When the power supply VDD rises, the potential of the node N1 rises, the drain current of the transistor Tr2 decreases, and the rise of the internal power supply VDDc is suppressed. Power supply V
When DD decreases, the potential of the node N1 decreases, the drain current of the transistor Tr2 increases, and the decrease of the internal power supply VDDc is suppressed.

When the power supply VDD rises, the node N2
, The drain current of the transistor Tr4 increases, and the internal power supply Vssc decreases. When the power supply VDD decreases, the potential of the node N2 decreases, the drain current of the transistor Tr4 decreases, and the internal power supply Vssc increases.

FIG. 4 shows the activation signal generation circuit 7. The internal power supplies VDDc and Vssc are supplied to the NAND circuit 11a and the inverter circuits 12a and 12b constituting the activation signal generation circuit 7.

The control signal φ1 is supplied to the NAND circuit 11a
And the output control signal OE is input to the NAND circuit 11a via the inverter circuit 12a. The output signal of the NAND circuit 11a is output as a control signal φ2 via a three-stage inverter circuit 12b.

When the control signal φ1 goes high when the output control signal OE is at the low level, the output signal of the NAND circuit 11a goes low.
Level, and the control signal φ2 becomes H level after the operation delay time of the inverter circuit 12b.

When output control signal OE is at H level or when control signal φ1 is at L level, NA
Since the output signal of ND circuit 11a is at H level, control signal φ2 is at L level.

FIG. 5 shows a specific configuration of the data output buffer 9. The control signal φ2 is supplied to the NAND circuit 11
and input to the NOR circuit 13 via the inverter circuit 12c.

The read data RD input to the data output buffer 9 is supplied to the NAND circuit 11b and the NO
The signal is input to the R circuit 13. And the NAND circuit 1
The output signal 1b is input to the gate of a pull-up output transistor Tr5 composed of a P-channel MOS transistor, and the output signal of the NOR circuit 13 is a pull-down output transistor Tr6 composed of an N-channel MOS transistor. Input to the gate.

The source of the output transistor Tr5 is connected to a power supply VDD, the drains of the output transistors Tr5 and Tr6 are connected to an output terminal connected to each other to output an output signal DQ, and the source of the output transistor Tr6 is Connected to power supply Vss.

In the data output buffer 7 configured as described above, when the control signal φ2 goes low, the output signal of the NAND circuit 11b goes high and the output signal of the NOR circuit 13 goes low. Then, the output transistor Tr5,
Both Tr6 are turned off, and the output data DQ becomes high impedance.

When the control signal φ2 goes high,
Output data DQ attains H level or L level based on read data RD. Next, a data read operation of the semiconductor memory device configured as described above will be described.

When the read operation is set by the control signal RAS and the L level output control signal OE, the control signal φ1 goes high and the control signal φ2 goes high.

Then, the output transistors Tr5 and Tr6 are activated, and the output data DQ based on the read data RD is output.
Is output. The output of the output data DQ is started based on the rise of the control signal φ2.

The rising timing of the control signal φ2 is adjusted by the activation signal generation circuit 7. That is, when the ambient temperature decreases, the current driving capability of the MOS transistor increases, and the operation speed of the activation signal generation circuit 7 increases.

At this time, due to the operation of the power supply circuit 14 of the activation signal generation circuit 7, the internal power supply VDDc decreases and the internal power supply Vssc increases. Therefore, the improvement in the operation speed of the activation signal generation circuit 7 due to the decrease in the ambient temperature is offset by the decrease in the internal power supply voltage. Is suppressed.

When the ambient temperature increases, the current driving capability of the MOS transistor decreases, and the operating speed of the activation signal generation circuit 7 decreases. At this time, the operation of the power supply circuit 14 of the activation signal generation circuit 7 causes the internal power supply VDD to operate.
c rises and the internal power supply Vssc falls. Therefore, the decrease in the operating speed of the activation signal generation circuit 7 due to the rise in the ambient temperature is offset by the rise in the internal power supply voltage. As a result, even if the ambient temperature rises, the timing of the rise of the control signal φ2 changes. Is suppressed.

Further, when the power supply VDD rises, the current driving capability of the MOS transistor also rises. Therefore, if the power supply VDD is supplied to the activation signal generation circuit 7, the operation speed is improved.

However, the activation signal generation circuit 7 is supplied with internal power from the power supply circuit 14,
By this operation, the rise of the internal power supply VDDc is suppressed even if the power supply VDD rises. Therefore, a change in the operation speed of the activation signal generation circuit 7 due to the rise of the power supply VDD is suppressed, and
As a result, even if the power supply VDD rises, a change in the rising timing of the control signal φ2 is suppressed.

When the power supply VDD decreases, the current driving capability of the MOS transistor decreases, so that if the power supply VDD is supplied to the activation signal generation circuit 7, the operation speed decreases.

However, the activation signal generation circuit 7 is supplied with internal power from the power supply circuit 14,
By this operation, even if the power supply VDD decreases, the decrease in the internal power supply VDDc is suppressed. Accordingly, a change in the operation speed of the activation signal generation circuit 7 due to a decrease in the power supply VDD is suppressed, and
As a result, even if the power supply VDD drops, a change in the rising timing of the control signal φ2 is suppressed.

As described above, in this semiconductor memory device, it is possible to suppress a change in the rising timing of the control signal φ2 due to a change in the ambient temperature or a change in the power supply VDD supplied from the outside.

Therefore, as shown in FIG. 6, even when the ambient temperature or the power supply VDD changes, the change in the delay time from the fall of the control signal CAS to the start of the output of the output signal DQv is suppressed. be able to. As a result, the time during which the valid output signal DQv is output can be substantially equal to the output guarantee time t4, so that the data output operation can be almost stabilized.

[0050]

As described in detail above, the present invention can provide a semiconductor memory device capable of outputting output data with a stable output guarantee time regardless of changes in power supply voltage and ambient temperature.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram illustrating a semiconductor memory device according to one embodiment;

FIG. 3 is a circuit diagram showing a power supply circuit of an activation signal generation circuit.

FIG. 4 is a circuit diagram showing an activation signal generation circuit.

FIG. 5 is a circuit diagram showing a data output buffer.

FIG. 6 is a timing waveform chart showing a data read operation according to one embodiment.

FIG. 7 is a timing waveform diagram showing a data read operation of a conventional example.

[Explanation of symbols]

 7 Activation signal generation circuit 9 Data output buffer 10 Memory cell array 14 Timing compensation circuit RD Read data φ2 Activation signal DQ Output data

Claims (4)

[Claims] 1. A read data read from a memory cell array is output as output data via a data output buffer. The data output buffer receives an activation signal generated by the activation signal generation circuit. A semiconductor memory device that outputs the output data when the activation signal generation circuit generates the activation signal. And a timing compensating circuit for suppressing at least one of fluctuations in the output timing of the activation signal. 2. The power supply circuit according to claim 1, wherein the power supply circuit supplies an internal power supply to the activation signal generation circuit based on an external power supply supplied from the outside. Reducing the internal power supply voltage,
2. The semiconductor memory device according to claim 1, wherein said internal power supply voltage is increased based on an increase in ambient temperature. 3. The timing compensation circuit comprises a power supply circuit for supplying an internal power supply to the activation signal generation circuit based on an external power supply supplied from outside, and the power supply circuit detects a change in the external power supply voltage. 2. The semiconductor memory device according to claim 1, wherein a suppressed internal power is supplied. 4. The power supply circuit includes a first power supply circuit that generates an internal high-potential-side power supply, and a second power supply circuit that generates an internal low-potential-side power supply. A resistor- and diode-connected P-channel MOS transistor connected in series between an external high-potential power supply and an external low-potential power supply; a gate connected to the source of the P-channel MOS transistor; P-channel MOS connected to the potential side power supply and outputting the internal high potential side power supply from the drain
A second N-channel MOS transistor and a resistor connected in series between an external high-potential-side power supply and an external low-potential-side power supply; and the N-channel MOS transistor. An N-channel MOS having a gate connected to the source of the N-channel MOS transistor, a source connected to the external power source on the low potential side, and an internal low potential side output from the drain
4. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is constituted by a transistor.