JPH1070098A - Planarization method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To polish a substrate where wide and narrow recesses are mixed uniformly by employing a method for temporarily achieving planarization in the way of first polishing for a second easy polishing layer and a third polishing stop layer and then achieving complete planarization by continuing second polishing. SOLUTION: A first polishing stop layer 21, a first easy polishing layer 31, a second polishing stop layer 22, a second easy polishing layer 32 and a third polishing stop layer 23 are deposited sequentially. The third polishing stop layer 23 and the second easy polishing layer 32 are then polished by first polishing, i.e., chemical mechanical polishing, until the second polishing stop layer 22 is exposed at a protrusion on a substrate 10. After achieving temporary planarization by first polishing, second polishing, i.e., chemical mechanical polishing, is performed. More specifically, the second polishing stop layer 22, the first easy polishing layer 31 and the second easy polishing layer 32 are polished until the first polishing stop layer 21 at a protrusion on the substrate and the second polishing stop layer 22 at a recess in the substrate are exposed. Uniform polishing can be performed by taking account of each polishing speed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a planarization method applicable to planarization of a so-called trench element isolation region of a semiconductor device and planarization of an interlayer insulating film.

[0002]

2. Description of the Related Art Heretofore, a so-called LOCOS method has been used as an element isolation of a semiconductor device. However, this LOCOS method has a problem that a portion covered with a silicon nitride film at the time of manufacturing. Since the oxide film penetrates into the ends of the substrate, bird's beak is generated, and the area of the bird's beak becomes unnecessary, which is disadvantageous for miniaturization and large capacity.

[0003] Therefore, a groove is formed vertically in a semiconductor substrate by reactive ion etching or the like, an insulating film is deposited including the inside of the groove, and the other parts than the groove are polished by CMP (chemical mechanical polishing) or the like. There is a so-called trench element isolation method in which the trench is polished by a method to leave an insulating film in the trench, thereby filling the trench with the insulating film. According to this method, there is no bird's beak, which is advantageous for improving the degree of integration.

However, in this trench element isolation method, as shown in FIG. 3, when the substrate 10 has a portion WT having a large trench width and a portion NT having a small trench width, the insulating layer IL filling the uneven portion of the substrate is formed by CMP or the like. During polishing, as shown by a broken line in the figure, there is a problem that the insulating film of the trench WT having a large trench width is excessively ground, and the planarization of the entire semiconductor device becomes insufficient.

On the other hand, if the interlayer insulating film of the semiconductor device has irregularities, it may exceed the exposure depth of photolithography, and the line width of the resist pattern may fluctuate, and a predetermined pattern may not be obtained. Further, if the interlayer insulating film on which the wiring is provided has irregularities, there is a problem that the step coverage deteriorates at the step portion, the yield decreases, and the resistance of the wiring layer increases. Therefore, the planarization technique of the interlayer insulating film is important, and among the planarization techniques, the mechanical polishing and the chemical mechanical polishing are more uniform planarization methods such as BPSG reflow. In the case where there is a concave portion, there is a problem that polishing proceeds in a wide portion thereof and planarization becomes insufficient.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a flattening method capable of uniformly polishing a substrate having a mixture of a large-area concave portion and a small-area concave portion.

[0007]

According to the present invention, in order to achieve the above object, a first polishing stopper layer is formed on at least a convex portion of a substrate having a concave portion and a convex portion. The first polishing layer having a higher polishing rate covers the uneven portion of the substrate including the first polishing stopper layer, and the polishing rate is higher than that of the first polishing layer on the first polishing layer. Forming a small second polishing stop layer, forming a second easy polishing layer having a higher polishing rate than the second polishing stop layer on the second polishing stop layer,
A third polishing stopper layer having a lower polishing rate than that of the second polishing layer is formed on the second polishing layer, and the third polishing stopper layer exists in the concave portion of the base and the convex portion of the substrate. A first polishing step of polishing the third polishing stop layer and the second easy-polishing layer until the second polishing stop layer is reached; and after the first polishing step, a first polishing step existing in the concave portion of the base. Polishing the third polishing stop layer, the second easy-polishing layer, and the second polishing stop layer until reaching the second polishing stop layer and the first polishing stop layer existing in the convex portion of the base. And a polishing step.

According to the planarization method of the present invention, the first projection is formed on the projection of the base.
Then, a first easy-polishing layer, a second polishing-stopping layer, a second easy-polishing layer, and a third polishing-stopping layer are sequentially laminated so as to cover the irregularities of the substrate. The two easy polishing layers are 3
The polishing rate is higher than the polishing stop layer of the layer. In this case, the height of the upper surface of the third polishing stop layer in the concave portion of the substrate and the height of the upper surface of the second polishing layer in the convex portion of the substrate from the bottom surface of the concave portion of the substrate are made substantially equal. Further, the height of the upper surface of the second polishing stopper layer in the concave portion of the substrate and the height of the upper surface of the first polishing stopper layer in the convex portion of the substrate from the bottom surface of the concave portion of the substrate are made substantially equal.

After forming each layer on the substrate as described above, first, the first polishing is performed, and the third polishing stop layer and the second easy-polishing layer are polished. Then, in the convex portion of the base, the third polishing stopper layer is firstly shaved, and then the second easy-polishing layer is shaved. Since the second easy-polishing layer is easily polished, the polishing proceeds quickly. Since the upper surface of the third polishing stopper layer in the concave portion and the upper surface of the second polishing stopper layer in the convex portion are substantially the same height, the second polishing stopper layer is exposed in the convex portion of the base, and In the recess, polishing of the third polishing stopper layer starts. Since the second polishing stop layer and the third polishing stop layer have a low polishing speed, the polishing speed is temporarily reduced here. Therefore, the end of the first polishing can be easily determined. When this first polishing is completed,
Since there is a polishing stopper layer on both the concave portion and the convex portion of the base, even if the area of the concave portion is large, polishing of the concave portion is not performed rapidly, and polishing of a uniform thickness is achieved as a whole.

Next, a second polishing is performed. Since polishing with a uniform thickness has been achieved in the first polishing, it is preferable to perform polishing in the second polishing so that the entire polishing is uniform. In the second polishing, first, the third polishing stopper layer existing in the concave portion of the substrate and the second polishing stopper layer existing in the convex portion of the substrate are removed. Then, the first easy-polishing layer existing in the convex portion of the base and the second easy-polishing layer in the concave portion of the base are mainly scraped. Preferably, the polishing rates of the first easy-polishing layer and the second easy-polishing layer are set to be approximately the same. Since the upper surface of the second polishing stopper layer in the concave portion and the upper surface of the first polishing stopper layer in the convex portion are substantially the same height, the first polishing stopper layer existing in the convex portion of the base is exposed, and The second polishing stop layer in the recess is exposed. Since these polishing stopper layers have a low polishing rate, the polishing can be easily stopped here.

As a result, in the concave portion of the base, the second polishing stopper layer prevents the concave portion from being further polished,
In the convex portion of the substrate, the first polishing stopper layer prevents further polishing, so that even if there is a concave portion having a large area, uniform polishing can be achieved over the entire concave / convex portion of the substrate.

In this case, the first polishing and the second polishing can be performed continuously under the same conditions, and do not necessarily mean different polishing. As described above, the planarization method of the present invention employs a method of achieving planarization once (first polishing) during polishing, and then continuing polishing to achieve planarization (second polishing). ing. Therefore, local polishing can be prevented, the surface to be polished can be uniformly polished, and the entire surface to be polished can be flattened.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below, but the present invention is not limited to the following embodiments. The planarization method of the present invention achieves planarization by combining a polishing stopper layer and an easy polishing layer. Here, the polishing stop layer and the easy-polishing layer mean that the relative polishing rates are small and large, respectively.
This is a relative value that varies depending on the polishing method. For example, when CMP is used, the polishing rate increases, but in some cases, the polishing rate decreases in normal mechanical polishing. [First Embodiment] In this embodiment, a planarization method for forming a so-called trench element isolation region will be described with reference to FIG.

First, as shown in FIG. 1A, in order to relieve the stress of, for example, a silicon nitride film to be formed later on a semiconductor substrate 10 as a base, a silicon oxide film 20 of, eg, 50 nm is formed by a conventional CVD method. Then, a silicon nitride film 21 as a first polishing stopper layer is deposited to a thickness of, for example, about 100 nm by a conventional CVD method. Thereafter, the resist R1 is opened only in the element isolation region by photolithography so as to form the narrow isolation region NT and the wide isolation region WT. Next, the silicon nitride film 21, the silicon oxide film 20, and the silicon substrate 10 are etched by performing anisotropic etching by reactive ion etching or the like according to a conventional method. At this time, the silicon substrate etching amount (trench depth) H ₀ is, for example, 500
nm. As a result, as shown in FIG. 1A, a structure in which the first polishing stopper layer 21 exists in the convex portion (substrate surface) of the substrate having the narrow trench NT and the wide trench WT. In this case, the height convex H ₁ of the upper surface of the first polishing stopper layer 21, when referenced to the substrate recess surface 11 (reference point hereinafter the same) is 500 + 50 + 100 = 650nm.

After the trenches NT and WT are formed in the substrate, as shown in FIG. 1B, the resist R1 is removed, and the silicon oxide film 31 as the first easily polished layer is formed by a low pressure CVD method or the like. Deposit 500 nm by a normal pressure CVD method or the like. The silicon oxide film 31 is a material that fills the trenches NT and WT to form a trench isolation region. afterwards,
For example, a silicon nitride film 22 as a second polishing stopper layer is deposited to a thickness of 150 nm by a CVD method or the like. Next, for example, a BPSG film 32 as a second easy-to-polish layer is
A 600 nm is deposited by the method D, and a silicon oxide film 23 as a third polishing stopper layer is further deposited to a thickness of 100 nm, for example. As the third polishing stopper layer 23, silicon nitride may be deposited.

In this case, the silicon oxide 31 as the first easily polished layer has a higher polishing rate than silicon nitride when the mechanical polishing property of CMP is high, and becomes an easily polished layer in relation to silicon nitride. However, when polishing is performed by increasing the chemical polishing property by CMP, for example, the polishing rate is lower than that of BPSG, and it may be a polishing stop layer in relation to BPSG. This is a relative concept that changes depending on the polishing conditions of the easy-polishing layer and the polishing stopper layer. Examples of the polishing stopper layer include, in addition to the above silicon nitride and silicon oxide, ceramics such as alumina and TiO ₂ , metal oxides, and the like.
In addition, as the easily polished layer, besides BPSG, for example, polycrystalline silicon, PSG, BSG, AsSG, PbS
Silicon oxide containing impurities such as G and SbSG can be given as an example.

Further, as shown in FIG. 1B, the height H of the upper surface of the convex portion of the substrate of the second polishing stopper layer 22 is raised.
₂ is 500 + 150 + 500 + 150 = 1300n
m, the height H ₂ of the upper surface of the concave portion of the substrate of the second polishing stopper layer 22 is 500 + 150 = 650 nm, and the height H of the upper surface of the concave portion of the substrate of the third polishing stopper layer 23 is H
₃ is 500 + 150 + 600 + 100 = 1350 nm
It is. That is, the first polishing stopper layer 2 in the substrate convex portion
1 of the height of the upper surface convex H ₁ = the height concave H ₂ = 650 nm of the upper surface of the second polishing stopper layer 22 in the substrate recess, has a substantially equal height. In addition, the second in the substrate convex portion
Height convexity H ₂ of upper surface of polishing stopper layer 22 = 1300 nm ≒ Height concave height H of upper surface of third polishing stopper layer 23 in substrate concave portion
_The heights are almost equal at ₃ = 1350 nm. The term “substantially equal” as used herein is a relatively broad concept including a variation in the thickness of the polished surface including an error due to a measurement error and a measurement location within an allowable range of the variation. The height H of the upper surface of the third polishing stopper layer 23 in the recess of the substrate is H.
_The reason why ₃ is slightly higher than the height H ₃ of the third polishing stopper layer 23 in the convex portion of the substrate is that the third polishing stopper layer 23 in the concave portion is slightly polished while the BPSG layer 32 is being polished. Therefore, a margin is given.

After forming a multi-layer polishing layer as shown in FIG. 1B, as shown in FIG.
For example, by a chemical mechanical polishing method, a silicon oxide film 23 as a third polishing stopper layer and B as a second easily polished layer
The PSG layer 32 is polished until the silicon nitride film 22 serving as a second polishing stopper layer on the convex portion of the substrate is exposed.
At this time, since the silicon oxide film 22 as the third polishing stopper layer of the substrate convex portion receives a stronger polishing force than the silicon oxide film of the concave portion, the silicon oxide film 23 of the substrate convex portion disappears, and the polishing rate is high. Before the BPSG is rapidly polished and the silicon oxide film 23 in the concave portion does not disappear, the silicon nitride film 22 in the convex portion is exposed. At this time, since the silicon nitride film 22 in the convex portion and the silicon oxide film 23 in the concave portion are almost the same height, the surface becomes flat.

As the first polishing, it is preferable to use CMP having a large chemical action. Polishing of glass containing impurities such as BPSG progresses due to a chemical reaction between the impurities and the polishing solution, so that a large difference is generated in the polishing rate between the BPSG film and the silicon oxide film, and the silicon oxide 23 in the substrate recesses is formed. A process of polishing only the BPSG 32 without polishing the substrate.

After the planarization is once achieved by the first polishing, the second polishing is further performed by, for example, chemical mechanical polishing, as shown in FIG. In this polishing, a silicon nitride film 22 as a second polishing stopper layer, a silicon oxide 31 as a first easy-polishing layer, and a BPSG layer 3 as a second easy-polishing layer
2 is polished until the silicon nitride film 21 as a first polishing stopper layer of the substrate protrusion and the silicon nitride film 22 as the second polishing stopper layer of the substrate recess are exposed. Second
In the above polishing, it is preferable to employ a polishing method in which the mechanical polishing property of chemical mechanical polishing is enhanced. Thereby, the difference in polishing rate between the silicon oxide film 31 as the first easy-polishing layer and the BPSG layer 32 as the second easy-polishing layer is made smaller than that obtained by the first polishing method, and uniform polishing is performed. Can be.

When the second polishing proceeds, the first protrusion of the substrate
Polishing stopper layer 21 and second polishing stopper layer 22 of substrate recess
Will be exposed almost simultaneously. Since these polishing stopper layers have almost the same height, and the polishing rate of the silicon nitride film is lower than that of the silicon oxide film, if the polishing is stopped before these silicon nitride films disappear, FIG. As shown in FIG. 5, flattening can be achieved.

After flattening, as shown in FIG.
The silicon nitride film 21 is removed by boiling phosphoric acid,
As shown in (f), the silicon oxide film 2 is formed by dilute hydrofluoric acid.
By etching 0, a wafer having a narrow trench isolation region and a wide trench isolation region and having a uniform thickness of these trench isolation regions can be completed.

Therefore, according to the present embodiment, the pattern dependence of the thickness of the element isolation film and the dependence within the wafer plane, which are problems in the formation of the trench element isolation by polishing, are very small. Can be formed, thereby reducing the parasitic capacitance, improving the reliability, and reducing the cost by improving the yield. [Second Embodiment] In this embodiment, an element such as a transistor formed on a semiconductor substrate constitutes a convex portion of a base,
This is a case where the substrate surface forms a concave portion of the substrate. Elements in this case include elements that need to be buried when planarizing an interlayer insulating film, such as a stacked capacitor of a DRAM.

The second embodiment is basically the same as the first embodiment, and uses a three-layer polishing stop layer and two easy-polishing layers, and once flattens at a high speed in the first polishing. After achieving the planarization, a uniform polishing is performed by the second polishing to achieve the planarization. First, as shown in FIG. 2A, a silicon oxide film (not shown) is formed as a first polishing stopper layer over the entire surface of a substrate having elements 13 and 14 such as transistors formed on a semiconductor substrate surface and having irregularities. ) Is, for example, 5
A silicon nitride film 21 is deposited to a thickness of about 100 nm by CVD. In this case, the height convex H ₁ from the substrate surface of the upper surface of the silicon nitride film on the elements 13 and 14 is 650 nm. Note that, unlike the first embodiment, the silicon nitride film 21
The silicon oxide film for stress relaxation below the silicon oxide film is not always necessary, and for example, an offset oxide film on the element can be used.

Next, the silicon oxide film 31 as the first easy-polishing layer is formed to a thickness of 500 nm by a low pressure CVD method, a normal pressure CVD method or the like.
accumulate. Thereafter, for example, a silicon nitride film 22 as a second polishing stopper layer is deposited to a thickness of 150 nm by a CVD method or the like. Next, for example, a BPSG layer 32 as a second easy-to-polish layer is deposited to a thickness of 600 nm by, for example, a low-pressure CVD method, and a silicon oxide film, for example, as a third polishing stopper layer is formed by one layer.
Deposit 00 nm.

Also in this case, the height protrusion H ₂ of the upper surface of the protrusion of the substrate of the second polishing stopper layer 22 is 500 + 150 +
500 + 150 = 1300 nm, the height H ₂ of the upper surface of the concave portion of the substrate of the second polishing stopper layer is 500 + 150.
= 650 nm, the height H ₃ of the upper surface of the concave portion of the substrate of the third polishing stopper layer is 500 + 150 + 600 + 100.
= 1350 nm. That is, the first in the substrate convex portion
The height protrusion H ₁ of the upper surface of the polishing stopper layer 21 of the second polishing stopper = the height recess H ₂ of the upper surface of the second polishing stopper layer 22 in the concave portion of the substrate = 650 n
m, which are almost the same height. Also, the height H ₂ of the upper surface of the second polishing stopper layer 22 at the substrate protrusion is H ₂ = 1.
The height of the upper surface of the third polishing stopper layer 23 in the concave portion of the substrate at 300 nm ≒ the concave height H ₃ = 1350 nm, which is almost the same height.

As in the first embodiment, FIG.
As shown in (b), the first polishing is performed by CMP with enhanced chemical action, the BPSG film 32 is rapidly polished, and the second polishing stop layer 22 of the convex portion of the substrate and the concave portion of the substrate are formed. The first polishing is stopped by using the third polishing stopper layer 23 as a polishing stopper to temporarily achieve the flattening.

Subsequently, as shown in FIG. 2C, a second polishing is performed, and a CMP is performed with an enhanced mechanical polishing action. In the concave portion, the second easy-polishing layer 32 is polished, and the first polishing stopper layer 21 in the convex portion of the substrate and the second polishing layer 32 in the concave portion of the substrate are polished.
The second polishing can be stopped by using the polishing stopper layer 22 as a polishing stopper. As a result, a semiconductor device in which the interlayer insulating film is flattened as shown in FIG. 2C can be reliably manufactured.

Thereafter, as usual, the semiconductor device is manufactured through processes such as contact formation, contact embedding, and formation of a wiring layer. Although FIG. 2 shows that the element is polished to a position directly above the element, the substrate is an interlayer insulating film covering the element, and the planarization method of the present invention is applied to the interlayer insulating film having the irregularities. May be flattened.

As described above, in the second embodiment, since the interlayer insulating film is flattened, it is advantageous in terms of the depth of focus of photolithography, and fine wiring can be processed. In addition, step coverage deteriorates at the step,
It is possible to prevent the yield from decreasing and the resistance of the wiring layer from increasing.

In the above example, the target of planarization is a semiconductor device. However, the planarization method of the present invention
The present invention is not limited to this, and various changes can be made without departing from the scope of the present invention.

[0032]

According to the flattening method of the present invention, it is possible to reliably achieve flattening of a substrate having a concave portion having a small area and a concave portion having a large area.

[Brief description of the drawings]

FIG. 1 shows an embodiment in which the planarization method of the present invention is applied to a trench element isolation method of a semiconductor device, and (a) to (f).
Is a cross-sectional view showing the step.

FIGS. 2A to 2C are cross-sectional views illustrating a process in which the planarization method of the present invention is applied to an interlayer insulating film of a semiconductor device. FIGS.

FIG. 3 is a cross-sectional view illustrating a problem of the conventional polishing.

[Explanation of symbols]

10: substrate (substrate), 21: first polishing stop layer, 22:
Second polishing stop layer, 23: third polishing stop layer, 31: first easy polishing layer, 32: second easy polishing layer

Claims (5)

[Claims] A first polishing stopper layer formed on at least a convex portion of a substrate having a concave portion and a convex portion; and a first easy-polishing layer having a higher polishing rate than the first polishing stopper layer. Forming a second polishing stop layer having a lower polishing rate than the first easy-polishing layer on the first easy-polishing layer; and forming the second polishing stop layer on the first easy-polishing layer. Forming a second easy-polishing layer having a higher polishing rate than the second polishing stop layer on the stop layer; and forming a third polishing rate lower than the second easy-polishing layer on the second easy-polishing layer. A third polishing stopper layer existing in the concave portion of the substrate and a second polishing stopper layer existing in the convex portion of the substrate. A first polishing step of polishing the layer, and after the first polishing step, a second polishing stop layer present in the concave portion of the substrate and a convex portion of the substrate. 1 above until reaching a polishing stop layer of the third polishing stop layer and the second free-abrasive layer second
And a second polishing step of polishing the polishing stop layer. 2. The height of the projection of the substrate from the concave portion of the substrate on the upper surface of the first polishing stopper layer is substantially equal to the height of the upper surface of the second polishing stopper layer from the concave portion of the substrate in the concave portion of the substrate.
2. The planarizing method according to claim 1, wherein the height of the upper surface of the second polishing stopper layer at the convex portion of the substrate from the concave portion of the substrate is substantially equal to the height of the upper surface of the third polishing stopper layer at the concave portion of the substrate. . 3. The semiconductor device according to claim 1, wherein the concave portion of the base forms an element isolation region of the semiconductor substrate, the convex portion of the base is a surface of the semiconductor substrate, and the first polishing layer is an insulating layer filling the concave portion. 2. The flattening method according to 1. 4. The flattening method according to claim 1, wherein the convex portion of the base is an element constituting a semiconductor device, and the concave portion of the base is a surface of the semiconductor substrate. 5. The first polished layer has a low chemical polishing property, the second polished layer has a high chemical polishing property, and the first polishing step has a high chemical polishing property. 2. The method according to claim 1, wherein the polishing step has low chemical polishing properties.