JPH1069368A - Graphics controller circuit, and method for executing command on computer system and graphics controller chip - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a graphics system which is improved in a performance by solving a bus bottleneck. SOLUTION: The graphics controller circuit is provided which minimizes an amount of data received from a host. This graphics controller circuit is equipped with a register file 350 including registers. The graphics controller receives a command addressed to a virtual register and generates instructions including an instruction for accessing one of the registers in the register file. The command uses the number of virtual registers like this and several instructions are generated in response to it, so that this graphics controller circuit minimizes the amount of data that the host sends through a system bus.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates generally to computer graphics systems. Specifically, the present invention relates to a method and apparatus for executing a command in a graphics controller chip.

[0002]

2. Description of the Related Art Graphics controllers are designed to display video images on a display system by receiving commands and display data from a host system and generating display signals from those display data and commands. FIG. 1 shows such a graphics controller 120 and a host 110.
FIG. 1 is a block diagram of a computer system 100 having a display unit 130 and a display unit 130.

The graphics controller 120 receives commands and display data from the host 110 via the system bus 112, and executes the commands in the process of generating a display signal on the display bus 123, thereby forming the display data. The video image can be displayed on the display unit 130.
Graphics controller 120 may generate additional display data while executing commands received from host 110. The display data includes, for example, text data, graphics / video data in RGB format, and the like.

[0004] The graphics controller 120 may store the display data in the display memory 140 before generating the corresponding display signal on the display bus 123. Each element of the display data stored in the display memory 140 may correspond to one pixel on the display unit. In the following description, such a data element will be referred to as a “pixel datum”, and an aggregate of such pixels will be referred to as “pixel data”.

[0005] Commands received from the host 110 can specify various operations, such as, for example, a mobile display block operation. The moving display block operation means that a certain display block (hereinafter, referred to as a “source display block”) is moved from the area of the display memory 140 to another area (the destination display) on the display memory 140 by the graphics controller 120. Block). In some cases,
The source display block may be located in the host 110. In such a case, the host 110 can send the display data of the source display block via the system bus 112. In response, graphics controller 120 stores the pixel data of the source display block in display memory 140.
Can be moved to a memory location corresponding to the destination display block.

[0006] The host 110 can send several commands to the graphics controller 120 to perform each operation. For example, to perform a mobile display block operation, the host 110
Sends a command specifying the X / Y coordinates of the start position of the source display block, and specifies the X range of the source display block (ie, the length of the display block in the X-axis direction with respect to the start address) and the Y range. After sending this command, another command specifying the X / Y coordinates of the start address of the destination display block can be sent. Host 11
0 can finally send yet another command specifying the start of moving display data to the memory location in display memory 140 corresponding to the destination display block.

A graphics-only application (usually a “graphics user interface (GU)
With the advent of I) "), computer system 100 may need to perform some graphics operations in a short amount of time. For example, a mouse click by a computer user
The computer system 100 may be required to perform some graphics operations. Each operation requires the execution of several commands,
The host 110 may send a correspondingly larger number of commands to the graphics controller 120 via the system bus 112.

[0008]

Problems associated with the prior art computer system 100 include, for example,
The system bus 112 may not have enough bandwidth to support the transfer of such a large number of commands and display data, which may be a performance bottleneck for the computer system 100. Such a performance bottleneck causes a decrease in the performance throughput of the computer system 100.

The performance bottleneck in the system bus 112 is exacerbated when the host 110 and the graphics controller 120 operate faster and with wider bandwidth than the system bus 112. For example, a host 110 with a Pentium ™ processor may operate at a clock speed of 75 MHz and a 64-bit internal bus, and the graphics controller 120 may operate at a clock speed of 62.5 MHz and a 64-bit internal bus. In contrast, a system bus 112 such as a PCI bus
May operate on a 33 MHz clock speed and a 32 bit wide bus. G dedicated to graphics operations
When such a difference in clock rate and bus width is found in the UI application, it is caused by the system bus 1
12 causes a data throughput bottleneck, which causes the performance of the computer system 100 to decrease.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a graphics system having improved performance by eliminating a bus bottleneck.

[0011]

SUMMARY OF THE INVENTION A graphics controller circuit for use in a computer system having a bus and a host according to the present invention, wherein the host is coupled to the bus, transmits a command from the host on the bus. A host interface for receiving and generating a plurality of instructions from the command, and an execution circuit for executing the plurality of instructions to execute the command are provided, thereby achieving the above object.

In one embodiment, the graphics controller circuit further comprises a register file including a plurality of registers, wherein the command accesses the first register in the register file. The host interface generates a first instruction set, and if the command accesses a second register, the host interface generates a second instruction set and is included in the first instruction set. The number of instructions is different from the number of instructions included in the second instruction set, and the first instruction set includes accessing the first register.

In one embodiment, the second register includes a virtual register, and the second set of instructions includes at least one instruction for accessing the first register.

In one embodiment, the host interface examines data on the system bus and determines whether the command is addressed to the first register or to the second register. Determining a command encoder coupled to the system bus, wherein if the command is addressed to the first register, generating the first instruction set; A command encoder that generates the second instruction set, stores the instruction generated by the command encoder, and provides the instruction to the execution block, and a FIFO queue that generates the second instruction set. It has.

[0015] In one embodiment, the command is included in a plurality of commands for manipulating a moving display block, and the host comprises: host data;
The plurality of commands for operating the mobile display block via the host bus.

In one embodiment, the command encoder stores the host data, a set of instructions corresponding to the plurality of commands, and the FIFO queue including a plurality of entries, and the command encoder stores the plurality of entries in the FIFO queue. A tag bit is generated that indicates whether the data stored in each of the entries contains a host datum or an instruction.

In one embodiment, the tag bit of each of the plurality of entries is examined, and if the tag bit is
Sending the data contained in the entry to the execution block if the data contained in the corresponding one of the plurality of entries includes host data;
An O output control circuit is further provided.

A computer system according to the present invention comprises: a host for sending a set of commands and pixel data via a bus; a display unit; a display memory for storing a set of pixel data corresponding to a display image on the display unit; A graphics controller circuit for supplying the set of pixel data to the display memory, a host interface receiving the set of commands and the pixel data on the bus from the host, wherein the host interface receives the set of pixels and the pixel data from each of the set of commands; A host interface for generating a plurality of instructions; and a graphics controller circuit including an execution circuit for executing the plurality of instructions to store the pixel data in the display memory. Cage, said object is achieved.

In one embodiment, the computer system wherein the graphics controller circuit further comprises a register file including a plurality of registers, wherein the command accesses a first register in the register file. The host interface generates a first instruction set, and if the command accesses a second register, the host interface generates a second instruction set; The number of instructions included in the instruction set is different from the number of instructions included in the second instruction set, and the first instruction set includes accessing the first register.

In one embodiment, the second register includes a virtual register, and the second set of instructions includes at least one instruction for accessing the first register.

In one embodiment, the host interface examines data on the system bus and determines whether the command is addressed to the first register or to the second register. Determining a command encoder coupled to the system bus, wherein if the command is addressed to the first register, generating the first instruction set; A command encoder that generates the second instruction set, stores the instruction generated by the command encoder, and provides the instruction to the execution block, and a FIFO queue that generates the second instruction set. It has.

In one embodiment, the set of commands includes the command, and the set of commands is:
Designed to perform mobile display block operations.

[0023] In one embodiment, the command encoder stores the host data and a set of instructions corresponding to the set of commands in the FIFO queue including a plurality of entries, and the command encoder stores the set of instructions in the plurality of entries. Generate a tag bit that indicates whether the data stored in each of these contains pixel datums or instructions.

In one embodiment, the tag bit of each of the plurality of entries is examined, and if the tag bit is
Sending the data contained in the entry to the execution block if the data contained in the corresponding one of the plurality of entries includes a pixel datum;
An O output control circuit is further provided.

A graphics controller circuit according to the present invention comprises: a physical register that stores parameters for a graphics operation, addressable as a memory location, a first command to access the physical register, and a virtual register. And generating a first instruction set in response to the first command and generating a second instruction set in response to the second command.
An encoder, wherein the first instruction set and the second instruction set are both
An encoder comprising instructions for accessing the physical register, wherein the second instruction set comprises the first instruction set; and an encoder comprising the first instruction set and the second instruction set.
And an FIFO output control circuit coupled to the physical register, the control signal accessing the physical register in response to the instruction accessing the physical register. And a FIFO output control circuit for generating the above, thereby achieving the above object.

A method for executing a command in a graphics controller chip according to the present invention includes the steps of receiving the command, generating a plurality of instructions from the command, storing the plurality of instructions in a command queue, Executing the plurality of instructions in the command queue, thereby achieving the above object.

[0027] In one embodiment, the method further comprises examining the command to determine whether the command accesses a physical register or a virtual register, if the command accesses the physical register or the virtual register. If accessing a physical register, the step of generating a plurality of instructions generates a first set of instructions, and if the command accesses the virtual register, a second set of instructions. , The first instruction set and the second instruction set both include instructions for accessing the physical register, and wherein the second instruction set comprises the first instruction set. Include set .

The operation will be described below.

The graphics controller circuit of the present invention includes a host interface capable of receiving a command from a host and generating a plurality of instructions from the command. The execution circuit executes a plurality of instructions to actually execute the command received from the host.

This graphics controller circuit
Further, a register file including a plurality of registers may be provided. The host interface generates a first set of instructions if the command accesses a first register in the register file, and generates a second set of instructions if the command accesses a second register. be able to. The first set of instructions may include accessing a first register. The second register according to the invention can be a virtual register. The second set of instructions may include instructions that direct access to the first register.

By providing such commands issued to virtual registers and generating a large number of instructions, including commands that command access to registers in the register file, the graphics controller according to the present invention provides for certain registers in the graphics controller. Can be combined with several other commands into a single command on the system bus. Since several commands can be combined into a single command on the system bus, the amount of data transferred on the system bus can be minimized.

The host interface according to the present invention includes a command encoder that examines data on the bus and determines whether the command is addressed to the first register or the second register. Is also good. The command encoder generates a first set of instructions if the command is addressed to a first register, and a second set of instructions if the command is addressed to a second register. Instructions can be generated.

The host interface may also include a FIFO queue that stores instructions generated by the command encoder and provides those instructions to the execution block. When the host interface generates a large number of instructions from each command, the instruction path for the graphics controller and the path for data supplied to the host can operate with a narrower bus width, so that the Space can be saved. The graphics controller can thus execute more instructions, even if it operates faster than the system bus.

According to the present invention, a plurality of commands for performing a moving display block operation may include data supplied to the host. The host can send host data and multiple commands for manipulating the mobile display block via the host bus. The command encoder can store host data and a set of instructions corresponding to a plurality of commands in a FIFO queue including a plurality of entries. The command encoder can generate a tag bit that indicates whether the data stored in each entry includes a host datum or an instruction.

FI in the graphics controller circuit
The FO output control circuit examines the tag bit of each entry, and if the tag bit indicates that the data contained in the corresponding entry contains instructions, the data contained in that entry is included. To the execution block, and if the tag bit indicates that the data contained in the corresponding entry contains host data, send the data contained in that entry to the pixel processing block. .

[0036]

DETAILED DESCRIPTION OF THE INVENTION This application claims priority from Provisional Application No. 60 / 000,490, filed June 23, 1995, entitled "Byte Enable FIFO Architecture."

The graphics controller 120 according to the present invention is designed to reduce the number of commands received via the system bus 112 as shown in FIGS. 4A to 4D. ing. In FIG.
As shown in (a), when performing a graphics operation, the host 110 according to the prior art is
Send two commands. That is, a first command (410) for setting the register A, a second command (420) for setting the register B, and a third command (4
30).

In the present invention, the host 110 need only send two commands to perform an equivalent graphics operation. That is, a command (411) for instructing the setting of the register A and a command (412) for instructing the setting of the register B and instructing the start of execution using A and B. Therefore, according to the present invention, two commands according to the related art can be combined into one command. 4B to 4D are also described in the same manner as FIG. 4A. That is, in each of the figures, two commands are combined into one command in the related art.

For example, in the prior art, graphics controller 120 may receive four commands from host 110 to perform a moving display block operation. That is, the first command specifies the address of the source display block, the second command specifies the address of the destination display block, and the third command specifies the X and Y ranges of the source display block. However, the fourth command may instruct the graphics controller 120 to start execution using parameters that can be set in the first three commands. In response to the fourth command, the graphics controller 12
0 (specified by the first and third commands)
The pixel data of the source display block is stored in the display memory 140 corresponding to the destination display block (specified by the second command).
May be moved to a memory location within

On the other hand, according to the present invention, the graphics controller 120 only needs to receive three commands from the host 110 when performing a moving display block operation. The first and second commands specify the addresses of a source block and a destination block, as in the prior art. But,
The third command not only specifies either the X range or the Y range or both, but also causes the graphics controller 120 of the present invention to start moving the pixel data of the source display block. In the graphics controller 120 of the present invention, since the number of commands received to perform the mobile display block operation is reduced, the amount of data that the host 110 sends on the system bus 112 can also be reduced. In addition, since virtual register space is used, no additional physical registers are needed in such virtual register space, further saving silicon space.

Graphics controller 120 can achieve such a reduction in the amount of data transferred by having the registers store the X and Y ranges. Graphics controller 120 may receive one type of command directing that the X and Y ranges be stored in these registers and another type of command issued to a virtual register. In response to such a command destined for a virtual register, the host interface 210 (shown in FIG. 2) may not only store the X and Y ranges in the register, but also other instructions. It can also be generated. In the example described above, in response to a command instructing access to the virtual register, the host interface 120 instructs to store the X and Y ranges in the corresponding register, and instructs to start moving the pixel data of the source display block. Many instructions can be generated.
Therefore, in the present invention, the third and fourth commands according to the related art can be combined into one command on the system bus 112 by using the virtual register.

According to the present invention, since a large number of commands used in the prior art can be combined into one command, the amount of data on the system bus 112 can be reduced. Although the invention is described herein as applying to a mobile display block operation, it should be understood that performing other types of operations is within the scope and spirit of the invention.

FIG. 2 shows a host interface 210,
FIG. 4 is a block diagram of a graphics controller 120 according to the present invention having an execution block 220 and a pixel processing block 230. The host interface 210 can receive commands and host data from the host 110 via the system bus 112 and generate a number of instructions corresponding to each command. By generating such a large number of instructions corresponding to each command, the graphics controller 120 can reduce the amount of data transferred from the host 110 to the graphics controller 120. The host interface 210 can receive commands at one clock rate (ie, the clock rate of the system bus 112) and generate instructions at another rate (ie, the internal clock rate of the graphics controller 120).

The execution block 220 performs an operation specified by a command from the host 110 by executing the instruction generated by the host interface 210. The instructions executed by the execution block 220 include the pixel data of the source display block with the display memory 140.
Various operations are included, such as an operation to move to a memory location corresponding to a destination display block within. The host 110 is connected to the system bus 11
2, the host 110 can specify the memory location in the display memory 140 where the pixel data of the source display block exists. The execution block 220 receives the pixel data from the host 110 or the display memory 140 from the control bus 1.
14 to control movement.

The pixel processing block 230 generates additional pixel data by processing the pixel data. Such processing may include performing a raster operation well known in the art. The pixel processing block 230 converts the pixel data generated by such processing into
It can be stored at the memory location specified by execution block 220.

FIG. 3 is a detailed block diagram of host interface 210 according to the present invention, including address register 333, data register 336, command encoder 330, and command / data FIFO 340. The encoder 330 of the present invention generates a number of instructions from each of the received commands,
Command / data FIF
O 340.

FIG. 3 further shows a FIFO output control circuit 3.
60, execution engine 370, and register file 35
FIG. 3 includes a detailed block diagram of an execution block 220 according to the present invention, including zeros. FIFO output control circuit 360
Can control when data is stored in register file 350. FIFO output control circuit 36
0 may also determine when execution of various operations is to begin and control the operation of execution engine 370 via bus 366. The FIFO output control circuit 360
Each of these operations is performed based on command / tag information received on buses 213 and 214 of the command / data FIFO bus 212.

The register file 350 may include a plurality of registers, each storing a value corresponding to a predetermined parameter. For example, registers 0 and 1 can store the X and Y coordinates of the start address of each of the source and destination display blocks for moving display block operation, respectively. Register 2 can store the X and Y ranges of the source display block.
In the present specification, the registers included in the register file 350 are also called “physical registers”.

In the preferred embodiment, each register in register file 350 can store 32 bits. In that case, the X and Y ranges and the X and Y coordinates are each stored in 16 bits. Register file 350 can be addressed as a memory-mapped register set (ie,
(Each register has a predetermined memory address). In the preferred embodiment, register file 350 contains eight registers.

Thus, a command, such as a command specifying the start address of the source and destination display blocks, involves writing data to the corresponding registers in register file 350. The system bus 112 has a 32-bit PCI
A bus may be included. Therefore, the host 110
To send a command, 32 bits of address information can be sent during one clock cycle (of the system bus 112) and the corresponding 32 bits of data can be sent during the following one clock cycle.

For example, the host 110 sends the 32-bit memory address of the register 0 during one clock cycle to set the start address of the source display block, and transmits the corresponding data during the following one clock cycle. Can be sent. The 32-bit data may include 16 bits corresponding to each of the X and Y coordinates of the start address. Similarly, host 110 can send the address of register 2 and the corresponding data to set the X and Y ranges of the source display block for the move operation.

The host 110 can also send a memory address of the virtual register number (eg, 8 when the register file 350 contains eight registers numbered 0-7). In response to receiving such a virtual register number, the graphics controller 120 according to the present invention generates an instruction and stores the data received in the next clock cycle in any of the predetermined registers 0-7; Pixel data,
It can be moved to a memory location in the display memory 140 corresponding to the destination display block.

By using such virtual register addressing and generating instructions for instructing storage and movement, the graphics controller 120
There is no need to add a command to command the start of pixel data movement. As a result, the amount of command data transferred via the system bus 112 can be reduced. The graphics controller 120 according to the prior art
It will be appreciated that such an additional command is required to initiate the transfer of the pixel data to the memory address of the destination display block. It will also be appreciated that different instructions may be generated in response to such virtual register addressing without departing from the scope and spirit of the present invention.

Still referring to FIG. 3, address register 333 and data register 336 can respectively store address and data information received over system bus 112 during each bus cycle. The address from the host 110 may include the memory-mapped address of a register in the register file 350, or may include the address of a virtual register.

The command encoder 330 can generate a corresponding instruction by examining the address stored in the address register 333. For example, if the address corresponds to register 0, command encoder 330 can generate two instructions. The first instruction is 3 (stored in data register 336).
The Y coordinate occupying 16 bits of the 2-bit data can be stored in register 0, and the second instruction can store the X coordinate occupying the remaining 16 bits in register 0.

If the address stored in address register 333 corresponds to a virtual register, the command register can generate additional instructions other than the stored instructions. For example, in a preferred embodiment, the graphics controller 120
Host 1 while performing mobile display block operation
The three virtual registers (range, execute, X register, range, execute, Y register and range,
Execution / XY register).

The operation of writing to the range / execution / X virtual register (register number 8) indicates that only the X range needs to be changed. Start immediately with. In response to such a range / execution / X write operation, the command encoder 330 generates an instruction to change the X range and another command to start the operation of moving the display data to the address specified by the register 1. Generate instructions. Similarly, the command encoder 330 can generate two instructions corresponding to a range, execute, and write operation to the Y register.

The command encoder 330 can generate three instructions corresponding to the write command to the range / execution / XY virtual register (register number 10). The first instruction is 32
The 16-bit X component of the bit data is written, and the second instruction causes the remaining 16-bit Y component of the 32-bit data to be written. The third instruction may be a movement instruction for instructing the start of movement of the pixel data of the source display block to the destination display block.

Each of the instructions generated by command encoder 330 can include 32 bits. The 16 bits are used for any one of the X range, the Y range, the X coordinate, and the Y coordinate. The remaining 16 bits can specify an instruction code that can indicate the type of instruction (eg, storage in register 1, start of display data move operation, etc.). Command encoder 330 can send such 32-bit instructions via instruction / data bus 334.

Command encoder 330 also sends a tag bit on signal line 343 to determine whether the information sent on instruction / data bus 334 corresponds to an instruction or to a host datum. Can be shown. The command encoder 330 can send a logical value 0 as a tag bit while sending instructions via the instruction / data bus 334, and send a logical value 1 while sending host datum.

Such host data is received from the host 110 via the system bus 112 and corresponds to the pixel data of the source display block. Register 0 may have a value indicating that the pixel data of the source display block is provided by host 110. In such a case, the host 110 can send the pixel data of the source display block for the moving display block operation.

Command / data FIFO 340 stores each instruction or host datum received over instruction / data bus 334 and stores the corresponding tag bit received over signal line 343. it can. Command / data FIFO 340 may include 32 entries in the preferred embodiment. Here, each entry includes 33 bits. That is, each entry can store a 32-bit instruction or host datum and a corresponding 1-tag bit. Each tag bit in the command / data FIFO 340 (tag bit field 34
6) can indicate whether the corresponding 32 bits represent an instruction or a host datum.

If the 33 bits in the command / data FIFO 340 entry represent an instruction, the instruction code field 347 can store 16 bits corresponding to the instruction code. The data field 348 can store the remaining 16 bits corresponding to the data part of the instruction. If the 33 bits in the command / data FIFO 340 entry represent host data, the command / data FIFO 340 can use the data fields 347 and 348 to store 32 bits of host data in the entry. If host data is provided, the data is processed by pixel processing block 230 via bus 212 as indicated by the tag bits on bus 213.

By generating multiple instructions from a single command, a command /
It should be understood that the data FIFO 340 can operate effectively with a narrower data width (33 bits) than the system bus 212. If such a large number of instructions are not generated, the command / data FIFO becomes 64 bytes.
It must operate with a data width of bits. The graphics controller 120 is connected to the system bus 112
Since the graphics controller 120 can operate at a higher clock rate,
More instructions can be executed. For example, a system bus 112 such as a PCI bus
Operating at z, graphics controller 120 can operate at 62.5 MHz.

Still referring to FIG. 3, FIFO output control circuit 360 extracts 33-bit data in each entry of command / data FIFO 340 and checks tag bit 346, whereby the extracted data corresponds to the instruction. Or whether it corresponds to the host data. If the 33-bit entry represents an instruction, FIFO output control circuit 360 checks the instruction code (stored in field 347) so that the instruction stores the data in a register in register file 350. It is determined whether the instruction instructs the user to perform the instruction. If so, FIFO output control circuit 360 stores the 16 bits in data field 348 in the register indicated by the instruction code by generating assert signal 365.

If the 33-bit entry represents an execution instruction, the FIFO output control circuit 360
Can begin execution via the execution engine 370 on the control bus 366. Execution engine 370 processes the host data properly by generating control signals to pixel processing block 230. For example, the host data may correspond to pixel data of a preceding moving display block command. In that case, execution engine 3
70 can store pixel data at a memory location indicated by a register in register file 350. The graphics controller 120 can generate a display signal from the pixel data stored in the display memory 140 to the display unit 130.

Thus, the host interface 210 according to the present invention can generate a large number of instructions from each command received from the host 110. Thus, the amount of data sent from the host 110 to the graphics controller 120 can be reduced. By generating such a large number of instructions, the graphics controller 120
It can operate effectively with a narrow bus width.

In the above description, the present invention is applied to the operation of moving the display block, but other types of operations can be performed without departing from the scope and spirit of the present invention. For example, multiple instructions can be generated during a read access to a register. Such a register may be a virtual register as described above, or may be a physical register (for example, one of registers 0 to 7 in the register file 350). Good). Read and write commands are collectively referred to herein as “access commands”.

It will be readily apparent to one skilled in the art that the present invention can achieve all of the objects set forth above. After reading the above detailed description, it will be apparent to those skilled in the art that various modifications, substitutions, and / or equivalent arrangements may be made to the invention disclosed broadly herein. Various aspects could be implemented. Thus, the scope of protection to be provided by the present invention is intended to be limited only by the definitions contained in the appended claims and equivalents thereof.

[0070]

According to the present invention, it is possible to provide a graphics system having improved performance by eliminating a bus bottleneck.

[Brief description of the drawings]

FIG. 1 is a block diagram of a computer system including a graphics controller, a host, a display memory, and a display unit.

FIG. 2 is a block diagram of a graphics controller according to the present invention including a host interface, an execution block, and a pixel processing block.

FIG. 3 is a block diagram showing a more detailed architecture of a host interface and an execution block according to the present invention.

FIG. 4 illustrates the difference between the prior art and the present invention in the number of commands used to perform graphics operations.

[Explanation of symbols]

 112 system bus 114 control bus 210 host interface 212 command / data FIFO bus 213, 214, 215 bus 220 execution block 230 pixel processing block 330 command encoder 333 address register 334 instruction / data bus 334 336 data register 340 command / data FIFO 343 signal Line 346 tag bit field 347 instruction code field 348 data field 350 register file 360 FIFO output control circuit 365 assert signal 366 control bus 370 execution engine

 ────────────────────────────────────────────────── ─── Continuation of front page (71) Applicant 595158337 3100 West Warren Avenue, Fremont, California 94538, U.S.A. S. A. (72) Inventor Richard Charles Henry Owen United States of America Washington 98106, Seattle, 39TH Avenue South 3810 (72) Inventor Mark Emil Bonnerick United States of America Washington 98105, Seattle, 41 Estee Avenue NE 4625

Claims (17)

[Claims] 1. A graphics controller circuit for use in a computer system having a bus and a host, the host being coupled to the bus, wherein the graphics controller circuit receives a command from the host on the bus, and receives a command from the command. A graphics controller circuit comprising: a host interface that generates a plurality of instructions; and an execution circuit that executes the plurality of instructions to execute the command. 2. The graphics controller circuit further comprising a register file including a plurality of registers, wherein the host interface is provided if the command accesses a first register in the register file. Generating a first instruction set; if the command accesses a second register, the host interface generates a second instruction set; and a number of instructions included in the first instruction set. 2. The graphics of claim 1, wherein the number of instructions is different from the number of instructions included in the second set of instructions, and wherein the first set of instructions includes accessing the first register. Controller circuit. 3. The method of claim 2, wherein the second register comprises a virtual register, and wherein the second set of instructions comprises at least one instruction accessing the first register. Graphics controller circuit. 4. The host interface examines data on the system bus to determine whether the command is addressed to the first register or the second register. A command encoder coupled to the system bus, the command encoder generating the first instruction set if the command is addressed to the first register, wherein the command is stored in the second register; If addressing, a command encoder for generating the second instruction set; and a FIFO queue for storing the instruction generated by the command encoder and providing the instruction to the execution block. 4. The graph according to claim 3, wherein Tsu box controller circuit. 5. The method according to claim 5, wherein the command is included in a plurality of commands for operating a moving display block.
5. The graphics controller circuit according to claim 4, wherein said host sends host data and said plurality of commands for operating said mobile display block via said host bus. 6. The FIFO including the host data, a set of instructions corresponding to the plurality of commands, and a plurality of entries.
6. The method of claim 5, wherein the command encoder generates a tag bit indicating whether the data stored in each of the plurality of entries includes a host datum or an instruction. Graphics controller circuit as described. 7. Examining the tag bits of each of the plurality of entries, if the tag bits indicate that data contained in a corresponding one of the plurality of entries includes host data, 7. The graphics controller circuit according to claim 6, further comprising a FIFO output control circuit that sends data included in an entry to the execution block. 8. A host for transmitting a set of commands and pixel data via a bus, a display unit, a display memory for storing a set of pixel data corresponding to a display image on the display unit, and a set of pixel data. A graphics controller circuit that supplies the set of commands and the pixel data on the bus from the host, the plurality of instructions being generated from each of the set of commands. And a graphics controller circuit including a host interface and an execution circuit for executing the plurality of instructions to store the pixel data in the display memory. 9. The computer system, wherein the graphics controller circuit further comprises a register file including a plurality of registers, if the command accesses a first register in the register file. The host interface generates a first instruction set, and if the command accesses a second register, the host interface generates a second instruction set; 9. The method of claim 8, wherein the number of instructions included is different from the number of instructions included in the second instruction set, and wherein the first instruction set includes accessing the first register. Computer system described Tem. 10. The method of claim 9, wherein the second register comprises a virtual register, and wherein the second set of instructions comprises at least one instruction for accessing the first register. Computer system. 11. The host interface examines data on the system bus to determine whether the command is addressed to the first register or to the second register. A command encoder coupled to the system bus, the command encoder generating the first instruction set if the command is addressed to the first register, wherein the command is stored in the second register; If addressing, a command encoder for generating the second instruction set; and a FIFO queue for storing the instruction generated by the command encoder and providing the instruction to the execution block. The method according to claim 10, wherein Computer system. 12. The set of commands comprising the commands, wherein the set of commands is designed to perform a moving display block operation.
2. The computer system according to claim 1. 13. The FEC including a plurality of entries, wherein the command encoder stores a set of instructions corresponding to the set of host data and the command.
13. The command encoder stored in an IFO queue, wherein the command encoder generates a tag bit indicating whether the data stored in each of the plurality of entries includes a pixel datum or an instruction. A computer system according to claim 1. 14. Examining the tag bit of each of the plurality of entries, if the tag bit indicates that the data contained in a corresponding one of the plurality of entries includes a pixel datum. 14. The computer system according to claim 13, further comprising a FIFO output control circuit that sends data included in an entry to the execution block. 15. Stored parameters for a graphics operation, addressable as a memory location,
Receiving a physical register, a first command to access the physical register, and a second command to access the virtual register, generating a first instruction set in response to the first command; An encoder for generating a second instruction set in response to the second command, wherein the first instruction set and the second instruction set both include an instruction for accessing the physical register. An encoder, wherein the second instruction set includes the first instruction set, an FIFO for storing the first instruction set and the second instruction set, and a physical register and the FIFO coupled to the physical register and the FIFO. FIFO
A graphics controller circuit, comprising: an output control circuit, wherein the FIFO output control circuit generates a control signal for accessing the physical register in response to the instruction for accessing the physical register. 16. A method for executing a command on a graphics controller chip, the method comprising: receiving the command; generating a plurality of instructions from the command; storing the plurality of instructions in a command queue. Executing the plurality of instructions in the command queue. 17. The method of claim 17, further comprising examining the command to determine whether the command accesses a physical register or a virtual register, if the command accesses the physical register. Generating a plurality of instructions if generating the first instruction set, and generating a second instruction set if the command accesses the virtual register. The first instruction set and the second instruction set both include an instruction that accesses the physical register; and the second instruction set includes the first instruction set. Claim 16 The method described in.