JPH1065757A - Start-stop synchronous communication equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the load of CPU concerning communication error processing and the burden of a user with several settings and to remarkably reduce time for resending in generating a communication error. SOLUTION: UART 13A is provided with an input/output control circuit 137 switching the input of communication data DS and the output of communication error information EI in response to the supply of a reception finishing signal RE and an error information transmission shift register 136 transmitting communication error information EI to the circuit 137 by synchronizing with a reception clock CKR, and UART 23A is provided with an input/output control circuit 237 switching the output of communication data DS and the input of communication error information EI in response to the supply of a transmission finishing signal TE and an error information receiving shift register 136 retransmission request signal RT to the register 236 by synchronizing with a transmission clock CKT.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an asynchronous communication device, and more particularly to an asynchronous communication device used for communication between microcomputers.

[0002]

2. Description of the Related Art Asynchronous communication (Universal)
Asynchronous Receiver / Tra
The nsmitter (hereinafter, UART) system is one of serial communication systems, is widely used in a communication system between microcomputers, and it has become important to reliably transfer a large amount of data at high speed. For this reason, when a communication error such as data loss (hereinafter, framing error) or conversion (hereinafter, parity error) occurs, it is important to reliably detect and appropriately process the error.

Conventionally, in such a communication error processing in serial communication between microcomputers, when a communication error is detected on the receiving side, a communication error detection signal is generated in an interrupt controller (hereinafter referred to as INTC), and the receiving side receives the communication error signal from the INTC. Requests communication error processing from a central processing unit (hereinafter, CPU). The CPU transmits the communication error occurrence information to the transmission side via a general-purpose port or the like for communication error processing. On the transmission side, upon receiving the communication error occurrence information, the transmission side CPU performs a communication error process such as retransmission of communication data by a preset program.

FIG. 7 is a block diagram showing a conventional communication system between microcomputers including a conventional asynchronous communication device (UART). Referring to FIG. 7, the conventional communication system between microcomputers includes a microcomputer on a receiving side and a microcomputer on a transmitting side. Consists of 1 and 2.

The receiving microcomputer 1 has a CPU
11, an INTC 12, and a UART unit 13. These CPUs 11 and INTC 1
2, the UART unit 13, the reception data terminal T11, and the port P11.

The transmitting microcomputer 2 has a CPU
21, an INTC 22, and a UART unit 23. The CPU 21 and the INTC 2
2, a UART unit 23, a transmission data terminal T21, and a port P21.

Referring to FIG. 8A, which shows a block diagram of the configuration of the URT section 13 for the reception control function,
The unit 13 includes a reception shift register 132 that shifts and inputs communication data, a reception buffer 131 that temporarily stores data received from the reception shift register 132, and a reception that controls shift input of communication data and storage timing to the reception buffer. A timing control circuit 133, and a communication error detection circuit 134 for detecting a communication error of the received data.
And a communication error register 1 for storing communication error information.
35.

Referring to FIG. 8B, which shows the configuration of the URT unit 23 in terms of a transmission control function in a block diagram.
A transmission buffer 231 for holding transmission data to be written via the internal bus 25, and a transmission shift register 23 for fetching transmission data from the transmission buffer 231 and shifting and outputting the transmission data.
2 and a transmission timing control circuit 233 that controls shift output timing of communication data and transfer timing from the transmission buffer to the transmission shift register.

Next, the operation of the conventional start-stop synchronous communication apparatus will be described with reference to FIGS. 7 and 8A and 9B and FIG. 9 showing a time chart of data reception timing. In the URT unit 13 on the reception side, the reception shift register 132 inputs the serial data DS input from the reception data terminal T11 in synchronization with the reception clock CKR supplied from the reception timing control circuit 133, and outputs the serial data DS to the reception shift clock CSR. The data is converted into parallel data DP by shifting in synchronization. The reception shift register 132 generates a reception end signal RE when receiving communication data having a predetermined number of bits (hereinafter referred to as one communication data), and transmits the reception end to the reception timing control circuit 133. Reception timing control circuit 133 that has detected the end of reception
Allows data transfer to the reception buffer 131 by the reception control signal group RC, and the reception buffer 131 stores the data DP in synchronization with the reception clock CKR. The data DP stored in the reception buffer 131 is stored in the C via the internal bus 15.
It is read by PU11.

At the same time, the communication error detection circuit 134 generates a communication error detection signal EC when detecting a communication error, which is a communication error, from the data DS input from the reception data terminal T11.

The content of the communication error is, for example, when data is lost (hereinafter referred to as a framing error) or conversion (hereinafter referred to as a parity error) in the course of communication, or at the receiving side, the CPU 11 stores the data DP This is a case where the next data is stored before reading the data (hereinafter, overrun error). For the recognition of the framing error and the parity error, a communication protocol is determined in advance between the transmitting side and the receiving side, and the receiving side detects the error based on whether or not received data according to the protocol has been received.

In the communication protocol of the UART system, the state of the transmission data terminal when there is no communication data DS is "1".
At the start of transmission, 1 bit “0” (hereinafter, start bit ST) indicating the start of transmission, 8 bits of actual data (hereinafter, data bit groups 0 to 7), and 8 bits after the data bit group Is "1" when the number of "1" in the actual data is an even number, and "1" when the number is an odd number.
1-bit data (hereinafter, parity bit P) indicating "0", and 2-bit "1" (hereinafter, stop bit ST) indicating the end of communication are set.

For example, if the data bit group is "011010"
Assuming that the bits are 8 bits of “01”, the transmission side transmits “0” of the start bit ST and “011010”
01, the parity bit P is “1”, and the stop bit SP is “11”, that is, “00110010011”.
The transmission side transmits 12 bits of “1” as one communication data.The receiving side receives “011101001” as a data bit group, calculates the number of “1” in the received data, and calculates the calculated parity bit P “1”. Received parity bit P "
Receiving that 1 "matches and further receiving the subsequent two stop bits SP" 11 ", it recognizes that there is no communication error.

If a framing error occurs, for example, if the second bit of the data bit group is missing, the received data will be 11 bits of "00101001111". On the receiving side, 8 bits “01010011” following the start bit SP are received as a data bit group,
The next one bit is received as a parity bit P, and the remaining “1” is received as a stop bit SP. The framing error is detected because only one stop bit has been received, contrary to the protocol of two bits "1". If a parity error occurs, for example, if the third bit of the communication data is changed, the received data will be 12 bits of “001001001111”. On the receiving side, 8 bits following the start bit SP
01001001 "is received as a data bit group, and since the number of 1s in this data is an odd number," 0 "is expected as the parity bit P, but the received parity bit P is" 1 ".
Therefore, a parity error is detected.

The communication error detection circuit 134 detects an error occurring in communication in this way and generates a communication error detection signal EC. The communication error detection signal EC is
1 and stored in the communication error register 134 at the same time. The CPU 11 reads out the error information stored in the communication error register 134 via the internal bus 15.

Next, the transmitting side URT unit 23 first
The CPU 21 transmits the transmission buffer 23 via the internal bus 25.
Write the transmission data in 1. When the writing to the transmission buffer 231 is completed, the transmission timing control circuit 233 permits the data transfer from the transmission buffer 231 to the transmission shift register 232 by the transmission control signal group 151. The data transferred to the transmission shift register 232 is converted into serial data DS by being shifted in synchronization with the transmission shift clock CST supplied from the transmission timing control circuit 233, and is transmitted in synchronization with the transmission clock CKT. Output from T21. When transmission of one communication data is completed, a transmission end signal TE is generated, and the transmission end signal is transmitted to the transmission timing control circuit 233.

Referring to FIG. 9 again, here, data is received in synchronization with the reception clock CKR in accordance with the above-mentioned communication protocol, and a start bit ST, data bit groups 0 to 7, This shows a case where the bits are received with a parity bit P and a stop bit SP. When the reception of the stop bit SP is completed,
The reception end signal RE becomes active.

The data transmission timing is the same except that the reception clock CKR becomes the transmission clock CKT in FIG.

Next, referring to FIG. 10, which is a flowchart showing a UART communication process in a conventional microcomputer, a UART in a conventional microcomputer will be described.
In the following, a description will be given of a case where communication is performed using one data frame as 512 communication data for convenience of explanation.

First, on the transmitting side and the receiving side, various processing steps P11 and P2 for processing at the time of occurrence of a communication error.
1 is set. Next, the transmission of the UART unit 23 is permitted (step P22), and the reception side permits the reception of the UART unit 13 (step P12). Next, the transmission side writes data to the transmission buffer 231 (step P2).
3). When data is written to the transmission buffer 231,
The transmitting side executes transmission of one communication data (step P2
4) Yes. At this time, the receiving side determines the operation of receiving one communication data and a communication error (step P13). A transmission / reception operation of one communication data starts with a start bit, and includes data of a designated number of bits, a parity bit, and a stop bit.

Next, when one transmission / reception operation of communication data is completed, the UART section 13 on the receiving side determines whether there is a communication error or not.
The notification is sent to the NTC 12 (step P14). 1 on the sending side
Each time the transmission of communication data is completed, the transmission end determination processing for one data frame is performed, and the above-described transmission operation is performed until the transmission of one data frame is completed (steps P23 to P24).
Is repeated. Similarly, the receiving side performs the above-described receiving operation (step P13) until the reception of one data frame is completed. During reception, the INTC 12 on the receiving side sets the UART unit 1
3 receives a communication error from the communication error detection signal EC (step P14), and when a communication error is detected, requests the CPU 11 to perform a communication error interrupt process (step P15). In response to the communication error interrupt request, the CPU 11 performs a preset error detection process (step P11), that is, notifies a predetermined general-purpose port that a communication error has been detected (step P1).
6). Communication error detection information ECI via the transmitting-side general-purpose port P21 connected to the receiving-side general-purpose port P11
(Step P25) is transmitted to the INTC 22 on the transmission side (Step P26). The INTC 22 requests the CPU 21 to perform a retransmission interruption process. These processes (steps P14 to P16, P25 to P27) are performed by the UART 1
This is performed in parallel with the transmission and reception performed in 3 and 23. When the transmission of one data frame is completed, the transmission side determines whether there is a communication error with respect to this data frame. When a communication error is detected, that is, when a retransmission interrupt request has been transmitted to the CPU (step P27)
In step P28, one data frame in which a communication error is detected is retransmitted (step P28).

As described above, in the conventional UART, communication error processing requires software intervention through the intervention of the CPU, which is a burden on the CPU. In addition, it is difficult to cope with error processing such as retransmission for each communication data when an error occurs, and it is necessary to retransmit all one data frame, which is inefficient.

[0023]

In the above-mentioned conventional start-stop synchronous communication apparatus, the processing of the communication error requires the intervention of the CPU, so that the communication error processing imposes a heavy burden on the CPU, and the performance is greatly reduced. There was a disadvantage of becoming.

Also, it is difficult to cope with error processing such as retransmission for each communication data when an error occurs.
Since error processing is performed for each data frame, there is a disadvantage that error processing is inefficient.

Further, since the user has to set and execute the processing when a communication error occurs in advance by software, various settings of software processing for detecting and processing the communication error increase, and the burden on the user increases. There were drawbacks.

An object of the present invention is to reduce the load on the CPU by eliminating the intervention of the CPU in processing when a communication error is detected, and to improve the efficiency of processing when an error occurs by implementing error processing for each communication data. It is another object of the present invention to provide a start-stop synchronous communication device that can reduce various settings for software processing and reduce a burden on a user.

[0027]

According to a first aspect of the present invention, there is provided an asynchronous communication apparatus, wherein a reception control means shifts and inputs received serial communication data in synchronization with a reception clock to generate reception data; A reception buffer that temporarily stores the reception data supplied from a reception shift register, a reception timing control circuit that controls generation of the reception clock, shift input of the serial communication data, and storage timing of the reception data, A communication error detection circuit that detects a communication error of the received data and outputs communication error information; and a communication error register that stores the communication error information. The transmission data output from the buffer is fetched and shifted and output in synchronization with the transmission clock. A transmission shift register that outputs communication data, a transmission timing control circuit that controls generation of the transmission clock, shift output timing of the serial communication data, and transfer timing of the transmission data to the transmission shift register, In a start-stop synchronous communication device that performs start-stop synchronous serial communication between a first microcomputer including the reception control unit and a second microcomputer including the transmission control unit, the reception control unit may include a first microcomputer. A first input / output control circuit for switching between input of the serial communication data and output of the communication error information in response to the supply of the control signal, and receiving the communication error information output from the communication error detection circuit. An error information transmission shift register for transmitting the error information to the first input / output control circuit in synchronization with a clock. A second input / output control circuit that switches between output of the serial communication data and input of the communication error information in response to the supply of a second control signal; An error information reception shift register that takes in the communication error information input from the control circuit in synchronization with the transmission clock and transmits a retransmission request signal for requesting retransmission of the transmission data to the transmission timing circuit. ing.

[0028]

Next, the UART sections 13A and 23B on the receiving side and the transmitting side, which characterize the start-stop synchronous communication apparatus according to the embodiment of the present invention, are common to the components shown in FIG. Referring to FIGS. 1A and 1B, which are similarly indicated by blocks with reference characters / numerals, the UART section 13A of the present embodiment shown in FIG. In addition to the reception buffer 131, the reception timing control circuit 133, the communication error detection circuit 134, and the communication error register 134, the reception data terminal T
11 input / output control circuit 137 and communication error detection circuit 1
And an error information transmission shift register 136 which takes in the communication error detection signal EC from 34 and transmits it to the input / output control circuit 137 in synchronization with the reception clock CKR.

The input / output control circuit 137 inputs communication data from the reception data terminal T11 during reception of the reception end signal RE input from the reception shift register 132 as an input / output switching signal. Switching is performed so that the error information signal EI output from 136 is output to the reception data terminal T11.

Referring to FIG. 1B, the UART section 23A of the present embodiment shown in this figure includes a transmission buffer 231, a transmission shift register 232, and a transmission timing control circuit 233 which are common with those of the related art. , Transmission data terminal T
21, an input / output control circuit 137 and a transmission data terminal T21.
The error information signal EI input from the input / output control circuit 1
37, an error information reception shift register 236 for transmitting a retransmission request signal RT to the transmission timing control circuit 233 in synchronization with the transmission clock CKT via the transmission clock CKT 37.

The input / output control circuit 137 uses the transmission end signal TE output from the transmission shift register 232 as an input / output switching signal, outputs transmission data from the transmission shift register 232 to the transmission data terminal T21 during transmission, and transmits the data. Later, the error information E input from the transmission data terminal T21
Switching is performed so as to transfer I to the error information reception shift register 236.

Next, the operation of the present embodiment will be described with reference to FIGS. 1A and 1B and FIG. 2 showing a timing chart of data reception / transmission in a time chart. For convenience, it is assumed that a start bit ST, data bit groups 0 to 7, a parity bit P, and a stop bit SP are received / transmitted in synchronization with each reception / transmission clock CKR / CKT common to the conventional communication protocol, and a stop bit An error information bit EI is transmitted / received after the bit SP. When a communication error occurs, the reception-side URT unit 13A outputs error information EI from the reception data terminal T11 in synchronization with the reception end signal RE after the reception of the stop bit SP for each communication data. After the transmission of the stop bit SP is completed, the UART section 23A on the transmission side synchronously transmits the transmission data terminal T
The error information EI is taken in from the
When an error occurrence is detected from I, retransmission is executed.

The operation of this embodiment will be described in detail. First, at the time of normal reception, the URT unit 1 on the receiving side is used.
3A, the reception end signal RE output from the reception shift register 132 is inactive, and the input / output control circuit 1
37 switches the reception data terminal T11 to the input state, and supplies the reception serial data DS input from the data terminal T11 to the reception shift register 132 in the same manner as in the related art. The reception shift register 132 stores the supplied serial data D
S is input in synchronization with the reception clock CKR, and is converted into parallel data DP in synchronization with the reception shift clock CSR. At this time, first, the start bit ST, and then 8
Data bit groups 0 to 7, a parity bit P, and a stop bit SP are input. When the stop bit SP is received, the reception end signal RE becomes active, the input / output control circuit 137 switches the reception data terminal T11 to the output state, and outputs 1-bit error information EI. When the output of the error information EI is completed, the input / output control circuit 137
Returns the reception data terminal T11 to the input state, and performs a normal reception operation.

Referring also to FIG. 3A which shows a switching timing of the input / output control circuit 137 in a time chart,
Normal reception ends when the stop bit SP is received from the reception data terminal T11. That is, the reception ends when the stop bit SP is input from the reception data terminal T11 and shifted to the reception shift register 132 at the rise of the reception shift clock CSR, that is, at the timing of tA. Here, the received serial data DS
If a communication error is detected during this time, this communication error becomes active at the rising edge of the communication error detection signal EC, that is, at the timing of tB, and is taken into the error information transmission shift register 135 as error information EI. The reception shift register 132 activates the reception end signal RE at the timing of tC, and the input / output control circuit 137 switches the reception data terminal T11 to the output state in response to the activation of the reception end signal RE, and receives the error information EI. Output from the data terminal T11. After the error information is output, tE
The input / output control circuit 137 switches the reception data terminal T11 to the input state in response to the deactivation of the reception end signal RE, and performs a normal reception operation at the timing shown in FIG.

Next, the operation of the UART 23A will be described with reference to FIG. 3B which is a timing chart showing the switching timing of the input / output control circuit 237 of the UART 23A on the transmitting side. T21
Is terminated by the output of the stop bit SP from. That is, the data of the transmission shift register 232 is shifted and output at the timing of tF. Next, at time tG, the transmission end signal TE becomes active, and the input / output control circuit 237 switches the transmission data terminal 21 to the input state in response to the activation of the transmission end signal TE. Transmission data terminal T
The error information EI input from 21 is taken into the error information reception shift register 236 in synchronization with the next transmission shift clock CST, that is, at the timing of tH. After receiving the error information EI, at the timing of tI, the transmission end signal TE is deactivated, and the input / output control circuit 237 switches the transmission data terminal T21 to the output state in response to the activation of the transmission end signal TE, thereby performing normal transmission. Perform the operation.

As described above, in the receiving UART 13A, when an error is detected, the communication error detection signal EC becomes active, and stores it in the error information transmission shift register 135 as communication error information EI. Each time one communication data ends, the error information EI is output from the reception data terminal T11. The UART 23A on the transmission side takes in the error information EI into the error information reception shift register 236 via the transmission data terminal T21 every time one communication data ends. The error information EI stored in the error information reception shift register 236 is transmitted to the transmission timing control circuit 233 as a retransmission request signal RT. Retransmission request signal R
When T is activated, the transmission timing control circuit 233 executes retransmission processing, that is, the transmission buffer 2
The data of No. 31 is transferred to the transmission shift register 232, and the same data is transmitted again. As described in the related art, there are a plurality of types of communication errors, but the types of errors do not matter here.

The UART 13A of the present embodiment described above,
The serial communication operation between a plurality of microcomputers provided with the A.23A will be described first.
The transmission of the RT unit 23A is permitted, and the UART unit 1 is
3A reception is permitted. Next, in the UART unit 23A,
The transmission data is written to the transmission buffer 231. When the transmission data is written into the transmission buffer 231, the UART unit 23A executes transmission for one communication data. At this time,
The UART section 13A on the receiving side performs a receiving operation for one communication data and detects a communication error. The transmission / reception operation of one communication data starts with a start bit ST, a data bit group of a designated number of bits, a parity bit P, and a stop bit S.
P, which is no different from the operation of the prior art.

Next, when the transmission / reception operation for one communication data is completed, the reception-side UART section 13A switches the reception data terminal T11 to the output state, and transmits error information EI indicating the presence or absence of a communication error via the reception data terminal T11. And send. After the transmission of one communication data is completed, the UART unit 23A on the transmission side switches the transmission data terminal T21 to the input state, and receives the error information EI via the transmission data terminal T21. The UART unit 23A receives the received error information EI.
Is determined. If the error information is "0", that is, it indicates that the communication has been normally performed, the transmission operation of the next one communication data is started. If the error information is “1”, that is, it indicates that a communication error has occurred,
Request retransmission to the timing control circuit, and retransmit the data in which the communication error has occurred. In this way, transmission and reception are performed continuously, for example, until transmission and reception of a desired data frame with 512 communication data as one block is completed.

As described above, in the present embodiment, the UART
By having a communication error processing function in the unit itself, in the processing when a communication error occurs between the microcomputers, there is no need for the intervention of the CPU relating to the communication error processing,
The user can execute communication without being aware of error processing.

In the conventional communication between microcomputers using the UART unit, it is necessary to confirm whether or not a communication error has occurred for each data frame, and to retransmit every data frame when an error occurs. According to the present invention, since retransmission can be performed for each communication data, the number of retransmitted data can be greatly reduced. As an example, one data frame is 512 communication data, and the baud rate is 2400 bps.
Assuming that one communication error occurs during transmission and reception of twelve pieces of communication data, the retransmission time in the conventional processing is 1.706 seconds, but is 0.006 seconds in the processing of the present embodiment. , That is, 99.6% reduction.

Further, by realizing communication error processing by hardware, error processing on communication can be automatically performed, and all software settings for processing upon detection of a communication error can be eliminated. Become.

Next, a receiving UART section 13B and a transmitting UART section 23B according to a second embodiment of the present invention are shown by blocks using common characters / numerals for common components as in FIG. Referring to (A) and (B), the difference between this embodiment and the first embodiment shown in this figure is that the reception-side UART unit 13B converts the contents of a plurality of communication errors into two-bit communication errors. An error information encoding circuit 138 for encoding information EI and an error information transmission shift register 136A expanded to 2 bits in association with the error information encoding circuit 138.
An error information reception shift register 236A expanded to 2 bits to store the error information and an error information decoding circuit 238 for decoding communication error information. In the first embodiment, a 1-bit error indicating the presence or absence of an error as error information is provided. In contrast to the information transmission, this embodiment transmits 2-bit error information indicating the error content.

The error information encoding circuit 138 has a function of encoding a plurality of communication errors as described in the background art. Here, since the type of error does not matter, for convenience of description, Table 1 shows an example of a combination of error contents and error information data when detecting three communication errors, ERR0, ERR1, and ERR2.

[0044]

[Table 1]

Referring also to FIG. 5 showing a timing chart of data reception / transmission timing of the present embodiment,
The transmission timing of the error information receiving side UART 13B according to the present embodiment is such that after the reception of the stop bit SP is completed,
2-bit error information EI according to the combination of Table 1 from the reception data terminal T11 in synchronization with the reception end signal RE
1, EI2.

Input / output control circuit 1 of receiving UART 13B
FIG. 6 is a timing chart showing the switching timing of 37.
The operation of the third embodiment will be described with reference to (A). The reception end signal RE is activated at the timing tC, and the reception data is transmitted in response to the activation of the reception end signal RE. When the terminal T11 is switched to the output state, the error information EI1 and EI2 are output from the reception data terminal T11 in this order. After the output of the error information EI2, the reception end signal RE is deactivated at the timing of tE, and the input / output control circuit 137 switches the reception data terminal T11 to the input state in response to the deactivation of the reception end signal RE. Perform the receiving operation.

Next, the operation of the input / output control circuit 237 of the UART 23B on the transmission side will be described with reference to FIG. , TG, the transmission end signal TE is activated, and the transmission data terminal 21 is switched to the input state. The error information EI1 and EI2 input from the transmission data terminal T21 are taken into the error information reception shift register 236A at the timing of tH,
At the timing of tI, the transmission end signal TE is deactivated, and the input / output control circuit 237 switches the transmission data terminal T21 to the output state in response to the deactivation of the transmission end signal TE, and performs a normal transmission operation.

In this embodiment, the case where there are three types of error contents has been described. However, it goes without saying that this method does not depend on the number of types of error contents.

As described above, this embodiment can cope with a plurality of different types of communication errors. In addition to the case of the first embodiment, the content of the error can be transmitted, and if determined in advance, the processing method for the error occurrence can be changed depending on the content of the error.

[0050]

As described above, in the start-stop synchronous communication apparatus according to the present invention, the reception UART section switches between input of serial communication data and output of communication error information in response to the supply of the reception end signal. A first input / output control circuit; and an error information transmission shift register for transmitting the communication error information to the first input / output control circuit in synchronization with a reception clock. The transmission UART unit supplies a transmission end signal. A second input / output control circuit for switching the output of serial communication data and the input of the communication error information in response to the control signal, and taking the input communication error information in synchronization with a transmission clock and transmitting a retransmission request signal. A shift register for transmitting error information to be transmitted to the circuit, and the UART unit itself has a communication error processing function so that serial communication between microcomputers can be performed. It takes the processing when a communication error occurs, C
There is an effect that the operation can be performed without imposing a load on the PU.

Further, by performing error processing by hardware for each communication data, the number of retransmitted data when a communication error occurs can be greatly reduced, so that the efficiency of processing when a communication error occurs can be greatly improved. There is.

Further, by executing the communication error processing by hardware, various settings for software processing by the CPU can be reduced, and the burden on the user can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a start-stop synchronous communication device according to the present invention.

FIG. 2 is a time chart showing data reception / transmission timing in the start-stop synchronous communication device of the present embodiment.

FIG. 3 is a time chart showing switching timing of an input / output control circuit of each of the UART units on the reception side and the transmission side in the start-stop synchronous communication device of the present embodiment.

FIG. 4 is a block diagram showing a second embodiment of the start-stop synchronous communication apparatus according to the present invention.

FIG. 5 is a time chart showing data reception / transmission timing in the start-stop synchronous communication device of the present embodiment.

FIG. 6 is a time chart showing switching timings of the input / output control circuits of the UART units on the receiving side and the transmitting side in the start-stop synchronous communication device of the present embodiment.

FIG. 7 is a block diagram showing an example of a start-stop synchronous communication system between microcomputers.

FIG. 8 is a block diagram showing an example of a conventional start-stop synchronous communication device.

FIG. 9 is a time chart showing data reception / transmission timing in a conventional start-stop synchronous communication device.

FIG. 10 is a flowchart showing an example of a communication error process in a conventional start-stop synchronous communication device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Receiving microcomputer 2 Sending microcomputer 11 and 21 CPU 12,22 INTC 13,23,13A, 23A, 13B, 23B UA
RT unit 15 internal bus 131 reception buffer 132 reception shift register 133 reception timing control circuit 124 communication error detection circuit 135 communication error register 136, 136A error information transmission shift register 137, 237 input / output control circuit 138 error information encoding circuit 231 transmission buffer 232 Transmission shift register 233 Transmission timing control circuit 236, 236A Error information reception shift register 238 Error information decoding circuit T11 Reception data terminal T21 Transmission data terminal P11 Port

Claims (3)

[Claims] 1. A reception control means shift-inputs received serial communication data in synchronization with a reception clock to generate reception data, and temporarily stores the reception data supplied from the reception shift register. A reception buffer, a reception timing control circuit for controlling generation of the reception clock, shift input of the serial communication data, and storage timing of the reception data, and detects a communication error of the reception data and outputs communication error information. A communication error detection circuit, and a communication error register for storing the communication error information, wherein a transmission control means synchronizes a transmission buffer holding transmission data, the transmission data output from the transmission buffer, and a transmission clock. And a transmission shift register that shifts out and outputs serial communication data. A transmission timing control circuit that controls generation of the transmission clock, shift output timing of the serial communication data, and transfer timing of the transmission data to the transmission shift register, and includes a first microcontroller including the reception control unit. In a start-stop synchronous communication device that performs start-stop synchronous serial communication between a computer and a second microcomputer including the transmission control unit, the reception control unit responds to a supply of a first control signal, A first input / output control circuit that switches between input of serial communication data and output of the communication error information; and a first input / output control circuit that synchronizes the communication error information output by the communication error detection circuit with the reception clock. An error information transmission shift register for transmitting to an output control circuit, wherein the transmission control means supplies a second control signal. A second input / output control circuit that switches between output of the serial communication data and input of the communication error information in response to the communication error information, and synchronization of the communication error information input from the second input / output control circuit with the transmission clock And an error information reception shift register for transmitting a retransmission request signal for requesting retransmission of the transmission data to the transmission timing circuit. 2. The reception control unit further includes an error information encoding circuit that encodes a plurality of types of the communication error information with a predetermined code to generate encoded communication error information. 2. The start-stop synchronous communication device according to claim 1, further comprising an error information decoding circuit that decodes the encoded error information and outputs the plurality of types of communication error information. 3. The second control signal, wherein the first control signal is a reception end signal generated in response to detection of a stop pulse indicating the end of one frame of the received serial communication data. 2. The start-stop synchronous communication device according to claim 1, wherein: is a transmission end signal generated in response to the output of a stop pulse indicating the end of one frame of the transmitted serial communication data.