JPH1065543A - Digital/analog converting method and digital/analog converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide high-accuracy digital/analog(D/A) conversion by inputting/ outputting the input signals of two systems of a digital signal and the other prescribed processed output signal while switching them, independently operating the prescribed calculation for the switched input signals of two systems to obtain the converted value, and averaging and outputting the outputs of converted values before and after switching. SOLUTION: When performing the 1st conversion, a digital signal VLSB(nT) is supplied to a capacitor C12 and a ground signal is supplied to a capacitor C11 . Next, at the time of the 2nd conversion, a ground signal is supplied to the capacitor C12 , and a digital signal '-VLSB(nT)' is supplied to the capacitor C11 . Then, the input signals of two systems of the digital signal and the other prescribed processed output signal are inputted/outputted while being switched and further, processing is performed for obtaining the converted values independently multiplying '1/2' to the switched-out input signals of two systems and adding them. Thus, the outputs of the 1st and 2nd converted values are subtracted and averaged.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital-to-analog conversion method and a converter, and more particularly, to a unit DA.
The present invention relates to a technique for suppressing the influence of the mismatch of the capacitance ratio that determines the gain of C and providing high-accuracy digital-to-analog conversion means.

[0002]

2. Description of the Related Art Hitherto, various methods have been proposed for realizing a high-precision digital-to-analog converter (hereinafter, simply referred to as "DAC" as appropriate) having an accuracy of about 16 bits. Has been put to practical use.

[0003] Among the DACs that have been put into practical use, D is manufactured by being integrated on the same semiconductor substrate using a CMOS process.
A typical example of the AC is a so-called 1-bit DAC manufactured using a ΔΣ modulation method. However, since a DAC manufactured by adopting the ΔΣ modulation method cannot be used without oversampling, a digital filter for performing interpolation must be used.
It must be placed before the DAC. Therefore, DA
Even if a digital code is input due to the influence of the frequency characteristics of the digital filter and the ΔΣ modulator arranged in the preceding stage of C, the output corresponding to the digital code is 1
It does not correspond to one-to-one, and a large delay occurs from input to output of the digital code. A DAC currently proposed as a DAC having high accuracy without such a drawback is actually manufactured by performing a trimming process such as laser trimming or requires some calibration. .

[0004] If an accuracy of about 10 bits is sufficient,
Various DACs that do not require trimming and calibration as described above and can be integrated on the same semiconductor substrate using a CMOS process have been proposed. As one of them, an “algorithmic DAC” using a switched capacitor circuit is well known.

The digital-to-analog conversion (hereinafter simply referred to as “DA conversion” as appropriate) performed by the DAC is realized by using the following equation (1) using a switched capacitor circuit.

[0006]

(Equation 1)

Here, V (x) is a function that takes a value determined by the value of each bit constituting a digital code to be converted. In the case of a unipolar code, “X = 1”
, V (x) = VREFP ”,“ When X = 0, V (x) =
VREFN ”.

Note that the most significant bit and the least significant bit are "MSB" and "LSB", respectively. In the case of a bipolar code, especially “Sign + Magnitude code”, when “MSB = 0” and X = 1, V (x) = VREFP,
When X = 0, V (x) = 0, and “MSB =
1 ”, when X = 1, V (x) = VREFN, and when X = 0, V (x) = VREFN
(X) = 0, and eventually, V (x) becomes “VREFP”,
There are three values, "0" and "VREFN". At this time, VRE
There is a relationship "VREFP = -VREFN" between FP and VREFN.

As a circuit for realizing the DA conversion as shown by the equation (1), a "cyclic click system",
There is a “pipeline method” or a combination of them. Therefore, FIG. 6 shows a configuration diagram of a cyclic algorithmic DAC, FIG. 7 shows a configuration diagram of a pipelined algorithmic DAC, and FIGS. 8 and 9 show respective operation timing diagrams. The operating principle of the “cyclic method” and the “pipeline method” will be described below with reference to FIG.

In the following description, all analog switches are turned on when the control signal is "H (high level)" and turned off when the control signal is "L (low level)". It is also assumed that the gain of the operational amplifier constituting the DAC is sufficiently large. (1) Cyclic Algorithmic DAC The operation of the DAC will be described with reference to FIGS.

The cyclic algorithmic DAC shown in FIG. 6 converts a given digital signal into a voltage (V ₁ ).
And a sample and hold circuit 2 for sampling and holding the output of the unit DAC1,
The sample and hold circuit 3 that samples and holds the output of the sample and hold circuit 2 and the analog switch are turned on.
A clock generation circuit 60 that generates a plurality of types of clock signals to be turned off. Further, the unit DAC1
Two capacitance elements C ₁ and C ₂ connected to the inverting terminal of the operational amplifier 61 and analog switches 62, 63, 64 and 6
5, 66, 67, and 68. The analog switches 62, 65 and 66 are controlled by the clock φ ₁
The analog switches 63 and 64 are controlled by the clock φ ₂ to turn on and off. Analog switch 67
Is connected to an input terminal (V _IN ), the connection state with the ground point is controlled by a clock φ _init , and the analog switch 68 is controlled by a clock φ _conv . Note that a digital signal V _DIN is input to an input terminal connected to the analog switch 65.

The sample hold circuit 2 includes an operational amplifier 7
0 inverting the capacitor C _S1, which is connected to the terminal of, and an analog switch 69,71, 72, the analog switch 71 is turned on and off controlled by the clock phi _1, The analog switches 69 and 72 are , Clock φ
It is turned on and off by ₁ phi _2, the circuit to sample and hold the output V ₁ of the unit DAC1, and outputs it as V _2. Moreover, the sample hold circuit 3, a capacitor C _S3 connected to the non-inverting terminal of the operational amplifier 75 which is negative feedback-connected, comprises an analog switch 76, the analog switch 76, clock phi _samp Therefore on-off is controlled, the circuit output V ₂ of the sample and hold circuit 2 samples and holds, and outputs it as V _OUT.

A timing chart of the clocks φ ₁ , φ ₂ , φ _samp is shown in FIG. 8. Φ ₁ and φ ₂ alternately change in level, and φ _samp changes for a predetermined time every time interval T. Only ((1/4) .T) becomes high level. Note that φ _init is supplied to be at a high level only at the initial _stage .

First, the operation of the unit DAC1 will be described. In the sample period of “φ ₁ = H, φ ₂ = L”,
Since only the analog switches 62, 65, and 66 are turned on, the operational amplifier 61 has a voltage floor, and the voltage of the inverting input terminal of the operational amplifier 61 becomes equal to the input-referred offset voltage V _OFF of the operational amplifier 61.
Further, since the analog switches 65 and 66 are on, the voltages on the input side of the capacitance elements C ₁ and C ₂ are V _IN and V
It becomes _DIN . Therefore, the electric charges Q ₁ and Q ₂ stored in the capacitance elements C ₁ and C ₂ are as follows, respectively.

Q ₁ = C ₁ · (V _IN −V _OFF ), Q ₂ = C
_2. (V _DIN -V _OFF ). Next, in the hold period of “φ ₁ = L, φ ₂ = H”, only the analog switches 63 and 64 are turned on, and the charges Q ₁ and Q ₂ are stored. To establish. (C ₁ + C ₂ ) · (V ₁ −V _OFF ) = C ₁ · (V _IN −V
_OFF ) + C ₂ · (V _DIN −V _OFF ) Therefore, V ₁ is represented by the following equation (2).

[0016]

(Equation 2)

Here, assuming that C ₁ = C ₂ , equation (2) is rewritten as equation (3) and becomes as follows.

[0018]

(Equation 3)

As described above, the unit DAC1 performs DA conversion by multiplying the digital signal V _DIN by “１ ／” by alternately changing the clocks φ ₁ and φ ₂ . Next, the operation of the sample and hold circuit 2 will be described.

The basic operation of the sample and hold circuit 2 is the same as that of the unit DAC, but since the phases of the control signals φ ₁ and φ ₂ are opposite, “φ ₁ = L, φ ₂ = H” and the analog switch 69 , 72 are turned on and the operational amplifier 70
Becomes a voltage floor, and thus becomes a sample period. On the other hand, when “φ ₁ = H, φ ₂ = L”, only the analog switch 71 is turned on, and a hold period is generated. The output V ₂ during the hold period is equal to C in the equation (2).
_{Since 1} is replaced by C _S1 and C ₂ = 0, the output V ₂ is represented by the following equation (4).

[0021]

(Equation 4)

As described above, the sample hold circuit 2
The output V ₁ of the unit DAC1 and sample-and-hold,
It is the output V _2. Then, when outputting the final output voltage V _OUT, since its output must become a continuous waveform, the only sample and hold circuit 2 phi ₂ =
Since "0" is output at the time of H, another circuit must be provided, but this circuit is the sample and hold circuit 3.

The sample hold circuit 3, when the phi _samp = H, since the analog switch 76 is turned on, V ₂
And outputs V ₂ at the same time. And φ
_{When samp} = L, the analog switch 76 is turned off to hold this voltage.

Next, the operation of the entire DAC will be described. The input voltage according to the input code (digital signal) is V
A voltage corresponding to the data is input as _{DIN and} for each bit of data constituting the input code, that is, from LSB to MSB. The conversion process starts from the LSB, and only when the conversion is started, the clocks φ _INIT and φ _conv are respectively φ _INIT = H and φ _conv = L (usually φ _INIT = L and φ _conv).
conv = H), and V _IN = 0. At this time, V _DIN =
V (LSB), this value is halved by the unit DAC1, and the output V ₁ is V ₁ = (１ ／) · V (LS
B). This voltage is sampled and held by the sample and hold circuit 2, so that the hold output V ₂ becomes V ₂
= The V _1.

Next, the conversion of the “LSB + 1” bit is performed. Thereafter, until the conversion is completed, φ _INIT = L, φ _conv
= H and V _IN = V ₁ . By the way, "LSB + 1"
At the time of bit conversion, V _IN = V ₁ , V _DIN = V (LSB
+1), it is considered in the same manner as in the LSB conversion, and V ₂ =
V ₁ = 1 / 2V (LSB) + (1/2) ² · V (LSB
+1).

Similarly, when conversion is performed up to the MSB, the output V
₂ matches equation (1). The voltage value V ₂ at this time, the sample-and-hold circuit 3 is sampled and held until the sampling voltage following conversion ends. Digital-to-analog conversion is performed by repeating the above operation. The above is the outline of the operation of the cyclic algorithmic DAC. (2) Pipelined Algorithmic DAC Next, the operation of the pipelined algorithmic DAC will be described.

The operation of the DAC will be described with reference to FIGS. The pipelined algorithmic DAC shown in FIG. 7 includes a first unit DAC1 (10) that converts a given digital signal into a voltage (V ₁ ), and a second unit DAC1 (10).
And a sample-and-hold circuit 3 that samples and holds the output of the unit DAC2 (50), and turns on the analog switch.
And a clock generation circuit 80 that generates a plurality of types of clock signals to be turned off. Further, the unit DAC1 (1
0) are two capacitive elements C ₁₁ and C ₁₂ connected to the inverting terminal of the operational amplifier 81 and analog switches 82 and 83,
84, 85, and 86. Analog switch 8
2, 85 and 86 are controlled by a clock φ ₁ , and the analog switches 83 and 84 are controlled by a clock φ ₂ to turn on and off. The analog switch 85 has a connection state to a ground point controlled by the clock φ ₁ .
The voltage V _LSB (nT) for SB is input. In addition,
nT (n is an integer) represents a certain time. Also,
Unit DAC2 (20) is provided with two capacitive elements C _21, C ₂₂ connected to the inverting terminal of the operational amplifier 90, an analog switch 91,92,93,94,95. The analog switches 92 and 93 are controlled by a clock φ ₁ , and the analog switches 91, 94 and 95 are controlled by a clock φ ₂ to turn on and off. The analog switch 94 controls the connection state with the unit DAC1 (10) by the clock φ ₂ , and inputs “LSB +
The voltage V _{LSB +1} ((n−1) T) for the “1” bit is input. In the figure, voltages for the “MSB-1” bit and the “MSB” bit are input to the unit DAC1 (40) and the unit DAC2 (50), respectively.

The pipeline system operates in principle in the same manner as the cyclic system. However, the same unit DAC is repeatedly used in the cyclic system described above, whereas the unit DAC is used in the pipeline system. They are connected in series.

As shown in FIG. 9, the clock φ ₁ ,
φ ₂ alternately changes every unit time, and the control signal φ _samp of the sample and hold circuit 3 also changes every unit time,
It alternates between a high level and a low level. Then, in the unit DAC1, the sampling period is “φ ₁ = H, φ ₂ = L” and “φ ₁ = L, φ ₂ = H”.
Is the hold period. On the other hand, in the unit DAC2,
Performs the opposite operation.

In the pipeline system, the sample-and-hold circuit 2 used in the cyclic system is not required, and the unit DAC in the next stage can double as the sample-and-hold circuit. At this time, the control signals φ ₁ , φ
The phase of ₂ is inverted every stage. In the pipeline method,
Since the conversion voltage is propagated to the MSB side in order from the LSB, assuming an m-bit DAC, the input voltage of each unit DAC at a certain time nT is as follows in the case of a unipolar.

V _LSB = V _LSB (nT) V _{LSB +1} = V _LSB ((n-1) T) V _{LSB +2} = V _LSB ((n-2) T)...,..., V _MSB-1 = V _MSB-1 ((n−m + 2) T) V _MSB = V _MSB ((n−m + 1) T).

Thus, the pipelined algorithmic DAC performs the DA conversion operation. Note that the cyclic algorithmic DAC has a small circuit scale and low current consumption, but has a low conversion speed.
It is known that the pipelined algorithmic DAC has a high conversion speed, but has a large circuit scale and a large current consumption.

[0033]

By the way, by using the above-mentioned algorithmic DAC, it is possible in principle to perform error-free D / A conversion. It is difficult to realize. The factors that hinder the high precision of the DAC are specifically enumerated as follows. (1) The gain of the operational amplifier used in the unit DAC and the sample-and-hold circuit is an ideal value, that is, a finite value instead of an infinite value. (2) An operational amplifier has an offset voltage. (3) Feedthrough noise is generated from an analog switch included in the unit DAC and the sample / hold circuit. (4) For bipolar code input type, VREFP and V
Absolute value deviation between REFN. (5) In the unit DAC, there is a mismatch in the capacity determining the coefficient of "1/2", that is, a coefficient error occurs due to a difference in the capacity value.

Next, a method of coping with the above-described factors (1) to (5) for preventing the high accuracy from being considered will be described below. (1) The fact that the gain of the operational amplifier is a finite value can be eliminated as a factor preventing high precision by using an operational amplifier having a gain necessary to achieve a desired accuracy (number of bits). Becomes For example, in order to obtain 16-bit precision, an operational amplifier having a gain of about 100 (dB) is required. This gain value is a value that can be sufficiently realized by an operational amplifier manufactured by a CMOS process. (2) As described in the prior art, the influence of the offset voltage of the operational amplifier can be eliminated by using the offset cancel unit DAC and the sample-and-hold circuit. It is not a factor. (3) Normally, the feedthrough noise is considered to be the sum of a DC component that does not depend on a signal and a signal dependent component. It is known that a component serving as a function can be canceled by using the entire operation circuit if there is no mismatch between the positive side and the negative side. Therefore, so that the feedthrough noise becomes an even function with respect to the input signal,
Although various methods have been proposed, description will be made using the unit DAC1 shown in FIG.

In general, it is known that the clock phase is set as follows as a measure against feedthrough noise. That is, of the analog switches controlled by the clock phi _1, the analog switch to the analog switch connected between the inverting input terminal and the output terminal of the operational amplifier, is turned off earlier than the other analog switch-on・ The off state shall be controlled. By performing the switching control in this manner, the capacitance elements C ₁ , C ₂
The charge caused by the feedthrough noise stored in the analog amplifier is only the analog switch connected between the inverting input terminal and the output terminal of the operational amplifier. When the analog switch is turned off, the voltage at both ends of the analog switch matches the ground voltage, but since the feedthrough noise depends on the voltage at both ends of the analog switch, switch control is performed as described above. Thereby, signal-dependent feedthrough noise can be significantly suppressed. Furthermore, considering the small-level signal-dependent feedthrough noise that cannot be completely removed by the above method,
Since this noise is generated depending on the impedance of the circuit as viewed from the analog switch, the on-resistance of the analog switch connected to V _IN and V _DIN is an even function of the signal level, that is, the absolute value of the input signal is By using a CMOS analog switch so that the on-resistances are equal if they are equal, the charge due to the signal-dependent feedthrough noise becomes an even function. By performing the switching control in this manner, the feedthrough noise can be significantly reduced, so that the generation of the feedthrough noise does not always prevent the high accuracy. (4) Since the absolute value of the input voltage is always VREFP-VREFN when the so-called all-operation circuit is used, this error factor is cancelled, and there is no difference in absolute value between VREFP and VREFN. However, this is not necessarily a hindrance to higher precision. (5) When a capacitance element having the same capacitance value is manufactured by a CMOS process, the accuracy of the mismatch of the capacitance ratio is usually less than 1 (%) when a two-layer polysilicon is used as an electrode (double polysilicon process). In the case where the polysilicon layer and the aluminum wiring layer are used as electrodes (single silicon process), the value is about 1 (%).

In the case where there is a capacitance ratio error between the capacitance elements used in the unit DAC shown in FIGS. 6 and 7, a quantitative error analysis is performed using a 3-bit pipeline type DAC as an example.

First, the following conditions are assumed. C _i1 + C _i2 = 2C _i0 C _i1 = C _i0 (1−α _i ) C _i2 = C _i0 (1 + α _i ) where α _i is a mismatch of the capacitance ratio.

Further, the gain of the operational amplifier is infinite,
It is assumed that the charge amount due to the feedthrough noise is “ΔQ _i ” (ΔQ _i is generated at the end of the sample period, and the feedthrough noise generated at the end of the hold period is not propagated to the next stage). The subscript “i” represents a bit, “LSB = 1, LSB + 1 =
2, ..., ".

At this time, V ₁ after the conversion of LSB is:
It is given by equation (5) as follows.

[0040]

(Equation 5)

The same calculation is performed, and the output V ₃ of the third bit is obtained.
Is given by the following equation (6).

[0042]

(Equation 6)

As can be seen by referring to equation (6), the first order term of the capacitance ratio error appears in the output.
If the error is in the order of percent, the output will have an error in the order of percent.

When the capacitance ratio error α of the unit DAC shown in FIG. 6 is α = 0.01 (that is, the capacitance ratio error of the capacitance elements C ₁ and C ₂ is 1 (%)), the cyclic method is used. FIG. 10 shows the INL characteristic of the 8-bit DAC. In FIG. 10, the horizontal axis indicates digital inputs “−128” to “128” (unit, LSB), and the vertical axis indicates error (unit, LSB). It can be seen that a maximum error of about 0.6 (LSB) occurs.

FIG. 11 shows INL characteristics when the capacitance ratio error α = −0.01. In FIG. 11, as in FIG. 10, the horizontal axis indicates digital inputs “−128” to “128” (unit, LSB), and the vertical axis indicates error (unit, LSB). It can be seen that a maximum error of about 0.6 (LSB) occurs. Under these conditions, the INL error is about 0.6
The LSB and DNL errors are about 1.2 LSB and 1
With a capacitance ratio error of (%), only an accuracy of about 8 bits can be secured, and in order to realize a DAC having a 10-bit accuracy, the capacitance ratio error must be about 0.2 (%) or less. Disappears.

That is, an algorithmic DA using a switched capacitor circuit using a CMOS process
In C, there is a problem that it is very difficult to secure accuracy of 10 bits or more.

As described above, the deterioration of accuracy due to the factors (1) to (4) can be reduced by using all the operation circuits.
The accuracy can be improved to about 6 bits. However, due to the coefficient error generated due to the occurrence of the capacitance ratio error of (5), only a DAC with an accuracy of about 10 bits could be realized.

Therefore, as described in the prior art, in order to realize a digital-to-analog converter in which the integrated output and input code correspond one-to-one, trimming, calibration, and the like are performed. There is an unsolved problem that has to be used and leads to an increase in manufacturing cost.

Accordingly, an object of the present invention is to provide a highly accurate digital-to-analog conversion which suppresses the influence of the mismatch of the capacitance ratio determining the gain of the unit DAC without using a complicated manufacturing process. Is to do.

[0050]

In order to achieve the above object, according to the first aspect of the present invention, a digital signal and another signal subjected to predetermined processing are switched between two input signals. A step of inputting and outputting, a step of independently multiplying the output signals of the two systems by "1/2" to obtain a converted value, and a first converted value before switching and a second converted value after switching Averaging and outputting the converted values of the converted values.

According to a second aspect of the present invention, in addition to the first aspect, the average is an addition average or a subtraction average of a first conversion value and a second conversion value.
A digital-to-analog conversion method is provided.

Further, according to the third aspect of the present invention, there is provided a switching section for switching and inputting and outputting two systems of input signals, that is, a digital signal and another signal subjected to predetermined processing, A unit DAC circuit including a conversion unit that obtains a converted value by independently multiplying the output two-system input signals by “１ ／”; a first converted value before switching and a second converted value after switching And a sample-and-hold circuit that samples and holds the averaged value.

More specifically, as set forth in claim 4, a digital / analog having at least one unit DA converter for inputting a digital signal corresponding to a digital code and a predetermined signal and converting and outputting the added signal In the converter, the unit DA converter switches two or more capacitance elements that sample the digital signal and the predetermined signal, and switches input to each capacitance element between the digital signal and the predetermined signal. And a control unit for controlling the conversion operation so as to perform the DA conversion (digital / analog conversion) two or more times with the switching means activated, and further with the switching means activated. And a digital-to-analog converter provided with an arithmetic unit for adding or subtracting the outputs of the D / A conversion. This digital-analog converter is configured to output a difference between a DA conversion output of an input digital code and a DA conversion output of a digital code in which the polarity of the digital code is inverted in a state where the capacitance element is switched. Or the DA of the digital code in a state where the DA conversion output of the input digital code and the capacitive element are switched.
A configuration in which the sum of the conversion output and the output is output is also preferable.

[0054]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 shows a configuration diagram of a pipelined algorithmic DAC according to an embodiment of the present invention, and FIG. 4 shows a timing chart of a corresponding control clock.

The pipelined algorithmic DAC shown in FIG. 2 converts a given digital signal into a voltage (V ₁ ).
A plurality of sets of a first unit DAC1 (160) and a second unit DAC2 (170),
Further, a subtraction circuit 35 for subtracting the output of the unit DAC2 (500), a sample and hold circuit 45 for sampling and holding the subtraction result (V _SUB ), and a clock generation for generating a plurality of types of clock signals for turning on and off the analog switch. And a circuit 180. Further, unit D
AC1 (160) includes two capacitance elements C _11, C ₁₂ connected to the inverting terminal of the operational amplifier 161, analog switches 162,163,164,165,166,167,
168. The analog switch 164 is driven by the clock φ ₁ and the analog switch 162,
163 is turned on / off under the control of the clock φ ₂ . The analog switches 167 and 168 are controlled by clocks φ ₁₁ and φ ₁₂ , respectively.
In both 67 and 168, the connection state with the ground point is controlled by the clock. In addition, the analog switches 165, 1
66 is controlled by clocks φ ₁₁ and φ ₁₂ , respectively, and the analog switch 165 is controlled so that a voltage “V _LSB (nT)” corresponding to the voltage of “LSB” at time nT can be input. 166 is a voltage “−V _LSB ” corresponding to the reverse polarity of the voltage of “LSB” at time nT.
(NT) ". Similarly, the unit DAC 2 (170) includes two capacitive elements C ₂₁ and C ₂₂ connected to the inverting terminal of the operational amplifier 171 and analog switches 172, 173, 174, 175, 176,
77, 178. Analog switch 174
Is controlled by the clock φ ₂ and the analog switch 1
72,173 is controlled by the clock phi _1, on and off. The analog switches 177 and 178 are controlled by clocks φ ₂₂ and φ ₂₁ , respectively, and the connection state of the analog switches 177 and 178 to the unit DAC 1 (160) is controlled by the clock. The analog switches 175 and 176 are controlled by clocks φ ₂₁ and φ ₂₂ , respectively.
Is controlled so that the voltage “V _{LSB + 1} ((n−1) T)” corresponding to the voltage of “LSB” at the time “(n−1) T” can be input, and the analog switch 166 Time nT
"-V" corresponding to the opposite polarity of the voltage of "LSB"
_{LSB + 1} ((n-1) T) "is controlled to be inputtable.

As shown in FIG. 4, when the period of the sample-and-hold signal φ _SAMP of the sample-and-hold circuit 45 is T, φ ₁ and φ ₂ alternately change every “(１ ／) · T”. At the same time, the control signal φ _reset of the subtraction circuit, which will be described in detail later, rises at the fall of φ _SAMP and falls after “(１ ／) · T”.

[0057] Further, phi _11, together with phi ₁ becomes high level in synchronism with the high level signal, phi ₁ goes low in synchronism with the low level signal, this time, new in synchronization with phi ₂ becomes high level, with phi ₂₁ becomes high level, in synchronism with phi ₂ becomes the low level signal phi ₂₁ becomes a low level. Further, when φ ₁ becomes a high level signal again, in synchronization with this, φ _{1
At the same time that 12} goes high and φ ₁ goes low, φ ₁₂ goes low,
Synchronously newly becomes a high level phi _2, with phi ₂₂ becomes high level, in synchronism with phi ₂ becomes the low level signal phi ₂₂ becomes a low level. Thus, it phi ₁₁ and phi _12, phi ₂₁ and phi ₂₂ are alternately level changes. In this _{way, φ 1, φ 2, φ} 11, φ 12, φ 21, as phi ₂₂ changes, the clock generating circuit 180 is configured to provide a clock as a control signal to a predetermined analog switch ing.

The sample-and-hold circuit 45 corresponds to FIG.
A circuit having the same configuration as the sample-and-hold circuit 3 may be employed, and a configuration example of the subtraction circuit 35 may employ a circuit having the same configuration as the subtraction circuit 35 described later with reference to FIG. .

Next, the algorithmic D according to the present invention
The operation of the AC will be described using a pipeline DAC as an example. The unit DAC used in the conventional pipelined DAC performs the conversion operation once for each digital input code, but the present invention is characterized in that the conversion operation is performed twice each. Hereinafter, each unit D
The operation of the AC will be described by taking the unit DAC1 (160) in FIG. 2 as an example. A necessary clock is supplied according to the timing chart shown in FIG.

First, when the first conversion is performed, φ ₁₂
Is fixed at L, and φ ₁₁ = φ ₁ . At this time, the analog switches 166 and 167 are turned off, and the analog switches 165 and 168 are turned on in accordance with the control clock φ ₁₁ = φ ₁ .

At this time, through the analog switch 165
And the capacitive element C₁₂Digital signal V _LSB(NT) supplied
And at the same time, via the analog switch 168,
Quantity element C₁₁To the ground signal (predetermined processing (switching processing
And other signals) are supplied.

Therefore, at this time, since the same operation as that of the unit DAC1 described with reference to FIG. 6 is performed, assuming that only the capacity ratio error of the unit DAC degrades the conversion accuracy, the unit DAC1 (160) The output is
This is consistent with the above-described equation (5).

Next, in the second conversion, conversely, φ ₁₁ becomes L
And φ ₁₂ = φ ₁ . At this time, the analog switches 165 and 168 are turned off, and the analog switches 166 and 167 are turned on in accordance with the control clock φ ₁₂ = φ ₁ . At this time, the analog switch 1
Through 67, together with the ground signal (predetermined processing (other output signal considered as switching process) has been performed) is supplied to the capacitive element C _12, via the analog switch 166, a digital to the capacitor C ₁₁ signal "-V _LSB (n
T) "is supplied. Thus, an input digital signal, rather than V _LSB (nT), a -V _LSB (nT). At this time, the output is expressed by the following equation (7).

[0064]

(Equation 7)

Comparing the expressions (5) and (7), the polarity of the input voltage V _LSB is opposite, and the coefficient of α ₁ is changed from “1” to “−”.
It can be seen that only the point changing to "1" is different. Also, the charge amount ΔQ due to feedthrough noise
₁ is equal, assuming that there are only components that are even functions with respect to the input.

Similarly, at the timing shown in FIG.
When φ ₁₁ , φ ₁₂ , φ ₁ , φ ₂ change and the analog switch corresponding to each clock is turned on / off, the output of the third bit by the first conversion operation becomes (6 ), And the result of the second conversion operation is given by the following expression (8).

[0067]

(Equation 8)

The unit DAC2 (170) is connected to the analog switches 162 to 162 of the unit DAC1 (160).
168 is replaced by 178 from 173 and the clock φ
₁₁ , φ ₁₂ , φ ₁ , φ ₂ are clocks φ ₂₁ , φ ₂₂ , φ ₂ ,
Considering that changes in phi _1, because the operation itself is unchanged, omitted. In addition, the unit DAC1 (400), which is another unit DAC, the unit DAC2
The same applies to (500). However, since the pipeline processing is performed, the digital signal to be converted is shifted by one bit for each unit DAC.

Hereinafter, when the digital input signal is supplied in this manner, the conversion operation is performed according to the control clock. That is, two input signals of a digital signal and another output signal subjected to a predetermined process are switched and input / output, and further, the switched two input signals are independently multiplied by “１ ／”. In other words, a process of obtaining the converted value obtained by the addition is performed.

Next, the operation of the subtraction circuit 35 will be described. The subtraction circuit 35 is the same as the subtraction circuit 35 shown in FIG. 1. Although FIG. 1 is a circuit of a cyclic DAC instead of a pipeline DAC, it will be described here.

First, when φ _reset = H, the subtraction circuit 35
Is set to V _IN1 and the input offset of the operational amplifier 37 is set to V _OFF1 . Since the analog switch 36 is turned on, the operational amplifier 37 is in a voltage follower state, so that the output V _{SU B1} is V _SUB1 = V _OFF1 . Further, assuming that the charges charged to the capacitance elements C _S2 and C _H at this time are Q _S2 and Q _H , respectively, they are expressed by the following equations.

Q _S2 = C _S2 · (V _IN1 −V _OFF1 ) Q _H = 0 On the other hand, when φ _reset = L and the analog switch 36 is turned off and the input voltage is set to V _IN2 , this charge Q _{Since S2} remains conserved, the following equation holds according to the charge conservation law. C _S2 (V _IN1 −V _OFF1 ) = C _S2 (V _IN2 −V _OFF1 ) + C
_H (V _SUB2 −V _OFF1 ) Therefore, at this time, V _SUB2 is given by the following equation (9).

[0073]

(Equation 9)

Here, if C _S2 = C _H , equation (9) becomes equation (10).

[0075]

(Equation 10)

According to the timing chart shown in FIG. 4, V _IN1 is equal to the first DAC conversion output,
_IN2 is equal to the converted output of the second DAC. Therefore, V
_SUB2 is represented by the following equation from equations (6), (8), and (10).

[0077]

[Equation 11]

In this way, the processing of subtracting and averaging the output of the first conversion value and the output of the second conversion value is performed. Of course, the addition averaging may be used instead of the subtraction averaging, but the subtraction averaging is preferable because the offset of the operational amplifier is canceled.

Next, the sample-and-hold circuit 45 located at the last stage samples and holds the above-mentioned V _SUB2 , so that its output is _obtained by adding the offset voltage V _OFF2 of the sample-and-hold circuit 4 to V _SUB2 . Therefore, the output V _OUT is as shown in the following equation (12). Incidentally, the sample-hold circuit 45 for use in a pipelined manner DAC may be used the same as the sample-hold circuit 45 shown in FIG. 1, the circuit, as shown in FIG. 1, the operational amplifier 46 and the capacitor C _S3 Is configured to sample and hold the voltage output from the subtraction circuit 35 by the operation of the analog switch 47 controlled by the clock φ _samp .

[0080]

(Equation 12)

As can be seen from the equation (12),
Since V _OFF1 and V _OFF2 are constant values that do not depend on the input code, they are output offsets, but they do not cause deterioration of DAC accuracy. Also, the first-order term of α is removed by taking the difference between the two conversions, the term of ΔQ is basically removed, and the component that is not canceled is multiplied by the term of the capacitance ratio error α as a coefficient. Equation (6)
As compared with the equation (8), the error component becomes sufficiently small.

Therefore, the high-precision pipeline system D
AC can be realized. Next, a cyclic DAC will be described with reference to FIGS. The cyclic algorithmic DAC shown in FIG.
A unit DAC 15 for converting a given digital signal into a voltage (V ₁ ), a sample and hold circuit 25 for sampling and holding the output of the unit DAC 15, a subtraction circuit 35 for subtracting the output of the sample and hold circuit 25, and sampling the subtraction result Sample hold circuit 4 to hold
5 and a clock generation circuit 48 for generating a plurality of types of clock signals for turning on / off the analog switch. Further, the unit DAC 15 includes an operational amplifier 150
Two capacitive elements C ₁ and C ₂ connected to the inverting terminal of
Analog switches 151, 152, 153, 154, 1
55, 156, 157, 158, and 159. The analog switch 159 is controlled by a clock φ ₁ , and the analog switches 151 and 152 are controlled by a clock φ ₂ to turn on and off. The analog switch 157 controls the connection state with the ground point by the clock φ _init .
Is controlled by a clock φ _conv . The analog switches 153 and 154 are connected to the clocks φ ₁₁ and φ _{11 respectively} .
₁₂ and connected to analog switches 157 and 158. In addition, analog switch 1
56 and 155 are controlled by clocks φ ₁₁ and φ ₁₂ , respectively. The analog switch 156 receives a digital signal V _DIN, while the analog switch 155 receives a digital signal “−V _DIN ” having a different polarity. Is entered.

[0083] Further, the sample-hold circuit 25, a capacitor C _S1, which is connected to the inverting terminal of the operational amplifier 29 comprises an analog switch 26, 27, and 28, the analog switch 26, on the clock phi ₁ The analog switches 27 and 28 are ON / OFF controlled by clocks φ _{1 and} φ _2. The circuit samples and holds the output V _{1 of the} unit DAC ₁ and
Output as ₂ .

Further, the subtracting circuit 35 includes an operational amplifier 37.
In, connect the negative feedback capacitor C _H, further provided in parallel with the negative feedback capacitor C _H, the clock φ and the analog switch 36 controlled by the _reset, the capacitor C which is connected to the inverting terminal of the operational amplifier 37 _S2 . Further, the sample-and-hold circuit 45 includes an operational amplifier 4 connected in a negative feedback manner.
A capacitor C _S3 connected to the non-inverting terminal of the 6 comprises an analog switch 47, the analog switch 47
Is controlled on and off by a clock φ _samp , and this circuit samples and holds the output V _SUB of the subtraction circuit 35,
Output as V _OUT .

The timing chart of each clock is shown in FIG. 3, where φ ₁ and φ ₂ change level alternately at time intervals “(１ ／) · T”.
At each time interval T, φ _samp goes high for a predetermined time. Note that φ _init is supplied to be at a high level only at the initial _stage . φ _reset changes between a high level and a low level at each time interval of “(１ ／) · T”. Also, φ
_12, phi ₁₁ is equal to phi ₁ at a low level, whereas, phi ₁₁ it is, phi ₁₂ are clock generation to be equal to phi ₁ at a low level. The clock generation circuit 48
Clocks φ ₁ , φ ₂ , φ _samp , φ
_Reset , φ ₁₁ , φ ₁₂ , φ _init , and φ _CONV can be supplied to a predetermined analog switch.

The operations of the subtraction circuit 35 and the sample-and-hold circuit 45 are as described above, and will not be described again. Note that instead of the subtraction circuit 35,
A circuit for performing averaging may be employed. The sample-and-hold circuit 25 includes a sample-and-hold unit including an operational amplifier 29 and a capacitive element C _S1.
The voltage V ₁ output from the counter 5 is sampled and held so as to become the output V by the operation of the analog switches 26, 27 and 28 controlled by the clocks φ ₁ and φ ₂ .

An outline of the operation of the unit DAC 15 will be described with reference to the timing chart of FIG. First, the conversion process is started from the LSB, and only at the start of the conversion, the clocks φ _INIT and φ _conv become φ _INIT = H and φ _conv = L (normally φ _INIT = L and φ _conv = H), respectively. _IN = 0. At this time, V _DIN = V (LSB). Next, "L
The conversion of “SB + 1” bits is performed, and φ _INIT = L and φ _conv = H until the conversion is completed.

When the first conversion is performed, φ ₁₁ is fixed at L, and φ ₁₂ = φ ₁ . At this time, the analog switches 153 and 156 are turned off, and the analog switches 154 and 155 are turned on in accordance with the control clock φ ₁₁ = φ ₁ . Therefore, the analog switch 1
Through 55, with a digital signal "-V _DIN" is supplied to the capacitive element C ₁ is inputted, the analog switch 15
4, a signal V ₂ (another signal on which a predetermined process has been performed) is input and supplied to the capacitive element C ₂ .

The analog switch 159 is on / off controlled in accordance with the control clock φ ₁ , and the analog switches 151 and 152 are on / off controlled in accordance with the control clock φ ₂ .

Therefore, at this time, since the same operation as that of the unit DAC 1 described with reference to FIG. 6 is performed, if the factor that deteriorates the conversion accuracy is only the capacitance ratio error of the unit DAC, the output of the unit DAC 15 becomes This is consistent with the above-described equation (5).

Next, in the second conversion, conversely, φ ₁₂ becomes L
And φ ₁₁ = φ ₁ . At this time, the analog switches 154 and 155 are turned off, and the analog switches 153 and 156 are turned on in accordance with the control clock φ ₁₂ = φ ₁ . Therefore, the analog switch 15
6, a digital signal “V _DIN ” is input and supplied to the capacitive element C ₂ , and a signal V ₂ (another output signal on which predetermined processing has been performed) is input via the analog switch 153. It is supplied to the capacitor C _1. Thus, the second input digital signal is not -V _DIN ,
V _DIN .

The unit DAC 15 performs such an operation in accordance with a clock, switches and inputs and outputs two input signals of a digital signal and another output signal on which predetermined processing has been performed, and further switches. A process of independently multiplying the output two-system input signals by "1/2" to obtain a converted value is performed.

That is, the unit DAC of the cyclic system
15 also performs basically the same operation as the pipeline system, and differs in whether the same unit DAC is used repeatedly (cyclic system) or connected one bit at a time in series (pipeline system). In the case of a cyclic DAC, the coefficients in equation (12) are as follows.

Α ₁ = α ₂ = α ₃ C ₁₀ = C ₂₀ Therefore, equation (12) can be rewritten as equation (13).

[0095]

(Equation 13)

[0096] Thus, even in a cyclic manner DAC according to the invention, V _OFF1, V _{OF F2} is because a constant value independent of input code becomes the output offset,
It does not cause a deterioration in the accuracy of the DAC. Also, α
Is removed by taking the difference between the two transforms, the term ΔQ is also basically removed, and the component that is not canceled is multiplied by the term of the capacitance ratio error α as a coefficient. As compared with the equations (6) and (8), the error component becomes sufficiently small, and a highly accurate cyclic DAC can be realized.

FIG. 5 shows the INL characteristics of a cyclic algorithmic DAC according to the present invention. In FIG. 5, the capacitance ratio error α = 0.01 is for an 8-bit DAC, and the gain of the operational amplifier is 200 (dB).
It is. In FIG. 5, the horizontal axis indicates digital input “−128” to
"128" (unit, LSB) is taken, and the error (unit, LSB) is taken on the vertical axis. Maximum, 0.005 (LS
It can be seen that an error of about B) occurs. As can be seen by comparing FIG. 5 with FIG. 10 and FIG.
It can be seen that the accuracy of the order of bits has been improved to the accuracy of 16 bits.

As described above, according to the algorithmic DAC according to the present invention, the influence of the capacity ratio error that determines the gain of the unit DAC is changed from the primary one in the conventional system to the secondary one. So you can
The precision can be doubled in terms of bits, that is, n-bit precision can be improved to 2n-bit precision. Therefore, high-precision digital-to-analog conversion means of about 16-bit accuracy, in which the output corresponds to the input code on a one-to-one basis, can be realized without using trimming, calibration, or the like. Accurate digital-to-analog conversion means can be realized.

[0099]

As described above, according to the first aspect of the present invention, input / output is performed by switching between two input signals of a digital signal and another output signal which has been subjected to predetermined processing.
The two switched input signals are independently converted to “1 /
2 "to obtain a converted value, and outputs the average of the output of the first converted value before switching and the output of the second converted value after switching, so that the capacitance determining the gain of the unit DAC is output. High-precision digital-to-analog conversion with the effect of ratio mismatch suppressed.

According to a second aspect of the present invention, in addition to the first aspect, the average is obtained by adding or subtracting the average of the first conversion value and the second conversion value. , More accurate digital-to-analog conversion can be realized.

Further, according to the third aspect of the present invention, the conversion section independently multiplies the two input signals of the digital signal and the other output signal subjected to the predetermined processing by "1/2". To obtain a converted value, the averaging circuit averages the output of the first converted value before switching and the output of the second converted value after switching, and the sample and hold circuit samples and holds the averaged value. Therefore, it is possible to realize highly accurate digital-to-analog conversion in which the influence of the mismatch of the capacitance ratio that determines the gain of the unit DAC is suppressed.

Further, according to the fourth aspect of the present invention, the switching section inputs the input to two or more capacitive elements for sampling each of the digital signal and the predetermined signal by using the digital signal and the predetermined signal. The switching and control unit controls the conversion operation so as to perform the DA conversion two or more times in a state where the switching unit is activated, and further, the arithmetic unit controls the DA conversion in a state where the switching unit is activated. Since the outputs are added or subtracted, high-precision digital-to-analog conversion can be realized in which the influence of the mismatch of the capacitance ratio determining the gain of the unit DAC is suppressed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a cyclic algorithmic DAC according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a pipeline algorithmic DAC according to an embodiment of the present invention.

FIG. 3 is an explanatory diagram of operation timing of a cyclic algorithmic DAC.

FIG. 4 is an explanatory diagram of operation timing of a pipelined algorithmic DAC.

FIG. 5 is an explanatory diagram of ILN characteristics of an 8-bit cyclic algorithmic DAC according to the present invention.

FIG. 6 shows a conventional cyclic algorithmic DA.
It is a block diagram of C.

FIG. 7: Conventional algorithmic algorithm DA
It is a block diagram of C.

FIG. 8 shows a conventional cyclic algorithm DA.
FIG. 9 is an explanatory diagram of the operation timing of C.

FIG. 9 shows a conventional pipeline algorithm DA.
FIG. 9 is an explanatory diagram of the operation timing of C.

FIG. 10 shows a conventional cyclic algorithm D
FIG. 4 is an explanatory diagram of an example of an INL characteristic of AC.

FIG. 11 shows a conventional cyclic algorithm D
It is explanatory drawing of another INL characteristic example of AC.

[Explanation of symbols]

 15 Unit DAC 25 Sample hold circuit 26 Analog switch 27 Analog switch 28 Analog switch 29 Operational amplifier 35 Subtraction circuit 36 Analog switch 37 Operational amplifier 45 Sample hold circuit 46 Operational amplifier 47 Analog switch 48 Clock generation circuit 150 Operational amplifier 151 Analog switch 152 Analog switch 153 Analog switch 154 Analog switch 155 Analog switch 156 Analog switch 157 Analog switch 158 Analog switch 160 Unit DAC 170 Unit DAC 180 Clock generation circuit 400 Unit DAC1 500 Unit DAC2

Claims (4)

[Claims] 1. A step of switching between input and output of two input signals of a digital signal and another signal on which predetermined processing has been performed, and independently switching and outputting two input signals of "1/2" Multiplying and adding a converted value; and a first converted value before switching and a second converted value after switching.
Averaging and outputting the output of the converted value of the second time. 2. The digital-to-analog conversion method according to claim 1, wherein the average is an addition average or a subtraction average of a first conversion value and a second conversion value. 3. A switching unit for switching between two input signals of a digital signal and another signal on which predetermined processing has been performed and inputting / outputting the two input signals, and independent of two input signals output from the switching unit. And a conversion unit for obtaining a conversion value obtained by multiplying the conversion value by “１ ／”, and an averaging circuit for averaging the outputs of the first conversion value before switching and the second conversion value after switching And a sample-and-hold circuit that samples and holds the averaged value. 4. A digital signal having one or more unit DA converters for inputting a digital signal corresponding to a digital code and a predetermined signal and converting and outputting the added signal.
In the analog converter, the unit DA converter switches between the digital signal and the predetermined signal, two or more capacitance elements, and an input to each capacitance element between the digital signal and the predetermined signal. A switching unit, and a control unit that controls a conversion operation so as to perform DA conversion (digital / analog conversion) two or more times with the switching unit activated, and further comprising a state in which the switching unit is activated. A digital-to-analog converter comprising an arithmetic unit for adding or subtracting the outputs of the DA conversion in the above.