JPH1065016A - Manufacturing method of semiconductor device and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the manufacturing method of a semiconductor device, which prevents the deterioration in the short channel effect by means of detaching a contact region from a gate, without increasing the number of processes. SOLUTION: A first sidewall insulating film 7 such as an undoped CVD SiO2 film is arranged on the sidewall of a gate electrode 3 and a second sidewall insulating film 14 using a CVD SiO2 such as a TEOS(Tetraethoxysilane) film with high flowability on the first sidewall insulating film 7. Then, the contact area is restricted to be small to a required size and valid channel length can be maintained to a prescribed length by forming a second sidewall insulating film. When the method is applied to the semiconductor device of a semiconductor memory, the floating of GND can be reduced since the contact region for GND can be formed on the semiconductor substrate at every memory cell.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to a process for forming a contact with a silicon semiconductor substrate on which a transistor having an LDD structure is formed, and a semiconductor device formed by this process.

[0002]

2. Description of the Related Art High integration of semiconductor devices such as ICs and LSIs is remarkable, and advanced miniaturization technology is required. For example, in a semiconductor device having a MOS structure which is frequently used in a semiconductor memory or the like, a plurality of gate electrodes are juxtaposed in one well, and the space between the gate electrodes is becoming narrower due to miniaturization. For this purpose, a wiring connected to an active region in a semiconductor substrate and connected to another region via an external semiconductor substrate is provided with a contact opening between gate electrodes, that is, a so-called gate self-aligned contact. I use. Conventionally, when the gate self-aligned contact is formed, the upper and side portions of the gate electrode are so arranged that the wiring for contacting the underlying semiconductor substrate does not short the gate electrode of the MOS transistor. Even if it is covered with an insulating film having an etching rate lower than that of an interlayer insulating film formed on a semiconductor substrate and a contact is opened, a gate is formed.
A sufficient thickness of the insulating film is left between the electrode and the wiring. However, in this method, contact opening is not performed.
As the bar etching time is increased, the insulating film on the upper and side portions of the gate electrode decreases, so that there is not much process margin.

As a method for improving the above problem and ensuring that the insulating film remains, a gate electrode is covered with the insulating film, and then an insulating film and a polycrystalline silicon film are deposited on the entire surface. After the insulating film is deposited and melted, there is a method in which the insulating film on the polycrystalline silicon film is removed by an etching method capable of obtaining a selectivity with respect to the polycrystalline silicon, and then the polycrystalline silicon film is removed. By doing so, the insulating film covering the gate electrode is not etched, and the thickness of the interlayer insulating film at the portion where the contact with the semiconductor substrate is formed is considerably larger than that of the insulating film covering the gate electrode. Since the thickness can be reduced, an insulating film having a sufficient thickness can be left around the gate electrode even after some over-etching.

Next, a method for forming a contact region in a silicon semiconductor substrate on which a transistor having an LDD structure has been formed based on the prior art will be described with reference to the manufacturing process sectional views of FIGS. A case where an n-channel MOS transistor is formed in the surface region or the p-well region of the p-type substrate on the silicon semiconductor substrate 1 will be described. A gate oxide film 2 is formed on the surface of the semiconductor substrate 1 by a thermal oxidation method or the like. Thereafter, a polysilicon film 31 is formed on the semiconductor substrate 1.
Then, a silicide film 32 such as molybdenum silicide is laminated, and the laminated body is patterned to form a gate electrode 3 made of the laminated body on the gate oxide film 2. Next, the semiconductor substrate 1 is thermally oxidized to form a post-oxide film 4 on the surface of the semiconductor substrate and the surface of the gate electrode. Next, an impurity such as phosphorus (P) is ion-implanted into the semiconductor substrate 1 using the gate electrode 3 as a mask to form an n ⁻ impurity diffusion region 5.
As the transistor is miniaturized, the internal electric field increases, whereby electrons flowing from the source to the drain are accelerated by a strong electric field, and a large energy is obtained. These are hot carriers and degrade the transistor characteristics. In particular, an n-channel MOS transistor is easily affected by this. To solve this problem, it is effective to reduce the electric field near the drain.

[0005] Therefore impurity concentration by ion implantation of phosphorus is 10 ¹² ~10 ¹³ / cm ³ of about n as shown in FIG ^- formation of the impurity diffusion region 5, it is practiced to moderate the profile in the vicinity of the drain I have. A transistor having this is generally called an LDD transistor. This structure is called an LDD (Lightly Doped Drain) structure, and the n ^- impurity diffusion region 5 is called an LDDn ^- region 5 here.
Since an n-channel MOS transistor is particularly susceptible to the effects of hot carriers, an n ^- impurity diffusion region is formed only in the n-channel MOS transistor and a p-channel MOS transistor is formed.
It is not usually formed in a transistor (FIG. 9A). Next, a silicon nitride (Si ₃ N ₄ ) film 6 is deposited on the entire surface of the semiconductor substrate 1 (FIG. 9B). Next, the silicon nitride film 6 is etched by anisotropic etching such as RIE (Reactive Ion Etching) to remove the silicon nitride film 6 on the semiconductor substrate 1 except for the gate side wall. In this manner, a sidewall insulating film (hereinafter referred to as LDD) is formed on the side wall of the gate electrode 3.
7). Thereafter, an impurity such as arsenic (As) is ion-implanted (implanted) into the n-channel MOS transistor, and an n-type impurity diffusion having a source / drain region of about 10 ¹⁵ / cm ³ is formed in the silicon semiconductor substrate. A region 8 is formed (FIG. 9C).

Thereafter, the CV of the interlayer insulating film is formed on the semiconductor substrate 1.
A non-doped CVD oxide film (SiO ₂ ) formed by a D (Chemical Vapor Deposition) method is deposited to form an interlayer insulating film 15. Next, PEP (Photo Engraving
Process), first, a photoresist film 9 is formed on the semiconductor substrate 1, and is patterned to remove the photoresist film in the contact formation region (FIG. 10).
(A)). Then, using the patterned photoresist film 9 as a mask, a portion of the contact formation region exposed from the mask of the non-doped CVD oxide film 15 is removed by RIE to form a contact opening 10. After forming the contact opening 10, the photoresist film 9 is formed.
Is removed (FIG. 10B). Next, a polysilicon film 11 serving as a wiring is deposited on the semiconductor substrate 1. Mixing implantation is performed on the contact formation region via the polysilicon film 11 to obtain a high impurity concentration (10 ¹⁵ to 10 ¹⁶ /
An n ⁺ impurity diffusion region 12 of cm ³ ) is formed. By this manufacturing process, the impurity diffusion region is shared with the semiconductor substrate 1,
Here, MOS transistors A and B on which wirings are formed are formed.

[0007]

As shown in FIG. 10 (c), the n ⁺ impurity diffusion region 12 by implantation into the contact region is re-diffused by a subsequent heat process to rapidly push the effective channel length of the MOS transistor. The required effective channel length α cannot be obtained by reducing the actual effective channel length α ′
(Α ′ <α) was sometimes shortened. This has the problem of deteriorating the short channel effect, and has been a major obstacle to miniaturization. FIG. 5A shows the state shown in FIG.
FIG. 4 is an enlarged cross-sectional view of a contact region of FIG. As shown in this figure, the heat treatment makes the diameter h of the contact region 12 larger than the required diameter (h '), so that the transistor has an effective channel length α' smaller than a predetermined value. Further, in order not to be affected by the short channel effect, the effective channel length α must be maintained at a value equal to or more than a predetermined value, and for that purpose, the contact diameter of the contact region is made unnecessarily large. I can't do that. For example, FIG. 11 shows a memory cell C constituting a cell array of a semiconductor memory formed on a semiconductor substrate.
And a plan view in which a memory cell D adjacent to the memory cell is formed.

As the miniaturization of the semiconductor device progresses, the size of the transistors A and B also decreases, and furthermore, the distance between the transistors A and B, that is, the sidewalls 7 7 is smaller than the sum of a predetermined effective channel length α that does not deteriorate the short channel effect of both transistors and a necessary minimum contact region diameter h (x ≦ 2α + h).
It becomes necessary. In such a case, conventionally, the transistors A and B of the memory cell C forming the cell array are conventionally used.
No contact region 12 is provided between the memory cells C and D
Had been placed in between. However, in such an arrangement structure, the GND contact is formed rather than forming a GND contact for each memory cell.
Floats easily occur, and electrical stability may be lacking. Also, there was a limit to miniaturization in terms of layout. The present invention has been made in view of such circumstances, and without increasing the number of steps, to provide a method of manufacturing a semiconductor device that reduces the short-channel effect by keeping the contact region away from the gate and miniaturization, Provided is a semiconductor device which is miniaturized by arranging a contact region between transistors while maintaining an effective channel length.

[0009]

SUMMARY OF THE INVENTION The present invention provides a first sidewall insulation film, such as non-doped CVD SiO ₂ film disposed on the side wall of the gate electrode, high reflow resistance over the first sidewall insulating film TEOS Film (TEOS: Tetra Et
hoxy silane) and a _second sidewall insulating film using a CVD SiO ₂ film. That is, the invention of claim 1 includes a step of forming first and second MOS transistors having an LDD structure on a semiconductor substrate, and a step of forming a first sidewall insulating film on a gate sidewall of each of the first and second MOS transistors. Forming a film, forming a second sidewall insulating film on the first sidewall insulating film, and using the second sidewall insulating film as a mask, forming the first and second sidewall insulating films.
Forming a high-concentration impurity diffusion region serving as a contact region in the impurity diffusion regions constituting the first and second MOS transistors by performing mixing implantation between the MOS transistors; Forming a wiring that is electrically connected to the semiconductor device.
According to a second aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect, the second sidewall insulating film has a higher reflow property than the first sidewall insulating film.

[0010] The invention of claim 3 is claim 1 or claim 2.
5. The method for manufacturing a semiconductor device according to item 1, wherein the first sidewall insulating film is formed of a silicon nitride film,
The second sidewall insulating film is formed of a reflowable CVD.
It is characterized by comprising an oxide film. The invention of claim 4 is
The invention according to any one of claims 1 to 3, wherein the first and second MOS transistors constitute cells of a memory cell array formed in a semiconductor memory device. The invention according to claim 5, wherein a semiconductor substrate, a first sidewall insulating film formed on the semiconductor substrate, a gate sidewall, and a reflow from the first sidewall insulating film on the first sidewall insulating film. A first and a second MOS transistor on which a second sidewall insulating film having a large property is formed, and an impurity which is formed on the semiconductor substrate and constitutes the MOS transistor between the first and the second MOS transistor A semiconductor device includes: a contact region formed of a high-concentration impurity diffusion region formed in a diffusion region; and a wiring formed in the semiconductor substrate and electrically connected to the contact region. According to a sixth aspect of the present invention, in the semiconductor device according to the fifth aspect, the first and second M
The OS transistor constitutes a cell of a memory cell array of a semiconductor memory.

[0011] The invention of claim 7 is the invention of claim 5 or claim 6.
3. The semiconductor device according to item 1, wherein the semiconductor memory is S
In the SRAM, one of the first MOS transistor and the second MOS transistor is connected to a high-potential-side power supply voltage, and the other is connected to the first MOS transistor.
A first resistor connected to one of the source / drain regions of the transistor, and a second resistor connected to one of the source / drain regions of the second MOS transistor while the other is connected to the high potential side power supply voltage. One of a resistor and a source / drain region is connected to a first bit line, and the other of the source / drain region is connected to the first resistor and the first MOS.
A third MOS transistor connected to a connection point with the transistor and having a gate connected to a word line; one of a source / drain region connected to a second bit line and the other of the source / drain region connected to the second bit line; And the second M
A fourth MOS transistor connected to a connection point with the OS transistor and having a gate connected to the word line;
A gate of the first MOS transistor is connected to a connection point between the second resistor and the second MOS transistor, and the other of the source / drain regions is connected to a low potential power supply voltage; The gate of the second MOS transistor is connected to a connection point between the first resistor and the first MOS transistor, and the other of the source / drain regions is connected to a low potential power supply voltage. .

By forming the second sidewall insulating film, the contact region can be limited to a required size and the effective channel length can be maintained at a predetermined length.
When this method is applied to a semiconductor device such as a semiconductor memory, a GND contact region can be formed on a semiconductor substrate for each memory cell, so that floating of GND can be reduced.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. First, referring to FIG. 1 to FIG.
An example will be described. FIG. 4 is a cross-sectional view of a transistor formed by the manufacturing steps shown in FIGS. The transistor shown in the figure is formed in the surface region of the semiconductor substrate 1, but it can also be formed in a semiconductor substrate provided with a p-well. To respond to the high integration of semiconductor devices,
In this embodiment, for example, M
A contact opening of an insulating film covering a gate formed between the gates of the OS transistors to electrically connect an internal circuit of the semiconductor substrate and a wiring formed on the semiconductor substrate is formed by a gate. SAC (Self Align Contact) is used. n
An element isolation region is formed in the silicon semiconductor substrate 1 by a LOCOS method or the like, and an n-type MOS
The n-type source / drain regions 5 of the transistors A and B are formed. A gate oxide film 2 is formed in a transistor region on the surface of the semiconductor substrate 1. Gate oxide film 2
A gate electrode 3 made of a polysilicon film 31 and a silicide film 32 such as tungsten silicide is formed on the gate electrode 3. A gate electrode 3 such as a silicon nitride (Si ₃ N ₄ ) film is formed on the silicide film 32. An insulating film 33 for protecting the semiconductor device is formed.

The gate electrode 3 and the insulating film 33 thereon are made of S
It is covered with a post-oxide film 4 made of iO ₂ . The portion of the side wall of the gate electrode 3 which is covered with the post-oxide film 4 includes:
A sidewall insulating film 7 (first sidewall insulating film) made of silicon nitride is formed, and TEOS is formed thereon.
A side wall insulating film 14 (second side wall insulating film) made of a CVD SiO ₂ film having a high reflow property such as a (Tetra Ethoxy Silane) film which flows without melting is formed. The TEOS film is made of silane (Si (OC ₂ H ₅ ) ₄ ) abbreviated as TEOS of 600 to 900.
It is a silicon oxide film obtained by decomposition at a temperature of ° C., and is formed by normal pressure to low pressure CVD (Chemical Vapor Deposition). The gate - gate electrode 3, the insulating film 33, the oxide film 4 and the interlayer insulating film 15 such as SiO ₂ so as to cover the sidewall insulation films 7 and 14 after covering them is formed except for the contact region . In the surface region of the semiconductor substrate 1, an n-type impurity diffusion region 8 which is a source / drain region of the transistors A and B and an LD forming an LDD structure are formed.
Dn ^- region 5 is formed. A contact opening 10 of the interlayer insulating film 15 is formed between the two gate electrodes 3. Inside the contact opening 10, an n ⁺ impurity diffusion region 12 having a high impurity concentration and serving as a contact region is formed in the n-type impurity diffusion region 8 of the semiconductor substrate 1.

A wiring 11 made of polysilicon is formed in the interlayer insulating film 15 on the gate electrode 3 and in the contact opening 10 so as to be connected to the source / drain region 8. The wiring used in this embodiment is not limited to a polysilicon film, but may be a conventionally known wiring material such as a metal wiring such as aluminum, a metal silicide film, or a composite film of polysilicon and silicide. By forming the second sidewall insulating film, the contact region can be limited to a required size, and the effective channel length can be maintained at a predetermined length. Conventionally, as shown in FIG. 5, the contact region 12 is enlarged by heat treatment or the like (h → h).
h ′), as a result, the effective channel length often becomes a value α ′ smaller than the expected value α, but in the present invention, the presence of the second sidewall insulating film 14 makes the contact region a necessary size. (H), the effective channel length α required for the transistor can be maintained.

Next, a manufacturing process of the semiconductor device will be described with reference to FIGS. The figure is a manufacturing process sectional view for forming a contact region on a silicon semiconductor substrate on which a transistor having an LDD structure is formed. First, a gate oxide film 2 is formed on a silicon semiconductor substrate 1 by a thermal oxidation method or the like. After that, a polysilicon film 31 and a silicide film 32 such as molybdenum silicide are laminated on the semiconductor substrate 1,
Further, a silicon nitride (Si ₃ N ₄ ) insulating film 3 is formed thereon.
3 are laminated (FIG. 1A). Then, the laminate is patterned using the photoresist 9 as a mask to form a gate electrode 3 made of the laminate on the gate oxide film 2 (FIG. 1B). Next, the semiconductor substrate 1 is thermally oxidized to form a post-oxide film 4 on the surface of the semiconductor substrate and the surface of the gate electrode. Next, an impurity such as phosphorus (P) is ion-implanted into the semiconductor substrate 1 using the gate electrode 3 as a mask to form an n ^- impurity diffusion region 5 (FIG. 2A). In order to alleviate the electric field in the vicinity of the drain, the n ^- impurity diffusion region 5 having an impurity concentration of about 10 ¹² to 10 ¹³ / cm ³ is formed by ion implantation of phosphorus as described above, and the profile in the vicinity of the drain is moderated. Therefore, this region is referred to as LDDn ^- region 5. Since the n-channel MOS transistor is particularly susceptible to the effects of hot carriers, the LDDn ⁻ region is mainly formed in the n-channel MOS transistor and is not usually formed in the p-channel MOS transistor.

Next, a silicon nitride (Si ₃ N ₄ ) film 6 is deposited on the entire surface of the semiconductor substrate 1 (FIG. 2B). Next, the silicon nitride film 6 is etched by anisotropic etching such as RIE to remove the silicon nitride (Si ₃ N ₄ ) film 6 on the semiconductor substrate 1 except for the gate side wall. Then, a sidewall insulating film 7 (first sidewall insulating film) is formed on the side wall of the gate electrode 3. Thereafter, an impurity such as As is ion-implanted into the silicon semiconductor substrate so as to have an impurity concentration of 1 as a source / drain region of the transistor.
An n-type impurity diffusion region 8 of about 0 ¹⁵ / cm ³ is formed (FIG. 2C). Next, a CVD oxide film 13 having a high reflow property such as a TEOS film is deposited on the semiconductor substrate 1. Then, a photoresist film 9 'having a contact formation region opened is formed on the CVD oxide film 13 (FIG. 3A). Thereafter, anisotropic etching such as RIE is performed using the photoresist film 9 'as a mask. Then, reflow CVD is performed on the side wall of the first side wall insulating film 7.
A second sidewall insulating film made of an oxide film is formed. Thereafter, a non-doped CVD oxide (SiO ₂ ) film is deposited on the semiconductor substrate 1 by a CVD method to form an interlayer insulating film 15.

Next, PEP is performed.
A photoresist film (not shown) is formed thereon, and the photoresist film is patterned to remove the photoresist film in a contact formation region. Then, using the patterned photoresist film 9 as a mask, non-doped CV
A portion of the contact formation region exposed from the mask of the D oxide film 15 is removed to form a contact region 10.
After forming the contact region 10, the photoresist film is removed (FIG. 3B). Next, a polysilicon film 11 serving as a wiring is deposited on the semiconductor substrate 1. Then, mixing implantation is performed on the contact region 10 through the polysilicon film 11 to obtain a high impurity concentration (10 ¹⁵ -10 ¹⁶ / cm 3).
³ ) In this manufacturing step of forming the n ⁺ impurity diffusion region 12, the impurity diffusion region is made common to the semiconductor substrate 1, and the n-channel MOS transistors A and B having the wiring formed in this region are formed.

Next, a second embodiment will be described with reference to FIGS. FIG. 6 is a plan view of a semiconductor substrate on which MOS transistors are formed, and FIG. 7 is a circuit diagram showing a cell structure of a semiconductor memory (SRAM) using the transistors of FIG. This memory cell has four n-channel MOS
It has a transistor and two high resistances. That is, the memory cell includes the first MOS transistor A and the second M transistor.
The OS transistor B, one of the first resistors R1 connected to one of the source / drain regions of the first MOS transistor A, one of which is connected to the high potential power supply voltage, and one of which is connected to the high potential power supply voltage. A second resistor R2 connected to the other of the source / drain regions of the second MOS transistor B and one of the source / drain regions to the first MOS transistor B;
A third MOS transistor Q3 whose source / drain region is connected to a connection point between the first resistor R1 and the first MOS transistor A, and whose gate is connected to the word line WL. And one of the source / drain regions is connected to a second bit line / BL ("/" indicates an inverted signal; the same applies hereinafter), and the other of the source / drain regions is connected to the second resistor R2 and the second resistor R2. A fourth MOS transistor Q4 connected to a connection point with the MOS transistor B and having a gate connected to the word line WL; a gate of the first MOS transistor A has a second resistor R2 and a second MOS transistor The other of the source / drain regions is connected to GND (substrate potential), and the gate of the second MOS transistor B is connected to the first resistor R1 and the first resistor R1. And the other of the source / drain regions (for example, the source) is connected to GND (substrate potential).

This memory cell includes the transistors A and B of FIG. 4 as constituent elements. Transistors A and B
Have a common drain region, this drain region
It is connected to GND by wiring. The wiring and the common drain region are electrically connected via the contact region 12. FIG. 6 is a plan view in which a memory cell C constituting a cell array of a semiconductor memory formed on a semiconductor substrate and a memory cell D adjacent to the memory cell are formed. Since an active region having a predetermined effective channel length which does not deteriorate the short channel effect can be formed between the sidewall insulating films 14 of the transistors A and B, the contact having the minimum necessary contact diameter h can be formed. A region 12 is formed. Conventionally, FIG.
(A) As shown in FIG.
The contact region 12 is not provided between the transistors A and B, and the memory cells C and D are arranged between the memory cells C and D. However, in such an arrangement structure, the floating of the GND is higher than the case where the GND contact is formed for each memory cell. This was likely to occur, and electrical stability was sometimes lacking. Also, there was a limit to miniaturization in terms of layout. According to the present invention, the effective channel length α is maintained at a predetermined value or more so as not to be affected by the short channel effect by using the second sidewall insulating film having a high reflow property. Therefore, while maintaining the required value of the contact diameter in the contact region, GND
A structure that does not cause floating can be adopted, and it is possible to sufficiently cope with miniaturization of a semiconductor device.

Next, a third embodiment will be described with reference to FIG. The figure here relates to a wiring structure in a gate SAC formed in an integrated circuit having a CMOS structure. With the miniaturization of semiconductor devices, the well region where elements in a semiconductor substrate on which a semiconductor integrated circuit is formed is naturally narrowed, and the wiring electrically connected to the elements in the well through contacts is also very small. The use of a gate SAC is necessary because it must be formed. For example, an n-type silicon semiconductor substrate 1 having a resistivity of about 1 to 10 Ωcm is used as the semiconductor substrate.
After forming the element isolation region 16 having the buried structure, the p-well region 17 is formed by using photolithography and ion implantation. Then, a gate oxide film 2 having a thickness of about 50 to 200 angstroms is formed on the semiconductor substrate 1 by thermal oxidation or the like. Next, a polysilicon film 31 having a thickness of about 2000 Å is deposited on the gate oxide film 2. Impurities such as P are ion-implanted and diffused into the polysilicon film 31. Amorphous silicon can be used instead of polycrystalline silicon. Polysilicon film 3
Next, WS with a thickness of about 1000 angstrom
i ₂ film 32 is deposited, thereon 2000 Å - to form an insulating film 33 of about arm thick Si ₃ N _4.

Next, these laminated films are patterned by photolithography and anisotropic etching to form a gate formed of a polysilicon film 31 and a WSi ₂ film 32 on the p-well 17 and the semiconductor substrate 1. The electrode 3 and the insulating film 33 thereon are formed. The surface of the gate electrode 3 and the surface of the insulating film 33 are heat-treated to form a post-oxide film 4. Subsequently, the gate electrode 3 and the insulating film 3 formed on the surface of the semiconductor substrate 1
Silicon nitride (Si)
₃ N ₄₎ to form a film. Then, the silicon nitride film is etched by anisotropic etching such as RIE to form a first sidewall insulating film 7 made of silicon nitride on the laminate. Further, a second sidewall insulating film 14 of a CVD oxide film having a high reflow property such as a TEOS film is formed on the first sidewall insulating film 7. Next, source / drain regions of the MOS transistor are formed. The p-well 17 and the ion-implanted As LDDn ^- n-type source has an area 5 - to form a scan / drain region 8, the semiconductor substrate 1, p-type source of B ions are implanted - scan / A drain region 18 is formed. Next, the surface of the semiconductor substrate 1 including this laminate is covered with an interlayer insulating film 15 such as a non-doped CVD oxide film.

Next, a patterned photoresist film (not shown) is formed on the interlayer insulating film 15, and RIE is performed.
The contact opening 10 is formed in the contact formation region using anisotropic etching such as. The contact opening 10 is close to the gate electrode 3 of the p-well 17 and has a shape over the gate electrode. Next, a polysilicon film 11 is deposited on the interlayer insulating film 15 and in the contact opening 10 and the like, and the source / drain region 8 and the polysilicon film 11 are connected. Polysilicon film 11
Constitute the wiring. Although not shown, a semiconductor device is completed by forming a passivation film on the wiring 11 or further forming a multilayer wiring in the meantime. An n-channel MOS transistor (A) is formed in the p-well, and a p-channel MOS transistor is
A transistor (E) is formed. The miniaturization of the semiconductor device can be promoted while preventing the short channel effect from deteriorating.

[0024]

According to the present invention, the second sidewall insulating film is formed of a CVD oxide film having a high reflow property on the side wall.
By forming the side wall insulating film, the substantial injection region of the mixing implant into the contact region can be kept away from the gate, thereby preventing the short channel effect from deteriorating. In addition, since a contact region can be formed between the gates of adjacent transistors, a contact region can be provided for each memory cell. Therefore, a semiconductor device having a memory cell with a structure in which GND does not float can be obtained.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a manufacturing process of the present invention.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of the present invention.

FIG. 3 is a sectional view illustrating a manufacturing process of the present invention.

FIG. 4 is a cross-sectional view illustrating a manufacturing process of the present invention.

FIG. 5 is a partially enlarged sectional view of FIGS. 4 and 10;

FIG. 6 is a plan view of a semiconductor substrate on which a MOS transistor of the present invention is formed.

FIG. 7 is a circuit diagram showing a cell structure of a semiconductor memory using the transistor of FIG. 6;

FIG. 8 is a cross-sectional view of a semiconductor device of the present invention.

FIG. 9 is a cross-sectional view illustrating a manufacturing process of a conventional semiconductor device.

FIG. 10 is a cross-sectional view illustrating a manufacturing process of a conventional semiconductor device.

FIG. 11 is a plan view of a semiconductor substrate on which a memory cell adjacent to a conventional memory cell is formed.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon semiconductor substrate, 2 ... Gate oxide film, 3 ... Gate electrode, 4 ... Post-oxide film, 5 ...
LDDn ⁻ region (n-type low concentration impurity diffusion region), 6.
An insulating film made of a Si ₃ N ₄ film, 7 a first sidewall insulating film, 8 a source / drain region (n-type impurity diffusion region), 9 a photoresist film, 1
0 ... contact opening, 11 ... wiring (polysilicon film), 12 ... contact area, 13 ...
CVD oxide film with high reflow property, 14 ... second sidewall insulating film, 15 ... interlayer insulating film (non-doped CVD oxide film), 16 ... element isolation region, 1
7 ... p-well, 18 ... source / drain region (p-type impurity diffusion region), 31 ... polysilicon film,
32: silicide film, 33: insulating film.

Claims (7)

[Claims] 1. A step of forming first and second MOS transistors having an LDD structure on a semiconductor substrate, and forming a first sidewall insulating film on gate side walls of the first and second MOS transistors, respectively. Forming a second sidewall insulating film on the first sidewall insulating film; and using the second sidewall insulating film as a mask, between the first and second MOS transistors. Forming a high-concentration impurity diffusion region serving as a contact region in the impurity diffusion region forming the first and second MOS transistors by performing mixing implantation; and electrically connecting the contact region to the semiconductor substrate. Forming a wiring. 2. The method according to claim 1, wherein the second sidewall insulating film has a higher reflow property than the first sidewall insulating film. 3. The method according to claim 1, wherein the first sidewall insulating film is made of a silicon nitride film, and the second sidewall insulating film is made of a reflowable CVD oxide film. 3. The method for manufacturing a semiconductor device according to item 2. 4. The semiconductor device according to claim 1, wherein the first and second MOS transistors form cells of a memory cell array formed in the semiconductor memory device. Production method. 5. A semiconductor substrate, formed on the semiconductor substrate, having a first sidewall insulating film on a gate sidewall and a reflow property higher than the first sidewall insulating film on the first sidewall insulating film. A first and a second MOS transistor on which a large second sidewall insulating film is formed; and a first and a second MOS transistor formed on the semiconductor substrate.
A contact region formed of a high-concentration impurity diffusion region formed in an impurity diffusion region constituting the MOS transistor between the transistors; and a wiring formed on the semiconductor substrate and electrically connected to the contact region. A semiconductor device. 6. The semiconductor device according to claim 5, wherein said first and second MOS transistors form cells of a memory cell array of a semiconductor memory. 7. The semiconductor memory is an SRAM,
In this SRAM, one of the first MOS transistor and the second MOS transistor is connected to a high-potential-side power supply voltage, and the other is connected to one of source / drain regions of the first MOS transistor. A first resistor, one connected to the high potential side power supply voltage, the other connected to one of the source / drain regions of the second MOS transistor, and one of the source / drain regions connected to the first A third MOS transistor connected to one bit line, the other of the source / drain regions connected to a connection point between the first resistor and the first MOS transistor, and a gate connected to a word line; One of the source / drain regions is connected to a second bit line, and the other of the source / drain regions is connected to a connection point between the second resistor and the second MOS transistor. A fourth MOS transistor having a gate connected to a word line, wherein a gate of the first MOS transistor is connected to a connection point between the second resistor and the second MOS transistor; The other of the source / drain regions is connected to a low potential power supply voltage, and the gate of the second MOS transistor is connected to a connection point between the first resistor and the first MOS transistor. 7. The semiconductor device according to claim 5, wherein the other of the drain regions is connected to a low potential power supply voltage.