JPH1055680A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory which can prevent malfunction of a MOS transistor caused by a potential of an input/output node and prevent a leakage current. SOLUTION: A source/drain electrode of an NMOS transistor 101 connected to an input/output node Nio to which a DQ pin 110 is connected is connected to a gate electrode of the NMOS transistor 101 through a capacitor 103. When a negative potential is given to the DQ pin 110 in writing data, it is transmitted to a gate electrode of the NMOS transistor 101 through the capacitor 103, source/drain electrodes and a gate electrode connected to the input/output node Nio of the NMOS transistor 101 and the gate electrode are made the same potential.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having an input / output circuit for inputting and outputting data.

[0002]

2. Description of the Related Art FIG. 7 is a circuit diagram showing a conventional semiconductor memory device 700.

Referring to FIG. 7, in a semiconductor memory device 700, NMOS transistors 101 and 102 cause N
A MOS inverter is configured. Read data / RD is applied to the gate electrode of NMOS transistor 101 from node N1 via inverter 104.
The read data RD is supplied to the gate electrode of the NMOS transistor 102 from the node N2 via the inverter 105. The output node of the NMOS inverter is D
A Q pin (data input / output pin) 110 is connected to output data to the outside and input data from the outside. Hereinafter, the output node of this NMOS inverter is referred to as an input / output node Nio.

FIG. 8 is a timing chart showing an operation at the time of data reading of semiconductor memory device 700 of FIG.

[0005] Referring to FIG.
The operation at the time of data reading will be described. Referring to FIGS. 7 and 8, when nodes N1 and N2 are both at H (logic high) level,
Output data Dout output from the DQ pin (input / output node Nio) 110 to the outside is in a Hi-Z (high impedance) state. When complementary read data RD and / RD of H level and L (logic low) level are input, one of the NMOS transistors 101 and 102 is turned on and the other is turned off, and the DQ pin 110 is turned off.
Output data Dout of H level or L level is output to the outside.

[0006]

However, in semiconductor memory device 700, at the time of data writing, nodes N1 and N1 are not connected.
When both N2 are at H level, the NMOS transistor 1
If both 01 and 102 are off, DQ
Noise is put on the data sent to the pin 110,
For example, when a negative potential of -1 [V] or less is applied to the DQ pin 110, the NMOS transistors 101 and 102
With respect to the potential of each gate electrode (= Z [V])
The potential of the source / drain electrode connected to the Q pin (input / output node Nio) 110 is set to a sub-threshold (sub-th
reshold) potential and the NMOS transistor 10
1, 102 are turned on.

As a result, there is a problem that a leak current flows through the DQ pin 110. Furthermore, NMOS
A current also flows through the substrates of the transistors 101 and 102, causing the substrate potential to float. At this time, holes generated in the substrate destroy data in a memory cell (not shown), that is, an injection failure occurs. There was a problem.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor memory device capable of preventing a malfunction due to a potential of an input / output node and preventing a leak current. I do.

[0009]

According to a first aspect of the present invention, there is provided a semiconductor memory device, wherein one of the source / drain electrodes is the first.
And a first MOS transistor having the other source / drain electrode connected to the input / output node, one source / drain electrode connected to the second power supply, and the other source / drain electrode connected to the input / output node. A second MOS transistor connected to the output node; and, when data is input from the input / output node, the potential of the input / output node is changed to the first MOS transistor.
A potential supply means for supplying a voltage to the gate electrode of the transistor.

In a semiconductor memory device according to a second aspect of the present invention, a first MOS transistor having one source / drain electrode connected to a first power supply and the other source / drain electrode connected to an input / output node. And a second MOS transistor having one source / drain electrode connected to the second power supply and the other source / drain electrode connected to the input / output node, and one electrode connected to the gate electrode of the first MOS transistor. And a capacitor whose other electrode is connected to the input / output node.

According to a third aspect of the present invention, in a semiconductor memory device, a first MOS transistor having one source / drain electrode connected to a first power supply and the other source / drain electrode connected to an input / output node. A second MOS transistor having one source / drain electrode connected to the second power supply and the other source / drain electrode connected to the input / output node; and a capacitor having one electrode connected to the input / output node. And switching means for connecting the gate electrode of the first MOS transistor and the other electrode of the capacitor when data is input from the input / output node.

According to a fourth aspect of the present invention, in the semiconductor memory device according to the third aspect, when the data is output from the input / output node, the switching means includes a gate electrode of the first MOS transistor and a capacitor. Is separated from the other electrode.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

In the drawings, the same reference numerals indicate the same or corresponding parts. (1) First Embodiment FIG. 1 shows a semiconductor memory device 100 according to a first embodiment of the present invention.
FIG.

Referring to FIG. 1, semiconductor memory device 100
Includes NMOS transistors 101 and 102, a capacitor 103, and inverters 104 and 105.

The NMOS transistors 101 and 102 are
It constitutes an NMOS inverter. That is, NMO
One source / drain electrode of S transistor 101 is connected to a Vcc power supply for supplying power supply voltage Vcc, and the other source / drain electrode is connected to input / output node Nio for inputting / outputting data. One source / drain electrode of the NMOS transistor 102 is grounded,
The other source / drain electrode is connected to the input / output node Nio. Read data / RD is input to the input node of inverter 104 from node N 1, and its output node is connected to the gate electrode of NMOS transistor 101. Read data RD is input to the input node of inverter 105 from node N 2, and the output node is connected to the gate electrode of NMOS transistor 102. A DQ pin 110 for inputting / outputting data to / from the outside is connected to the input / output node Nio. One electrode of the capacitor 103 is an NMOS transistor 101
Is connected to the input / output node Nio.

FIG. 2 is a timing chart showing a state at the time of data reading of semiconductor memory device 100 of FIG.

Referring to FIG. 2, data of semiconductor memory device 100 will be described.
The operation at the time of data reading will be described. Referring to FIGS. 1 and 2, when nodes N1 and N2 are both at H level, output data Dout output from DQ pin 110 connected to input / output node Nio is in a Hi-Z state. Node N1, N
2, complementary read data RD of H level and L level,
/ RD is input, the NMOS transistor 10
1 and 102 are turned on and the other is turned off, and the output data Do output from the DQ pin 110 is output.
ut is at the H level when the NMOS transistor 101 is on, and at the L level when the NMOS transistor 102 is on.

After data output, nodes N1 and N2 are both at H level again, and DQ pin 110 is in the Hi-Z state.

Next, at the time of data writing, H-level or L-level data is sent to the DQ pin 110 from outside. On the other hand, nodes N1 and N2 both attain an H level,
The NMOS transistors 101 and 102 are turned off, and data is sent to an input buffer circuit (not shown).

At this time, it is assumed that noise or the like is included in data transmitted from the outside via the DQ pin 110, and data having a negative potential of, for example, -1 [V] or less is input instantaneously.

FIG. 3 is a circuit diagram of the semiconductor memory device 100 shown in FIG.
6 is a timing chart showing a state when a negative potential is applied to the Q pin 110 during data writing.

Referring to FIG. 3, a negative potential applied to DQ pin 110 is applied to node N3 to which the gate electrode of NMOS transistor 101 is connected via capacitor 103.
Given to. Therefore, the potential of the gate electrode of the NMOS transistor 101 is a negative potential equal to the data input to the DQ pin 110, so that the NMOS transistor 101 is not turned on.

As described above, in the semiconductor memory device according to the first embodiment of the present invention, even if a negative potential is input as noise from DQ pin 110, the negative potential is applied to the gate electrode of NMOS transistor 101 via the capacitor. Given the potential of
Since the gate electrode and the source / drain electrode connected to the DQ pin 110 have the same potential, it is possible to prevent an erroneous ON state and prevent a leak current.

As a result, it is possible to prevent the occurrence of an injection failure in which a current flows through the substrate to generate holes and destroy data in the memory cells.

(2) Second Embodiment FIG. 4 shows a semiconductor memory device 400 according to a second embodiment of the present invention.
FIG.

Referring to FIG. 4, semiconductor memory device 400
In the semiconductor memory device 100 of the first embodiment shown in FIG. 1, a transfer gate 401 is further provided.

Referring to FIG. 4, transfer gate 40
1 is connected between one electrode of the capacitor 103 and the gate electrode (node N3) of the NMOS transistor 101.

Here, the transfer gate 401 is composed of a PMOS transistor 401 which is turned on / off in response to a clock signal φ, and an NMOS transistor which is turned on / off in response to a clock signal / φ complementary to the clock signal φ. Have been. Clock signals φ and / φ are generated based on, for example, output enable signal / OE externally input or a delay signal of write designation signal / W, and turn on transfer gate 401 when data is input / output. / Off.

FIG. 5 is a timing chart showing a state of semiconductor memory device 400 of FIG.

The operation of the semiconductor memory device 400 will be described with reference to FIG. Referring to FIGS. 4 and 5, at the time of data reading, transfer gate 40 responds to clock signals φ and / φ.
1 is turned off.

As a result, the NMOS transistor 101
Is separated from one of the electrodes of the capacitor 103, so that data can be transmitted without losing the operation speed.

Conversely, when writing data, clock signals φ,
The transfer gate 401 is turned on in response to / φ, and a circuit similar to the semiconductor memory device 100 of the first embodiment is obtained.

Therefore, as described in the first embodiment, even if a negative potential is applied to DQ pin 110, the potential is transmitted to the gate electrode of NMOS transistor 101 via capacitor 103, and And the source / drain electrode connected to the DQ pin 110 have the same potential, so that malfunction of the NMOS transistor 101 can be prevented, and leakage current can be prevented.

As described above, in the semiconductor memory device according to the second embodiment of the present invention, in addition to the effect of the semiconductor memory device according to the first embodiment, the operation speed loss caused by the capacitor 103 during data reading is eliminated. It becomes possible.

(3) Third Embodiment FIG. 6 shows a semiconductor memory device 600 according to a third embodiment of the present invention.
FIG.

Referring to FIG. 6, semiconductor memory device 600
In the semiconductor memory device 100 according to the first embodiment shown in FIG. 1, the capacitor 103 is replaced with an NMOS transistor 601, and a potential detection circuit 602 for controlling the NMOS transistor 601 is further provided.

One source / drain electrode of the NMOS transistor 601 is connected to the gate electrode of the NMOS transistor 101, and the other source / drain electrode is connected to the input / output node Nio. The input node of the potential detection circuit 602 is connected to the input / output node Nio, and the output node is connected to the gate electrode of the NMOS transistor 601.

The potential detection circuit 602 includes an input / output node Ni
When detecting that the potential o, that is, the potential of the data input from the DQ pin 110 is a negative potential (less than or equal to 0 [V]), it outputs an H-level control signal to the gate electrode of the NMOS transistor 601. Thereby, NMOS
The transistor 601 is turned on, and the DQ pin 110
Is transmitted to the gate electrode of the NMOS transistor 101, and the source / drain electrode connected to the input / output node Nio of the NMOS transistor 101 and the gate electrode have the same potential. Therefore, NM
The OS transistor 101 is not turned on.

The potential detection circuit 602 operates only when the potential of the DQ pin 110 becomes negative.
Since a high level control signal is applied to the gate electrode to turn it on, the normal operation such as data reading is the same as in the first and second embodiments.

As described above, the semiconductor memory device according to the third embodiment of the present invention can obtain the same effects as the semiconductor memory device according to the first embodiment.

[0042]

According to the semiconductor memory device of the first aspect of the present invention, it is possible to prevent malfunction of the first MOS transistor due to the potential of the input / output node and prevent leakage current. .

According to the semiconductor memory device of the second aspect of the present invention, when data is input from the input / output node, the input / output node is connected to the gate electrode of the first MOS transistor via the capacitor. Since a negative potential is applied, it is possible to prevent a malfunction of the first MOS transistor caused by the potential of the input / output node and to prevent a leak current.

According to the semiconductor memory device of the third aspect of the present invention, when data is input from the input / output node, the gate electrode of the first MOS transistor is connected to the input / output node by the switching means. Are connected to each other via a capacitor, and the potential of the input / output node is applied to the gate electrode of the first MOS transistor. Therefore, when data is input from the input / output node, the capacitor is disconnected. The potential of the input / output node is applied to the gate electrode of the first MOS transistor via
Malfunction of the first MOS transistor caused by the potential of the input / output node can be prevented, and leak current can be prevented.

According to the semiconductor memory device of the fourth aspect of the present invention, in addition to the effect of the semiconductor memory device of the third aspect, when data is output from the input / output node, the data is output by the switching means. Since the gate electrode of one MOS transistor is separated from the input / output node, it is possible to eliminate a loss in operating speed due to the capacitor.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing a state at the time of data reading of the semiconductor memory device of FIG. 1;

FIG. 3 is a timing chart showing a state when a negative potential is applied to a DQ pin of the semiconductor memory device of FIG. 1 during data writing.

FIG. 4 is a circuit diagram showing a semiconductor memory device according to a second embodiment of the present invention.

FIG. 5 is a timing chart showing a state of the semiconductor memory device of FIG. 4;

FIG. 6 is a circuit diagram showing a semiconductor memory device according to a third embodiment of the present invention.

FIG. 7 is a circuit diagram showing a conventional semiconductor memory device.

8 is a timing chart showing a state at the time of data reading of the semiconductor memory device of FIG. 7;

[Explanation of symbols]

100, 400, 600 Semiconductor storage device, 101, 1
02,601 NMOS transistor, 103 capacitor, 401 transfer gate, 602 potential detection circuit.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Ryuji Omachi 2-6-2 Otemachi, Chiyoda-ku, Tokyo Mitsui Electric Engineering Co., Ltd. (72) Inventor Tatsuharu Kobayashi 2-6-Otemachi, Chiyoda-ku, Tokyo 2. Mitsubishi Electric Engineering Co., Ltd. (72) Inventor Yoshinori Murakami 2-6-1 Otemachi, Chiyoda-ku, Tokyo Mitsubishi Electric Engineering Co., Ltd.

Claims (4)

[Claims] 1. A semiconductor memory device for inputting / outputting data from an input / output node, wherein one source / drain electrode is connected to a first power supply,
A first MOS transistor having the other source / drain electrode connected to the input / output node, and one source / drain electrode connected to a second power supply;
A second MOS transistor having the other source / drain electrode connected to the input / output node; and, when data is input from the input / output node, the potential of the input / output node is changed to a gate electrode of the first MOS transistor. And a potential supply means for supplying the potential to the semiconductor memory device. 2. A semiconductor memory device for inputting / outputting data from an input / output node, wherein one source / drain electrode is connected to a first power supply,
A first MOS transistor having the other source / drain electrode connected to the input / output node, and one source / drain electrode connected to a second power supply;
A second MOS transistor having the other source / drain electrode connected to the input / output node; and a capacitor having one electrode connected to the gate electrode of the first MOS transistor and the other electrode connected to the input / output node. And a semiconductor storage device comprising: 3. A semiconductor memory device for inputting / outputting data from an input / output node, wherein one source / drain electrode is connected to a first power supply,
A first MOS transistor having the other source / drain electrode connected to the input / output node, and one source / drain electrode connected to a second power supply;
A second MOS transistor having the other source / drain electrode connected to the input / output node; a capacitor having one electrode connected to the input / output node; A switching device for connecting a gate electrode of one MOS transistor to the other electrode of the capacitor; 4. The semiconductor memory according to claim 3, wherein said switching means disconnects a gate electrode of said first MOS transistor and another electrode of said capacitor when data is output from said input / output node. apparatus.