JPH1051480A - Protocol processing system for gateway equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize high speed protocol processing. SOLUTION: A protocol identification section 3 outputs a protocol act signal PT when a reception frame is a frame of a protocol of a processing object. A header check section 7 and a check sum calculation check section 10 in a protocol processing section 6 check validity of a reception frame when the protocol act signal PT is received. Simultaneously, a routing table retrieval section 11 decides a transfer destination of the reception frame. Thus, the protocol processing of the gateway equipment is conducted in parallel and processed by the hardware, then the processing time for the protocol processing is remarkably reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gateway device for connecting networks, and more particularly, to a protocol processing method of a gateway device for performing protocol processing of a received frame.

[0002]

2. Description of the Related Art With the recent increase in the speed of information communication, there is a demand for an improvement in processing speed in a gateway device.
The protocol process in the gateway device includes a process of checking the received frame for some validity and a routing process for finding a transfer destination of the frame. In general, these processes are performed by software by a single CPU processor, whereby serial processing occurs.

[0003]

As described above, in the conventional gateway device, since a protocol processing including a plurality of processes is performed by software processing by a single CPU processor, it takes a long processing time, and the entire gateway device takes a long time. There is a problem that the processing speed is reduced. The present invention has been made to solve the above problems, and has as its object to provide a protocol processing method capable of realizing high-speed protocol processing.

[0004]

According to the present invention, as described in claim 1, whether a frame received from a network is a frame of a protocol to be processed is determined. A protocol identification unit that outputs a protocol act signal; and a protocol processing unit that, when the protocol act signal is input, checks the validity of the received frame and determines a transfer destination of the received frame. Form 1,
3). Also, as described in claim 2, a protocol identification unit that identifies whether a frame received from the network is a frame of a protocol to be processed, and outputs a protocol act signal when the frame is a frame of a protocol to be processed, A protocol processing unit that checks the validity of the received frame, determines the transfer destination of the received frame, and outputs a result of the validity check when a protocol act signal is input (second embodiment) 4).

According to a third aspect of the present invention, the protocol identifying unit compares a header holding register for holding a header of the received frame with a predetermined value for identifying the protocol and the header held by the register. And a comparison circuit that outputs a protocol act signal when they match (1, 2, and 3 of the embodiment). According to a fourth aspect of the present invention, the protocol identification unit includes a comparison circuit that constantly compares a received frame with a predetermined value for identifying a protocol, and a comparison match result obtained by the comparison circuit. (Fourth embodiment).

According to a fifth aspect of the present invention, the protocol processing unit checks the validity of the header when a header holding register for holding the header of the received frame and a protocol act signal are input. When a protocol act signal is input, a header check unit consisting of a check unit that outputs a comparison result signal and a header checksum of a received frame are calculated by comparing the valid value for the header held in the register. A checksum calculation check unit that compares the checksum value in the received frame with the calculated value and outputs a comparison result signal; and when a protocol act signal is input, a transfer corresponding to the destination address of the received frame. A routine that calculates destination information and outputs a table error signal if the destination address is not registered. It is made of a grayed table search portion (1 embodiment). Further, as described in claim 6, when the protocol act signal is input, the protocol processing unit compares the received frame with a valid value for checking the validity of the header of the received frame at the timing of the header. Calculates the checksum of the header of the received frame with the header checker that outputs the comparison result signal, and compares the calculated value with the checksum value in the received frame when the protocol act signal is input. A checksum calculation check unit that outputs a signal, and when a protocol act signal is input, obtains transfer destination information corresponding to a destination address of a received frame, and, if the destination address is not registered, a table error signal. Output from the routing table search unit, the header check unit and the checksum calculation check unit. Compare result signal, and is made of a flip-flop circuit for holding a table error signal from the routing table search unit (third embodiment).

Further, the protocol processing unit has a header holding register for holding the header of the received frame and a valid value and a register for checking the validity of the header. A header checker comprising a checker for comparing the headers and outputting a comparison result signal, calculates a checksum of the header of the received frame, compares the checksum value in the received frame with the calculated value, and outputs a comparison result signal. A routing table search unit for obtaining transfer destination information corresponding to the destination address of the received frame, and outputting a table error signal when the destination address is not registered, and a header check. Unit and a comparison result signal from the checksum calculation check unit, and a routing table search unit It is made of a gate circuit which outputs when La table error signal protocol act signal is input (2 embodiment). According to another aspect of the present invention, the protocol processing unit compares the received frame with a valid value for checking the validity of the header of the received frame at the timing of the header, and outputs a comparison result signal. Checksum calculation section that calculates the checksum of the header of the received frame, compares the checksum value in the received frame with the calculated value, and outputs a comparison result signal, and corresponds to the destination address of the received frame. A routing table search unit for obtaining transfer destination information to be transmitted and outputting a table error signal when a destination address is not registered, a comparison result signal from a header check unit and a checksum calculation check unit, and a routing table search unit And a flip-flop circuit holding a table error signal from the It is made of a gate circuit for outputting when the protocol activation signal comparison result signal and the table error signal from the drop circuit is input (fourth embodiment).

[0008]

FIG. 1 is a block diagram of a protocol processing device in a gateway device according to a first embodiment of the present invention, and FIG. 2 is a timing chart for explaining the operation of the protocol processing device. . The network interface unit 1 receives a frame from a network (not shown). In a network to which the gateway device is connected, frames of a plurality of different protocols are transferred, so it is necessary to identify whether or not the frame is a protocol of a processing target of the gateway device. The protocol identification unit 3 in the protocol processing device 2 performs such identification.

In this embodiment, an IP (Internet Protocol) is used as a frame to be processed by the gateway device.
A description will be given using a protocol frame as an example. FIG. 3 is a diagram showing a header information portion in the IP frame format of the Ethernet (Ethernet) format, and the size in the horizontal direction is 32 bits. H0 to H8 are header numbers.

In FIG. 3, reference numeral 101 denotes a field in which a physical layer destination address (Destination Address) is stored, and 102 denotes a physical layer source address (Source Address).
), 103 is a field for storing a protocol identifier, 104 is a field for storing an IP version (Version), 105 is a field for storing a header length, and 106 is a field for storing a header length.
Is a field storing a service type (Type of Service); 107 is a field storing a total length (Total Length) including a header and IP frame data;
A field 8 stores an identification number (Identification).

[0011] In addition, 109 is a fragment (Fragment O).
ffset) is stored in the field 110, and TTL (Ti
me to Live), a field 111 stores a protocol number (Protocol), 112
Is a field in which a header checksum is stored, and 113 is an IP source address (Source).
Address) is a field in which an IP destination address (Destination Address) is stored.

In this embodiment, received frames are sequentially transferred from the network interface unit 1 to the memory 17 as shown in FIG. The interface unit 1 outputs a transfer indicator as shown in FIG. 2B indicating that data is being transferred on the data bus 18. Then, when the transfer indicator becomes “1”, the timing generation unit 15 starts counting the number of data in the frame, and
Generates an act signal for taking in a necessary header from a frame flowing above.

First, the timing generator 15
An act signal T0 as shown in (e) is generated. When the act signal T0 is input, the header holding register 4-1 in the protocol identifying unit 3 holds the transfer data from the interface unit 1 at the rising edge of the clock shown in FIG. As a result, the header H0 is held as shown in FIG.

Next, the timing generation unit 15
An act signal T1 as shown in (g) is generated. When the act signal T1 is input, the header holding register 4-2 holds the transfer data from the interface unit 1 at the rise of the clock. As a result, the header H1 is held as shown in FIG. Similarly, the timing generator 1
5 generates an act signal T3 as shown in FIG.
When the act signal T3 is input, the header holding register 4
-3 holds the transfer data from the interface unit 1 at the rise of the clock. As a result, the header H3 is held as shown in FIG.

The comparison circuit 5 includes a header holding register 4-
The upper 16 bits (that is, the physical layer destination address) of the header H0 and the header H1 held in the steps 1 and 4-2 are compared with a predetermined value, and the header held in the header holding register 4-3. The upper 16 bits (protocol identifier) of H3 are compared with a predetermined value. If these comparison results do not match, a protocol error signal PE is output.

The output of the protocol error signal PE indicates that the gateway apparatus has received a frame of a protocol not to be processed. Therefore,
The transfer control means (not shown) outputs the protocol error signal PE.
Is received, the received frame written in the memory 17 is discarded by overwriting data or the like, and processing for stopping transfer to the device is performed.

If all the comparison results match, the comparison circuit 5 sets the protocol act signal PT to "1" as shown in FIG. 2 (q). Protocol act signal P
The output of T indicates that the gateway apparatus has received the frame of the protocol to be processed. When this protocol act signal PT is output, I
The P-protocol processing unit 6 is activated and performs the IP protocol processing.

The IP protocol processing unit 6 checks the header H3 and thereafter, as described later. But,
The protocol act signal PT is the header H3 of FIG.
Is delayed by two clocks. Therefore, the shift register 16 shifts the transfer data from the network interface unit 1 by two clocks as shown in FIG. 2D, and uses it as input data to the IP protocol processing unit 6. Thus, the phases of the header H3 and the protocol act signal PT match.

The timing generator 15 generates an act signal CT3 as shown in FIG. When the act signal CT3 is input, the header holding register 8-1 in the header check unit 7 holds the transfer data from the shift register 16 at the rise of the clock. As a result, FIG.
As shown in (l), the header H3 is held. When the protocol act signal PT is “1”, the check unit 9-1 outputs the header H3 held in the header holding register 8-1.
Is compared with its legal value. Then, the checking unit 9-1 outputs “0” as a comparison result signal when they match, and outputs “1” when they do not match.

When the protocol act signal PT is "1", the check unit 9-2 compares the header length portion of the header H3 held in the header holding register 8-1 with its valid value. The check unit 9-2 outputs “0” as a comparison result signal when they match, and outputs “1” when they do not match. When the protocol act signal PT is “1”, the checking unit 9-3 compares the service type portion of the header H3 held in the header holding register 8-1 with its valid value, and outputs a comparison result signal. Is similarly output.

Subsequently, the timing generator 15 includes act signals CT4 and CT (not shown), like the act signal CT3.
5, the act signals CT6, CT7, and CT8 shown in FIG. 2 (m), FIG. 2 (n), and FIG.
Generated at timing 8. Note that the above act signal C
T3 to CT8 are the protocol identifying units 3 for the above-described reason.
Needless to say, it is shifted by two clocks with respect to the act signals T0, T1, and T3.

Header holding registers 8-2 to 8 (not shown)
-5 and the header holding register 8-6 output the act signal CT.
When 4 to CT8 are input, the transfer data from the shift register 16 is held at the rising edge of the clock. As a result, the headers H4 to H8 are held in the header holding registers 8-2 to 8-6, respectively. The check unit 9-4 (not shown) outputs the protocol act signal PT
Is "1", the entire length of the header H4 held in the header holding register 8-2 is compared with its valid value, and a comparison result signal is output.

Similarly, a check unit 9-5 (not shown)
When the protocol act signal PT is "1", the identification number portion of the header H4 held in the header holding register 8-2 is compared with its valid value, and a comparison result signal is output. When the protocol act signal PT is “1”, the check unit 9-6 (not shown) outputs the header holding register 8-
Then, it compares the fragment portion of the header H5 held in No. 3 with its valid value and outputs a comparison result signal.

When the protocol act signal PT is "1", the check unit 9-7 (not shown) compares the TTL portion of the header H5 held in the header holding register 8-3 with its valid value. , And outputs a comparison result signal. The check unit 9-8 (not shown) outputs the protocol act signal P
When T is "1", the protocol number portion of the header H5 held in the header holding register 8-3 is compared with its valid value, and a comparison result signal is output.

When the protocol act signal PT is "1", the check unit 9-9, not shown, compares the header checksum portion of the header H6 held in the header holding register 8-4 with its valid value. Then, a comparison result signal is output. When the protocol act signal PT is “1”, the check unit 9-10 (not shown) stores the IP source address of the header H6 held in the header holding register 8-4 and the header H6 held in the header holding register 8-5. It compares the IP source address portion of the header H7 with its valid value and outputs a comparison result signal.

When the protocol act signal PT is "1", the check section 9-11 holds the IP destination address and the header holding register 8-6 of the header H7 held in the header holding register 8-5. It compares the IP destination address portion of the header H8 with its valid value and outputs a comparison result signal. Thus, the header checking unit 7 checks the validity of the header from the IP version to the IP destination address.

Next, the checksum calculation check section 10
Calculates the checksum value of the headers H0 to H8 excluding the checksum value, and compares the calculated value with the checksum value in the header H6. FIG. 4 shows a block diagram of the checksum calculation check unit 10. FIG. 2 (m) from the timing generator 15
Is received, the header holding register 31 in the checksum calculation check unit 10 holds the transfer data Din from the shift register 16 at the rise of the clock. This allows
The header H6 is held.

Upon receiving the checksum act signal CAT as shown in FIG. 2 (r) from the timing generator 15, the checksum calculator 32 calculates the checksums of the headers H0 to H8 excluding the checksum value in the header H6. I do. When the protocol act signal PT is “1”, the comparison circuit 33 compares the checksum value in the header H6 held in the header holding register 31 with the checksum value calculated by the checksum calculation unit 32. Then, the comparison circuit 33
Outputs "0" as a comparison result signal when they match, and outputs "1" when they do not match.

On the other hand, the routing table search unit 11
Outputs the transfer destination information corresponding to the IP transmission destination address by searching a correspondence table between the IP transmission destination address and the port number in the device. FIG. 5 is a block diagram of the routing table search unit 11. The routing table 34 stores an IP destination address indicating a transfer destination of a received frame and transfer destination information including a port number indicating to which port in the gateway the frame is to be output. ing.

When an act signal similar to the act signal CT7 in FIG. 2 (n) and an act signal similar to the act signal CT8 in FIG. 2 (o) are input from the timing generator 15, the header holding register 35 Holds the transfer data Din from the shift register 16. As a result, the headers H7 and H8 are held.

That is, the table search sequencer 36
When the routing table search act signal RAT and the protocol act signal PT as shown in FIG. 2 (s) are received from the timing generation unit 15, the routing table 34 is searched based on the IP destination address held in the header holding register 35, The transfer destination information corresponding to the IP destination address is read. At this time, if the transmission destination address is not registered in the routing table 34, a table error signal whose value is “1” is output to the OR circuit 12.

Next, the OR circuit 12 takes the logical sum of the comparison result signal from the header check unit 7, the comparison result signal from the checksum calculation check unit 10, and the table error signal from the routing table search unit 11. . The comparison result signal of the header check unit 7 becomes “1” when the header is not a valid value, and the checksum calculation check unit 1
The comparison result signal of 0 becomes “1” when the calculated value of the checksum is not equal to the checksum value in the header, and the table error signal of the routing table search unit 11 is I
It becomes “1” when the P destination address is not registered in the routing table.

Therefore, when there is any error in the header of the received frame, the header error signal HE output from the OR circuit 12 becomes "1". When the header error signal HE becomes "1", the transfer control means performs a process of discarding the received frame as in the case of the protocol error signal PE.

On the other hand, when the transfer destination information D as shown in FIG.
The transfer destination information D is stored in the memory 17 by being added to the header of the received frame or stored at an address uniquely corresponding to the address where the received frame is stored. Finally, the timing generation unit 15
Outputs a protocol processing end signal EN as shown in FIG. 2 (t) indicating that the protocol processing has ended. Upon receiving the protocol processing end signal EN, the transfer control means recognizes that the protocol processing has ended, and shifts to the next processing.

As described above, in the present embodiment, since each component is configured by hardware, comparison of the header can be performed by one.
This can be performed by a clock, and the routing process for obtaining the transfer destination information can be processed in a short time.

Embodiment 2 FIG. 6 is a block diagram of a protocol processing device of a gateway device according to another embodiment of the present invention, and FIG. 7 is a timing chart for explaining the operation of the protocol processing device. 6, the same components as those in FIG. 1 are denoted by the same reference numerals. In FIG. 7, the same or similar signals as those in FIG. 2 are denoted by the same reference numerals ((a), (b),...). Unless otherwise described, the signals are the same.

The timing generation unit 15a in the protocol processing unit 2a transmits the signals to the protocol identification unit 3 in the same manner as in the timing generation unit 15 of FIG.
Are output as act signals T0, T1, and T3. The operation of the protocol identification unit 3 is exactly the same as in FIG. Next, the header check unit 7a, the checksum calculation check unit 10a, and the routing table search unit 11a in the IP protocol processing unit 6a do not wait for the end of the protocol identification unit 3 (that is, the output of the protocol act signal PT). The same processing as in FIG. 1 is performed according to only the act signal from the timing generation unit 15a.

Therefore, the processes of the header check unit 7a, the checksum calculation check unit 10a, and the routing table search unit 11a are performed in parallel with the operation of the protocol identification unit 3, so that the IP protocol as in the first embodiment is used. There is no need to shift the input data to the processing unit by two clocks by the shift register, and it is not necessary to provide a shift register.

As a result, the act signal CT3 shown in FIG. 7 (k) and the act signals CT4 and CT (not shown) output from the timing generator 15a to the IP protocol processor 6a.
7, the act signal CT6 in FIG. 7 (m), the act signal CT7 in FIG. 7 (n), the act signal CT8 in FIG.
The checksum act signal CAT (r) and the routing table search act signal RAT in FIG. 7 (s) do not need to be shifted by two clocks.

Except for performing processing irrespective of the protocol act signal PT, the header check unit 7a, the checksum calculation check unit 10a, and the routing table search unit 11
The operation of a is the same as in FIG. Next, the AND circuit 13 serving as a gate circuit calculates the logical product of the output signal of the OR circuit 12 and the protocol act signal PT. Therefore, if the protocol act signal PT is "1", the output result of the OR circuit 12 is output as it is, and if it is "0", it is not output. As a result, the same header error signal HE as in FIG.

Finally, the timing generation unit 15a
A protocol processing end signal EN as shown in (t) is output. Thus, the same protocol processing as in the first embodiment can be realized, and the protocol identification unit 3 and the header check unit 7
a, the processing of the checksum calculation check unit 10a and the processing of the routing table search unit 11a are performed in parallel, so that the protocol processing can be performed at a higher speed than in the first embodiment.

Embodiment 3 FIG. 8 is a block diagram of a protocol processing device of a gateway device showing another embodiment of the present invention, and the same components as those in FIG. 1 are denoted by the same reference numerals. In this embodiment, since the timing of each unit is the same as that of the first embodiment, the description will be made with reference to the timing chart of FIG.

First, the operations of the protocol identification unit 3, the timing generation unit 15, and the shift register 16 in the protocol processing device 2b are exactly the same as those in FIG. Next, upon receiving the protocol act signal PT, the IP protocol processing unit 6b starts up and performs the IP protocol processing.

The timing generator 15 generates an act signal CT3 as shown in FIG. Header check section 7
The check unit 9b-1 in the protocol act signal P
When T is "1" and the act signal CT3 is input, the portion corresponding to the IP version in the transfer data (the header H3 at this timing) from the shift register 16 is compared with its valid value. And the check part 9
b-1 outputs "0" as a comparison result signal when they match, and outputs "1" when they do not match.

When the protocol act signal PT is "1" and the act signal CT3 is input, the check section 9b-2 compares the header length portion in the transfer data from the shift register 16 with its legitimate value. Then, a comparison result signal is similarly output. When the protocol act signal PT is “1” and the act signal CT3 is input, the check unit 9b-3 compares the service type portion in the transfer data from the shift register 16 with its valid value, The comparison result signal is output.

Subsequently, the timing generation unit 15 generates act signals CT4 and CT5 (not shown), as shown in FIG.
(N), the act signals CT6 and CT7 shown in FIG.
CT8 is generated at the timing of headers H4 to H8, respectively. When the protocol act signal PT is “1” and the act signal CT4 is input, the check unit 9b-4 (not shown) determines the entire length of the transfer data from the shift register 16 (the header H4 at this timing). A comparison result signal is output in comparison with the valid value.

The check unit 9b-5 (not shown) determines that the protocol act signal PT is "1" and the act signal CT4
Is input, the identification number portion in the transfer data from the shift register 16 is compared with its valid value, and a comparison result signal is output. Check part 9b-6 not shown
When the protocol act signal PT is "1" and the act signal CT5 is input, the fragment portion in the transfer data (the header H5 at this timing) from the shift register 16 is compared with its valid value. And outputs a comparison result signal.

The check unit 9b-7 (not shown) determines that the protocol act signal PT is "1" and the act signal CT5
Is input, the TTL portion in the transfer data from the shift register 16 is compared with its valid value, and a comparison result signal is output. The check unit 9b-8 (not shown)
When the protocol act signal PT is “1” and the act signal CT5 is inputted, the protocol number portion in the transfer data from the shift register 16 is compared with its valid value, and a comparison result signal is output.

The check unit 9b-9 (not shown) determines that the protocol act signal PT is "1" and the act signal CT6
Is input, the header checksum in the transfer data is compared with its valid value, and a comparison result signal is output. When the protocol act signal PT is “1” and the act signal CT 6 is input, the check unit 9 b-10 (not shown) outputs the I in the transfer data from the shift register 16.
The P source address portion is compared with its valid value, and when the act signal CT7 is input, the IP source address portion in the transfer data is also compared with its valid value, and the comparison result signal is output. Output.

When the protocol act signal PT is "1" and the act signal CT7 is input, the check unit 9b-10 sets the IP destination address portion in the transfer data from the shift register 16 to its valid value. Compare with
When the act signal CT8 is input, the portion of the IP destination address in the transfer data is similarly compared with its valid value, and a comparison result signal is output.

The operations of the checksum calculation check unit 10 and the routing table search unit 11 are exactly the same as those in FIG. Next, the flip-flop 14 outputs the comparison result signal from the header check unit 7b, the comparison result signal from the checksum calculation check unit 10, and the table error signal from the routing table search unit 11 to the timing generation unit 15.
The protocol processing end signal E shown in FIG.
Each of them is held at the timing of N.

The OR circuit 12a calculates the logical sum of these signals. Thus, the same header error signal HE as in FIG. 1 is output from the OR circuit 12a. In this way, the same protocol processing as in the first embodiment can be realized, and it is not necessary to provide a header holding register in the header check unit 7b, so that the amount of hardware can be reduced.

Embodiment 4 FIG. 9 is a block diagram of a protocol processing device of a gateway device showing another embodiment of the present invention, and FIG. 10 is a timing chart for explaining the operation of the protocol processing device. 9, the same components as those in FIGS. 1, 6, and 8 are denoted by the same reference numerals. In FIG. 10, the same signals as those in FIG. 7 are denoted by the same reference numerals ((a), (b),...).

The timing generator 15b in the protocol processor 2c is the same as the timing generator 15a in FIG. 6 except that an act signal shown in FIG. The comparison circuit 5a in the protocol identification unit 3a is configured as shown in FIG.
The transfer data from the interface unit 1 shown in (c) is constantly compared with a predetermined value. This value contains the header H
There is a predetermined value for the physical layer destination address of 0, a value for the same address in the header H1, and a predetermined value for the protocol identifier in the header H3.

The comparison circuit 5a outputs "0" as a comparison result signal when these three types of comparison results match, and outputs "1" when they do not match. Subsequently, the flip-flop 19 outputs the three comparison result signals output from the comparison circuit 5a to the act signal T0 in FIG. 10E, the act signal T1 in FIG. 10G, and the act signal T3 in FIG. At the timing of.

The OR circuit 20 takes the logical sum of the output signals of the flip-flop 19. And flip-flop 2
1 is output from the timing generator 15b in FIG.
The output signal of the OR circuit 20 is held at the timing of the act signal (w). Here, when the gateway device receives the frame of the protocol to be processed, the OR circuit 2
The output of “0” becomes “0”, and when a frame of a protocol not to be processed is received, the output of the OR circuit 20 becomes “1”.

Therefore, the same protocol error signal PE as in the first to third embodiments is output from the positive output of the flip-flop 21, and the protocol act signal PT is output from its inverted output. Become. Next, the header check unit 7c of the IP protocol processing unit 6c
The operation of the (checking units 9c-1 to 9c-11) is the same as that of the header checking unit 7b in FIG. 8 except that processing is performed irrespective of the protocol act signal PT.

The checksum calculation check section 10
a, the operation of the routing table search unit 11a is the same as in FIG. 6, the operations of the flip-flop 14 and the OR circuit 12a are the same as in FIG. 8, and the operation of the AND circuit 13 is
Is the same as Thus, the processes of the protocol identification unit 3a, the header check unit 7c, the checksum calculation check unit 10a, and the routing table search unit 11a can be performed in parallel, as in the second embodiment. Furthermore, since it is not necessary to provide a header holding register in the protocol identifying unit 3a, the amount of hardware can be reduced. (Since the flip-flops 19 and 21 are for holding 1 bit, the header holding register for holding 32 bits is required.) In comparison, the amount of hardware is small).

In the above embodiment, a case has been described where the gateway device processes only frames of the IP protocol. However, an actual gateway device processes a plurality of protocols. Therefore, in such a case, by providing a plurality of protocol processing units, performing identification according to each protocol in the protocol identification unit, and outputting a protocol act signal for each protocol to the corresponding protocol processing unit, Processing according to a plurality of protocols can be performed.

[0060]

According to the present invention, by providing a protocol identification unit and a protocol processing unit as described in claim 1, the protocol processing of the gateway device can be parallelized, and the processing can be performed by hardware. Therefore, the processing time of the protocol processing can be significantly reduced. As a result, it is possible to greatly contribute to speeding up the processing of the gateway device.

In addition, the protocol processing unit starts processing without waiting for a protocol act signal from the protocol identification unit, so that the protocol identification unit and the protocol processing unit operate in parallel. Therefore, the processing time can be further reduced.

Further, by configuring the protocol identification unit from the header holding register and the comparison circuit, the protocol identification unit can be easily realized. In addition, since the protocol identification unit includes the comparison circuit and the flip-flop circuit, it is not necessary to provide a header holding register, and the amount of hardware can be reduced.

Further, by configuring the protocol processing unit from a header check unit, a checksum calculation check unit, and a routing table search unit, the protocol processing unit can be easily realized. Further, as described in claim 6, the protocol processing unit is composed of a header check unit, a checksum calculation check unit, a routing table search unit, and a flip-flop circuit, so that it is necessary to provide a header holding register in the header check unit. And the amount of hardware can be reduced.

Further, as described in claim 7, the protocol processing unit comprises a header check unit, a checksum calculation check unit, a routing table search unit, and a gate circuit, and operates in parallel with the protocol identification unit. The protocol processing unit can be easily realized.
In addition, the protocol processing unit includes a header check unit, a checksum calculation check unit, a routing table search unit, a flip-flop circuit, and a gate circuit, and operates in parallel with the protocol identification unit. It is possible to easily realize a protocol processing unit that performs the processing. Also, since it is not necessary to provide a header holding register in the header check unit, the amount of hardware can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a protocol processing device in a gateway device according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the protocol processing device of FIG. 1;

FIG. 3 is a diagram showing an IP frame format.

FIG. 4 is a block diagram of a checksum calculation check unit.

FIG. 5 shows a block diagram of a routing table search unit.

FIG. 6 is a block diagram of a protocol processing device of a gateway device according to another embodiment of the present invention.

FIG. 7 is a timing chart for explaining the operation of the protocol processing device of FIG. 6;

FIG. 8 is a block diagram of a protocol processing device of a gateway device showing another embodiment of the present invention.

FIG. 9 is a block diagram of a protocol processing device of a gateway device according to another embodiment of the present invention.

FIG. 10 is a timing chart for explaining the operation of the protocol processing device of FIG. 9;

[Explanation of symbols]

2, 2a to 2c: protocol processing device, 3, 3a: protocol identification unit, 4-1 to 4-3, 8-1, 8-6: header holding register, 5, 5a: comparison circuit, 6, 6a to 6c
... IP protocol processing unit, 7, 7a-7c ... Header check unit, 9-1-9-3, 9-11, 9a-1-9a-
3, 9a-11, 9b-1 to 9b-3, 9b-11, 9
c-1 to 9c-3, 9c-11: check unit, 10: checksum calculation check unit, 11: routing table search unit, 13: AND circuit, 14: flip-flop, 21: flip-flop.

Claims (8)

[Claims] 1. A protocol identifying unit for identifying whether a frame received from a network is a frame of a protocol to be processed, and outputting a protocol act signal when the frame is of a protocol to be processed, and a protocol act signal being inputted. A protocol processing unit for checking the validity of the received frame and determining a destination of the received frame when the received frame is received. 2. A protocol identifying unit for identifying whether a frame received from a network is a frame of a protocol to be processed, and outputting a protocol act signal when the frame is of a protocol to be processed, and validity of the received frame. And a protocol processing unit for determining the transfer destination of the received frame and outputting the result of the validity check when a protocol act signal is input. 3. The protocol processing method for a gateway device according to claim 1, wherein said protocol identification unit includes a header holding register for holding a header of a received frame, a predetermined value for identifying a protocol, and A protocol processing method for a gateway device, comprising: a comparison circuit that compares headers held in registers and outputs a protocol act signal when they match. 4. The protocol processing method for a gateway device according to claim 1, wherein the protocol identification unit constantly compares a received frame with a predetermined value for identifying a protocol, and a comparison circuit using the comparison circuit. A protocol processing method for a gateway device, comprising: a flip-flop circuit for holding a match result and outputting the result as a protocol act signal. 5. The protocol processing method for a gateway device according to claim 1, wherein said protocol processing unit includes a header holding register for holding a header of a received frame, and a header holding register for receiving a protocol act signal. A header check unit including a check unit that outputs a comparison result signal by comparing a valid value for checking validity with the header held in the register and a checksum of a header of the received frame are calculated, and the protocol act is performed. A checksum calculation check unit that compares a checksum value in a received frame with the calculated value when a signal is input, and outputs a comparison result signal; The transfer destination information corresponding to the destination address is obtained, and the destination address is registered. And a routing table search unit for outputting a table error signal if not present. 6. The protocol processing method for a gateway device according to claim 1, wherein, when a protocol act signal is input, the protocol processing unit receives a valid value for checking validity of a header of the received frame and a received frame. And a header check unit that outputs a comparison result signal, calculates a checksum of the header of the received frame, and when a protocol act signal is input, checksum values in the received frame and the A checksum calculation check unit that compares the calculated values and outputs a comparison result signal; and, when a protocol act signal is input, obtains transfer destination information corresponding to a destination address of a received frame, and obtains the destination address. Routing table search unit that outputs a table error signal if is not registered And a flip-flop circuit for holding a comparison result signal from a header check unit and a checksum calculation check unit, and a table error signal from a routing table search unit. . 7. The protocol processing method for a gateway device according to claim 2, wherein the protocol processing unit includes a header holding register for holding a header of the received frame, and a valid value for checking the validity of the header. The header held by the register is compared, a header check unit including a check unit that outputs a comparison result signal, and a checksum of the header of the received frame are calculated. A checksum calculation check unit for comparing and outputting a comparison result signal, and obtaining transfer destination information corresponding to a destination address of a received frame, and outputting a table error signal when the destination address is not registered. Routing table search section, header check section and checksum calculation check section Comparison result signal, and the protocol processing method of the gateway device, characterized in that is made of a gate circuit for outputting when the table error signal from the routing table search unit protocol act signal is input. 8. The protocol processing method of the gateway device according to claim 2, wherein the protocol processing unit compares the received frame with a valid value for checking the validity of the header of the received frame at the timing of the header, A header check unit that outputs a comparison result signal; a checksum calculation check unit that calculates a checksum of the header of the received frame, compares the checksum value in the received frame with the calculated value, and outputs a comparison result signal. A routing table search unit that obtains transfer destination information corresponding to a destination address of a received frame and outputs a table error signal when the destination address is not registered; and a header check unit and a checksum calculation check unit. Comparison result signal and table from routing table search unit A gateway device comprising: a flip-flop circuit that holds an error signal; and a gate circuit that outputs a comparison result signal and a table error signal from the flip-flop circuit when a protocol act signal is input. Protocol processing method.