JPH10505467A - Multilayer sacrificial etching method for purging silicon substrate - Google Patents

Abstract

An accelerometer is made by forming a proof mass and at least one associated hinge in a silicon substrate by various etching and bonding processes. In this process, an oxide support layer (40), (42), (44) is formed under the proof mass by ion implantation, and the two complementary proof masses (62) and the substrate structure are bonded to each other. Bonding and integration, removing the oxide support layers (40), (42), (44) and the proof mass (62) is supported by hinges (67) inside the body of silicon material (12). So that In the bonding and etching back process, the wafer (532) is processed and cut in half, and the two halves are bonded again so that the complementary halves are joined to form a completed accelerometer. During the preparation of the composite wafer (900), the wafer (900) is mounted on a centrifuge (902) and spins off the etchant. The centrifuge (902) consists of a bar-shaped platform (904) that is rotated by a motor (906). The two compartments (910) are lined with filter paper (912), (914), (916), receive the composite wafer (900), and are covered by the lid (918).

Description

DETAILED DESCRIPTION OF THE INVENTION Multilayer sacrificial etching method for purging silicon substrate Field of the invention The present invention relates generally to a method for creating microstructures in a semiconductor substrate for use in precision measuring instruments such as accelerometers. More particularly, the present invention relates to a method of depositing an epitaxial silicon layer on an oxidized substrate wafer such that the former is converted to the latter via a bonding and etchback process. Background of the Invention Accelerometers have been used in various applications. For example, accelerometers are used to help determine the acceleration or deceleration of a ship or aircraft, and to monitor the forces being applied to equipment or devices such as cars and buses. Typical prior art accelerometers use a pendulum-type transducer, and the acceleration is detected by observing the displacement of the pendulum. A force is applied to the pendulum, typically by an electromagnetic current, forcing the pendulum back to its initial rest position. By measuring the current required to generate this field, the acceleration can be determined. The product of acceleration and mass is a force. More modern accelerometers rely on a movable electrode located between two fixed electrodes. This is described in Suzuki, Tuchitani, "Semiconductor Capacitance-type Accelerometer with PWM Electrostatic Servo Technique," Sensors and Actuator, A1-A23 (1990) 316-319, and European Patent Application No. EP03338688A1. The invention of Suzuki et al. Uses a silicon movable electrode located at the end of a cantilever attached to a silicon base. The movable electrode is spaced from two fixed electrodes located on either side of the movable electrode. The device is sandwiched inside a glass structure and is electrically connected to a monitor circuit. The circuit is generally shown in a paper and a patent application by Suzuki et al. Additional circuitry is described in US Pat. No. 5,142,921 to Stewart et al. And US Pat. No. 3,877,313 to Ferriss et al. U.S. Pat. No. 4,679,434 to Stewart discloses a sandwich accelerometer in which a semiconductor substrate is sandwiched between two non-conductive plates. In this configuration, hinges having crossed blades are used to provide the desired degree of bending and strength. The accelerometer is maintained near the signal processing circuit by placing it in a hybrid package with the signal processing circuit. Both the stewart accelerometer and the Suzuki accelerometer require a complex assembly of three parts. Proper alignment and orientation of the fixed electrode with the movable electrode is required for proper operation of the device. This alignment and assembly is more difficult due to the physical size of the device. Movable electrodes are necessarily extremely thin and very vulnerable to bending. Even more delicate are the Suzuki cantilevers or stewart hinges, both of which can be easily broken or bent by rough handling. With the Su zuki cantilever or stewart hinge, it is difficult to keep both sides of the intermediate substrate clean while aligning the three layers, and it can also hold down or hold the intermediate wafer of a stack of three wafers. difficult. An even greater danger is the formation of microcracks inside the crystal structure of the cantilever member. These microcracks may remain undetected during assembly, but may fail during operation, begin to make erroneous measurements as the cracks spread, and / or reduce conductivity. There is. The crossed blade design by stewart provides lateral stability of the movable electrode, which allows the movable electrode to bend by a vertical axis. This reduces the sensitivity to anomalies caused by torsional or rotational forces. The crossed blades by stewart use grooves with sharp ends terminating in the silicon crystal structure. This sharp termination can give stress points where microcracks can begin to occur. Suzuki's design uses a single cantilever located near the middle of a movable electrode. This is also known as proofmass. The central point of this contact gives the Suzuki device a torsional instability that can result from an electrostatic negative spring. As a result, erroneous measurements can occur as the movable electrode approaches both fixed electrodes as a result of rotation (twist). In the higher range, the negative spring ratio easily exceeds the torsion spring ratio of the hinge. This configuration also provides a place where microcracks begin to lead to device degradation. In U.S. Pat. No. 5,115,291 to Stroke, a four-step assembly process is used to place a movable electrode on a cantilever between two fixed electrodes. In the invention by Stroke, the movable electrode is doped separately from the cantilever. The Stroke invention also uses cantilevers located on all four sides of the movable electrode to maintain the position and orientation of the movable electrode. Suzuki and other similar devices use a pyrex outer edge on which the fixed electrodes are placed. Pyrex glass or other types of glass are not exceptional thermal conductors and are two orders of magnitude smaller than silicon. Pyrex, however, can support a temperature qradient through the thickness of the glass. The semiconductor material forming the fixed electrode has much better heat transfer properties than the Pyrex on which it is installed. The thermal conductivity coefficient mismatch between silicon and Pyrex is approximately 10 percent. This difference is sufficient to cause Pyrex-to-silicon stress and buckling of the structure when the temperature fluctuates. Therefore, there is a need to create a solid state measurement device such as an accelerometer that can be manufactured with minimal handling and reliability. The design and construction of such accelerometers should be such that exposed stress points are reduced to prevent or avoid microcrack formation. Summary of the Invention The present invention therefore relates to a process for forming a solid state device, such as an accelerometer, that uses a minimal number of mechanical assembly operations. Further, the process of the present invention forms a solid state accelerometer without exposed stress points from which microcracks originate. The present invention also provides a design that can be manufactured with uniformity and reliability. Further, the present invention provides an accelerometer design that minimizes thermal distortion. In a preferred embodiment, the present invention provides a method of forming a solid state measurement device, such as an accelerometer, where the proof mass is located at the end of a hinge. The proof mass is surrounded at the top and bottom by fixed electrodes, whereby the movement of this proof mass can be detected by external circuits. The present invention can be formed using a single silicon wafer, thereby reducing the effects of wafer-to-wafer variations in the fixed electrode and the proof mass itself. The present invention is preferably formed before the proof mass and hinge are physically separated from the underlying silicon wafer, whereby the hinge and proof mass are stressed during handling during manufacture. And to prevent other damage. In another embodiment, the topography of the proof mass and the hinge is such that the hinge is located along one side of the proof mass and close to the edge of the proof mass. The hinge, also known as flexure, is preferably slotted and has an aperture for selective etching to undercut the hinge at the time required to define the perimeter of the proof mass. give. In yet another embodiment of the invention, mass is added to the proof mass by forming complementary proof mass sections in different portions of the wafer (eg, the left and right halves). These complementary parts are then combined to form a single proof mass having a greater mass than otherwise available to form a proof mass. The hinge that attaches the proof mass to the wafer is removed in some embodiments of the invention, thereby preventing seams from forming along the length of the hinge and ensuring a uniform crystal structure of the hinge. . This also keeps the hinge very close to the (middle plane) midplane of the proof mass. Finally, the present invention is a method of forming a multi-layer sacrificial etched silicon substrate, comprising the steps of providing a silicon substrate having multiple buried oxide layers; Etching the layer; suspending the silicon substrate over a rotating fixture at a predetermined distance from its focal point; rotating the fixture about the focal point to define a predetermined position; Achieving centrifugal force. BRIEF DESCRIPTION OF THE FIGURES FIG. 1 is a side cross-sectional view of an embodiment of the present invention during wafer processing. 2 to 5 are further side sectional views of the embodiment of FIG. 1 during successive steps of wafer fabrication. FIG. 6 is a side cross-sectional view of the embodiment of the present invention formed from FIG. 1, showing the complementary top and bottom assembly of this embodiment. FIG. 7 is a cross-sectional side view of another embodiment of the present invention during manufacture. 8 to 15 are further side cross-sectional views of the wafer of FIG. 7 during successive steps of wafer fabrication. FIG. 16 is a side cross-sectional view of the embodiment of FIGS. 7-15, showing the complementary top and bottom assembly of this embodiment of the present invention. FIG. 17 is a side cross-sectional view of the embodiment shown in FIG. 16 after the complementary portions have been mated. FIG. 18 is a side cross-sectional view of the embodiment shown in FIG. 17 after wire bonding. FIG. 19 is a top view of the diffusion layer mask according to the embodiment of the present invention. FIG. 20 is a top view of an etching mask for providing a damping groove in the embodiment of FIG. FIG. 21 is a top view of the diffusion mask for the embodiment of FIG. FIG. 22 is a top view of the hinge etching mask for the embodiment of FIG. FIG. 23 is a top view of the overlay of the mask of FIGS. FIG. 24 is a composite view of the embodiment of FIG. 19, showing how the damping grooves intersect the bottom surface of the proof mass. FIGS. 25-28 illustrate side cross-sectional views of embodiments that undergo successive steps of another alternative method of wafer fabrication. FIGS. 29 and 30 illustrate where the complementary upper and lower wafers are bonded and then etched. FIG. 31 is an illustration of the wafer of FIG. 30, but after being cut in half and bonded to obtain a substantially completed proof mass still embedded in the oxide. FIG. 32 shows a state in which the oxide is removed by etching, and the completed proof mass and the hinge are intact. Figures 33-42 illustrate the first steps of another embodiment of the bonding and etching back process using a selective epitaxial process. FIG. 43 illustrates a process in yet another embodiment. FIGS. 44-47 illustrate modifications by a non-selective epitaxial process to those shown in FIGS. 33-42. FIG. 48 is an exploded view showing an exemplary centrifuqe for removing an etchant from a multi-layer composite wafer. Description of the preferred embodiment A first embodiment of the present invention is shown in FIGS. The following description of the preferred embodiment of FIGS. 1-6 describes the doping, flatness, and various dimensions of the structure. These particular characteristics may vary according to the teachings of the present invention. As a result of variations, the size of the elements can vary and the electrical properties can vary, but small variations do not hinder the operation of the device. Referring first to FIG. 1, there is shown a silicon wafer 12 doped with a P-type material, preferably boron, to achieve a resistance of 1 ohm-cm. 9. The silicon wafer 12 preferably has a diameter of approximately 100 mm; Polished to a flatness of 0 μm. Has a surface finish of 3 nm RMS. Oxide layers 14, 16 are formed on the front and back surfaces of silicon wafer 12. Oxide layers 14, 16 are grown to a thickness sufficient for subsequent diffusion or implantation mask operations. Referring now to FIG. 2, the oxide layer 14 is etched to provide openings for N-type diffusions and alignment marks placed on the backside of the silicon wafer 12. The surface oxide layer 14 is conceptually divided into three oxide areas 18, 20, 22. In effect, this is one continuous oxide film with small openings created by etching in it. N-type dopants 28, 30 such as phosphorus are then diffused through the openings 24, 26 into the oxide layer. Referring to FIG. 3, the oxide layers 16, 18, 20, 22 are removed or etched away, and new oxide implant mask segments 32, 34 are added to the N-type doping areas 28, 30. Is located above. Oxygen 36 is implanted to form a buried layer beneath the surface of the silicon wafer 12 adjacent the N-type portions 28, 30 by a process commercially known by the abbreviation SIMOX. The silicon wafer 12 is then heated and annealed with silicon to form a buried oxide layer from the implanted oxygen. Oxide layers 40, 42, 44 are located below the surface of silicon wafer 12 and are covered by silicon layers 46, 48, 50. N-type doped areas 28, 30 separate the oxide layers 44 and 42, 42 and 40, respectively. The exact thickness of the silicon material 46, 48, 50 is not critical, but the silicon layer must be continuous and crystalline and must be thick enough to withstand pre-epitaxial cleaning and surface oxide removal. Must be provided so that an additional layer of silicon can be epitaxially grown on the silicon wafer 12. According to FIG. 5, further epitaxial layers 60, 62, 64 are grown on the buried oxide layers 40, 42, 44. The epitaxial silicon layer is doped with a P-type dopant such as boron. This doping of the P-type material gradually decreases in a direction from the oxide layer toward the surface of the silicon wafer 12 and is used in selectively forming the non-etched regions 67 and 62 around the periphery. For the next N-type doping. The trench 68 and the guard trench 72 shown in FIGS. 5 and 6 are electrochemically etched. The opening 66 adjacent to the hinge 67 is also electrochemically etched. Next, a blanket P-type diffusion layer covering the surface and the hinge is placed (deposited, deposited), returning the etch protected slightly N-type region to P-type. Etching of the opening 66 is accomplished from the side, and the doping change assists in controlling the etching zone. Compared to FIG. 6, the wafers of FIGS. 1 to 5 are cut in half. The surface of the wafer is hydrated using a mixture of water, hydrogen peroxide, and ammonia to form silanol groups on the surface. Once hydrated, the complementary surfaces of the wafer are aligned, aligned and bonded. For bonding, the wafers must be positioned with their clean, flat surfaces facing each other. Whatever the presence of particles, the adhesion of the complementary wafer portions is prevented. Once assembled, the composite wafer is annealed at approximately 1100 ° C. for 5 hours. During the annealing process, oxygen and hydrogen are removed from the composite wafer. This 5 hour annealing is sufficient to make the surface P-type layer deeper than the N-type diffusion zone 30 adjacent the hinge 67. Wire bond vias 84 are anisotropically etched to form ramped walls 78,80. A shadow masked Ti Au layer (not shown) is typically placed as an electrical contact surface, thereby bonding wires 74 to it. Wire 74 is then bonded to point 82 in the cavity. Next, the oxide layer 42 is etched away, leaving openings 70, 71 surrounding the proof mass 62. Prior to etching, the composite wafer is cut into chips and centrifuged to remove the etchant. Alternatively, the composite wafer is purged (purged) with deionized water and T-butyl alcohol, followed by freeze-drying in vacuum to complete. In the centrifugation process, as shown in the expanded general view of FIG. 48, a composite wafer 900 is attached to a centrifuge 902 to remove the etchant. Be spun. In one embodiment, the centrifuge 902 comprises a platform 904 having the shape of a disk or flat bar rotated by a motor 906. In practice, the hardware for this rotation can be configured to operate on, for example, a photoresist spinner as is known in the art. The motor 906 has a spindle 908 chucked or connected to a platform 904 that rotates at its center of gravity for balanced rotation. A compartment 910 is provided at a fixed radius away from the center of gravity / center of rotation. In the bar-shaped platform 904 as shown in FIG. 48, there are two compartments, but it is of course possible to provide more compartments on a bar-shaped or circular platform. Each compartment 910 is sized to receive a composite wafer 910 therein. Each compartment 910 is lined with a liquid absorbing material such as filter paper, as shown separately in FIG. For filter paper, there are four side portions 912, a top portion 914, and a bottom portion 916. As the centrifugal separator 902 spins, the liquid corrosive (etchant) flows toward the outer periphery, driven by centrifugal force, and is absorbed by the filter paper portions 912, 914, 916. Each wafer 900 is secured in a respective compartment 910 by a lid 918 to prevent the composite wafer 900 from being ejected from the platform 904 when g is a large spin. Lid 918 is itself attached to platform 902 using screws 920 or similar fastening means. To ensure that the etchant is properly dried and purged (removed), the composite wafer 900 should be oriented inside each compartment 910 as shown. That is, the proof mass 922 should be oriented according to the outline of the proof mass 922 shown by the dashed line, thereby positioning the flexure or hinge 924 closer to the center of rotation. Also, ideally, the center of gravity of the proof mass 922 is aligned with the radius of the rotating platform 902. From empirical data, the radius is typically in the range of 30 mm to 50 mm for a composite wafer having dimensions of, for example, 3 mm x 3 mm. Such an arrangement minimizes proof mass bending and distortion during the centrifugation process. Empirically, the composite wafer 900 must withstand 1000 g to 3000 g to satisfactorily remove the etchant completely from corner to corner. If the proof mass 922 is not properly oriented and mounted in the compartment 910, such a force will surely damage the delicate hinge 924, at best. Platform 902 may rotate at a speed between 5000 RPM and 7000 RPM. Upon completion of the centrifugation process, the purged (removed) composite wafer 900 is removed from the compartment 910 and separated from the filter paper 912, 914, 916. The composite wafer 900 is now ready for the next process step. Further, the composite wafer may be subjected to a purging process using water from which ions have been removed and T-butyl alcohol, and may be freeze-dried in a vacuum. In the embodiment shown, the oxide regions 44, 40, 76 each have approximately 0. 5 microns thick. The spaces 70 and 71 are also formed by selectively etching away the oxide 42 present in these areas, so that the heights are approximately 0.1 mm. The capacitor, which is 5 microns and is formed by the guard ring frame and the surrounding fixed electrodes, has a dielectric constant of 4 in the embodiment shown. The capacitance of the substrate is reduced by region 72. The proof mass is approximately 70 microns in total thickness, since each section 62 is approximately 35 microns thick before bonding the complementary surfaces together. Similarly, the distance between the oxide layers 40, 76 is approximately 70 microns. Another embodiment of the structure shown in FIGS. 1-6 is illustrated in FIGS. A similar starting material, a P-type doped silicon substrate 112, has oxide layers 114, 116 formed on the front and back surfaces, which are used to form diffusions or implant masks. It has a sufficient thickness. This starting material is the same as in the example described above. Referring to FIG. 8, an oxide layer 114 is patterned for N-type ion implantation or diffusion, and alignment marks are patterned on the back or bottom oxide layer 116 of the substrate 112. The pattern corresponds to the openings 124, 126, 226, 330 through which phosphorus or other N-type material is diffused. After diffusion, the oxide layers 122, 118, 120, 122, 220 are removed (stripped) and a new oxide layer is placed. This new oxide layer is approximately 5000 angstroms thick. A thin layer of CVD silicon nitride, approximately 500 Å deep, is then placed over the surface of this new oxide layer. Referring to FIG. 9, a portion of the silicon nitride layer is effectively removed, leaving a patterned layer of silicon nitride at locations 234, 238, 240. This patterned nitride layer overlies the patterned oxide layers 232,236. The exposed areas of the substrate are then etched using a potassium hydroxide silicon etch to a depth of approximately 35 micrometers, as shown in FIG. This forms a channel 242 between the patterned oxide sections 232, 236. Walls 244, 246 with (111) bevels representing the crystalline plane surround the channel 242. Referring to FIG. 11, the oxide layer is then removed and potassium hydroxide is used to etch the newly exposed surface and channel 242 by another 2 micrometers. The remaining structure consists of a nitride layer in a separate section 234, 238, 240 just above the oxide layer sections 232, 236. These layers are on top of the N-type doped material previously diffused or implanted into the substrate. This N-type material is located at 128, 230, 330. The N-type material at location 330 is not protected by the nitride layer and is partially etched by the potassium hydroxide etch. The nitride and oxide layers are then removed and a CVD oxide layer is deposited and patterned, as shown in FIG. This layer has a thickness of approximately 8000 angstroms and is located at 260,262,264,266. A photoresist mask is applied, preferably by a spray linography process, to avoid the step coverage problem. The deposited oxide avoids surface steps that can occur if thermal growth oxidation is used due to the difference in oxidation rates between the substrate and the N-type doped regions 128, 130, 230, 330. Used for The oxide layer is then used to mask the implanted oxide layer. The implanted oxide layer is annealed at approximately 1300 ° C. for 5 hours and lies below the substrate surface where no CVD oxide is present. This is shown in FIG. 13 as oxide layers 270, 272, 278, 274, 276. Referring to FIGS. 14 and 15, the oxide used as a mask during the ion implantation is removed and a P-type epitaxial layer is grown on the substrate. This epitaxial layer has a thickness of approximately 35 micrometers, and has a thickness of 0.1 mm. It has a conductivity of 1 Ω · cm. This epitaxial growth fills channel 242. The epitaxial layer on the substrate is then wrapped or scraped until the oxide layer begins to appear. The oxide layer first appears at tab 280. The epitaxial growth layer is thus divided into several different sections 292,294,296,298. Here, the wafer is sliced in half, the complementary wafer surfaces are brought together, hydrated and bonded to form a composite wafer. The composite wafer is annealed at approximately 1100 ° C. for 5 hours. In the embodiment shown in FIG. 16, the top portion of the composite wafer is shown such that the proof mass section 295 is complementary to the proof mass section 294. Only one hinge 296 is formed in this embodiment to avoid an adhesive line or seam located in the center of the hinge. Once assembled, as shown in FIG. 17, the proof mass sections 294, 295 are joined to form a single proof mass 294, 295 surrounded by a channel 272. Hinge 296 is sandwiched between oxide layers 278,279. N-doped material 130, 131 is adjacent to the edge of pendulum arm 296. As shown in FIG. 18, the oxide layer 275 is removed and the wire bond vias 178 are etched inside the composite substrate. This allows wire 174 to be bonded at point 182 to an extension of P-type material 184 of pendulum arm 296. The oxide layer 274 prevents stray flow of current through the composite substrate. 17 and 18, the N-type materials 302, 304 further provide electrical insulation, as do the oxide layers 276, 277. The oxide layer 272 is removed by selective etching, and the gap is then cleaned using a centrifuge to remove the etchant. Alternatively, the gap is freeze-dried with T-butanol after purging. A shadow mask is used and a layer of metal is placed over surface 184 to allow wire bonds 182 to adhere to the substrate. Both of the embodiments described so far result in a pendulum having a precisely defined configuration located between two silicon electrodes. These electrodes are precisely separated from the pendulum by a predetermined amount. By using one wafer and slicing the wafer in half to form the complementary top and bottom of the device, the distance between the pendulum and each electrode on the side of the pendulum is kept uniform. In addition, unwanted variations that occur when another wafer is used can be reduced or eliminated. Alignment and assembly of the accelerometer according to the invention is achieved by both parts of the wafer being solid, thus minimizing all stress on the wafer and avoiding damage to the pendulum as a result of handling. . The present invention also significantly reduces or avoids the possibility that unwanted contaminants such as dirt and dust may be included inside the accelerometer. This provides uniform operation, minimizes failures, and extends the useful life of the device. The present invention also avoids the sharp edges of the cantilevers shown in the Stewart patent. Preferably, the design of the embodiment of FIGS. 1-6 is modified to use a hinge without seams. The oxide layer remaining on the substrate around the proof mass is used to block the stray current flowing in the substrate. An additional trench guard 72 shown in FIG. 6 can be used to reduce the capacitance from one to the other from the fixed electrode. The capacitance from the fixed electrode to the guard is also reduced as compared to a solid guard dielectric. Referring to FIGS. 19-24, a preferred topography of the device is shown. The illustrated topography uses a square proof mass. A rectangular proof mass whose length extending from the hinge is greater than the width of the proof mass may provide better properties when used in an accelerometer. Referring to FIG. 19, a mask suitable for diffusing or implanting N-type materials 28, 30 as shown in FIG. Have been. This same mask can also be used to place new oxide layers 32, 34 over the N-type regions 28, 38 as shown in FIG. This protects the N-type region during oxygen ion implantation. Referring to FIG. 20, there is shown a mask suitable for creating a damping reduction groove using a potassium hydroxide etchant. The damping groove is etched on the (111) plane in a direction toward the buried oxide layer. The damping groove is located on the proof mass. FIG. 23 shows the relative position of the damping groove 402 on the proof mass. Referring to FIG. 21, additional masking to create the proof mass 408, hinges 412, 418, and surrounding support structure is shown. Regions 422, 424, 426, 428 represent areas that have been removed to allow proof mass 408 to move into the interior of the wafer. Tab 404 is an N-type doped region that prevents it from being etched during selective etching with electrochemical dopants. These tabs are bridges that are located inside and extend above the undercut channel to the same depth as the buried oxide. When the two complementary halves of the wafer are brought together and glued, this complementary bridge covers the space between the bridges on each wafer, thereby securing the top and bottom fixed electrodes. It forms a shield that guards the stray capacitance between them, resulting in only stray capacitance to ground. Areas 406, 410, 432, and 434 are wire bonding locations. Metallization layers are placed in these areas before performing wire bonding. In the embodiment shown, two hinges 412, 418 are located along one side of the proof mass 408. The hinge extends only slightly inward from the outer edge of the proof mass. Region 420 is shown between the edge of hinge 418 and the edge of proof mass 408. A similar area is located between hinge 412 and the opposite edge of proof mass 408. Hinge 412 includes a reinforcement region 415 located at the base of the hinge. A plurality of fingers 414 separated by spaces 416 form the rest of the hinge. In one embodiment, hinge 412 has a width of approximately 400 microns. The use of a slotted hinge allows the etching solution to pass through the slot between the fingers 414. This ensures that the entire area under the hinge removes all unwanted material. If the slot 416 is not in the correct position, the etchant will only access the lower portion of the hinge around the edge of the hinge. This results in a substantially longer etch time, which can damage other components of the device, or leave residual material beneath the hinge that can interfere with the operation of the hinge. . FIG. 22 shows the relative positions of the hinge, the proof mass 408, and the tab 404. A closure 440 is formed in the epitaxial layer to allow access to the silicon oxide layer located below the proof mass 408. This opening 404 allows the silicon oxide to be selectively etched, leaving only the unetched surface of proof mass 408 and surrounding structures. Vias are above this opening, and after oxide removal, the opening functions as a wire bonding port for contact from the top surface to the bottom fixed electrode. FIG. 23 is a diagram of the composite mask, showing the upper surface of the substrate 12. The relative positions of the hinge 412, proof mass 408, tab 404, damping groove 402, etc. are shown in this figure as the interrelation of these configurations. FIG. 24 shows the location of the damping groove 403 left on the upper surface of the proof mass 408 after the damping groove mask of FIG. 20 has been used. The damping groove 403 allows air to escape from the bottom or top of the proof mass 408. More precisely, the damping groove 403 can eliminate any adverse effects that may result from abrupt passage of air around the edge of the proof mass 408. This allows the proof mass 408 to flex freely without being obstructed by the flow of air. Preferably, the space around proof mass 408 is filled with an inert gas such as nitrogen. This prevents degradation of the proof mass 408 or parts around the device. Damping can also be adjusted by sealing the device in a reduced pressure atmosphere. In the embodiment shown in FIGS. 19 to 24, the proof mass 408 is approximately 3 mm × 3 mm. With this configuration, two hinges, each 400 microns, are suitable for supporting the structure of the proof mass 408. It can be seen that the aspect ratio of the proof mass 408 can be varied and that the proof mass 408 can be made larger or smaller depending on the particular application. The width of the hinges 412, 418 and the width of the fingers 414 and the slots 416 can be varied to suit the requirements of the accelerometer design, creating a stiffer or more flexible hinge. In another embodiment, the present invention provides another alternative method of creating a solid state accelerometer. This alternative method is known as the bond and etch-back method and is shown in successive steps in FIGS. Note that FIGS. 25-32 show alternative steps to those shown in FIGS. The bonding and etchback method is similar to the method described above in that the wafer is processed, cut in half, and the complementary halves are joined to obtain an accelerometer. However, the bonding and etch-back methods use phospho-silicate glass (PSG), which is a glass doped with 7 percent phosphorus. This oxide can etch 10 times faster than other oxides known in the art. Therefore, the etching step is greatly simplified. Further, the thickness of PSG is easier to control as compared to the oxide used in the SIMOX process described above. For example, in the current technology, when the SIMOX method is used, a value of 0.1 is obtained. Only 5 micron thick growth is possible, In contrast, In the bonding and re-etching method, On the board, A 1 micron PSG layer can be deposited or an oxide layer can be grown. Ultimately, The thickness of the oxide layer is Determine the size of the gap between the proof mass and the surrounding wall. As shown in FIG. Bonding and etch back methods Begin with an upper P-type silicon substrate 500. this is, A commercial unpatterned wafer with a continuous buried oxide created by oxygen ion implantation (SIMOX), Or 1 is a commercially available bonded wafer having a buried oxide. P-type silicon layer Epitaxially grown on the wafer surface. This P-type epitaxial layer 504 becomes a proof mass, At this stage, Half the desired thickness of the finished proof mass. Preferably, The P-type epitaxial layer 504 is As grown by the SIMOX process described above, 35 microns thick. Since the P-type epitaxial layer 504 is very thin and consequently fragile, The upper P-type substrate 500 It must function as a handle for manipulation of the entire wafer during processing. The P-type epitaxial layer 504 is Preferably, P-type boron doped epitaxial silicon. In FIG. 25 (b), A cross-sectional view of a substrate that is a complementary half to the substrate shown in FIG. 25 (a) is shown. Especially, FIG. 26 (b) A cross-sectional view of a bottom P-type silicon substrate 506 having a PSG or a thermal oxide layer 508 disposed or grown thereon is shown. A nitride masking film 510 is adhered to the other side of the bottom P-type substrate 506. By CVD The nitride pattern 512 As can be seen in FIG. The P-type epitaxial layer 504 is disposed. The nitride pattern 512 Used as an etching mask in subsequent steps. In FIG. 26 (b), The photoresist pattern 514 having the trench 516 comprises Placed on the PSG or thermal oxide layer 508. Through a reactive ion etching process, With vertical trench 516, Some portions of the PSG oxide layer 508 include It is removed by etching up to the P-type silicon substrate 506. In FIG. 27A, Thermal oxide layer 518 Grow inside windows or openings in nitride pattern 512. Oxides In the area that defines the proof mass contour after the subsequent KOH silicon etch, It is removed by etching. Due to the presence of the grown oxide layer 518, The area of the hinge and the guard diaphragm is prevented from being etched in KOH, On the other hand, The trench between the proof mass and the frame Etch to a depth equal to the desired hinge thickness. at this point, Oxides are removed, In all areas not protected by silicon nitride, Silicon etching occurs. The hinge thickness is Preferably, 2-5 microns. FIG. 27 (b) FIG. 27 shows a sputter arrangement of amorphous silicon on the resist pattern of FIG. 26 (b). Amorphous silicon 520 In addition to being filled into the vertical trenches 516, Cover resist pattern 514. next, The resist pattern 514 is removed, at the same time, Excess amorphous silicon 520 that was not sputtered into trench 516 is removed. with this, The trench 516 is Become linear with amorphous silicon 520, This amorphous silicon 520 It functions as a seal around the oxide island 550. In FIG. 28 (a), Potassium hydroxide (KOH) is used, The P-type epitaxial layer 504 at the opening of the nitride pattern 512 Anisotropically etched. As seen in the drawing, During the same exposure as KOH etching, The completely bare area of the P-type epitaxial layer 504 is Rather than the area of the P-type epitaxial layer 504 covered by the grown oxide layer 518, More substances are removed. this is, The KOH etch is the result of a head start having in the bare area of the P-type epitaxial layer 504. Hinge 522 for proof mass half 524 and guard 526 It can be identified as shown in the figure. The hinge 522 and the guard 526 are It has a thickness determined by the initial thickness of the grown oxide layer 518. Furthermore, The outline of the proof mass half 524 is defined. For example, The upper part 528 of the proof mass 524 is visible, The P-type epitaxial layer 524 is Fully etched up to PSG buried oxide etch stop 502, A trench 530 is formed. Conceptually, Although not shown, The removed trench 530 is Delineate half 524 of the proof mass. The complementary lower substrate is At this point, As shown in FIG. No action has been taken. Therefore, FIG. 27 (b) and FIG. 28 (a) Are identical. next, The nitride pattern 512 It is removed from the P-type epitaxial layer 504. The removed bare silicon surface Hydrated with a mixture of water, hydrogen peroxide and ammonium hydroxide. 28 (a) and 28 (b) Aligned as shown in FIG. Silicon fusion bonding. The bonded wafer is next, Annealing is performed in the procedure described in the SIMOX process described above. The upper P-type substrate 500 previously used as a handle is no longer needed, Removed by reverse grinding to a thickness of 100 microns, next, Using KOH, The remainder is etched to the oxide etch stop. The lower P-type substrate 506 is Protected from KOH etching by nitride masking film 510. KOH etching Stopped by a buried oxide etch stop 508 that is later selectively removed. The remaining bonded and removed wafer 532 is This is shown in FIG. The wafer 532 is next, It is cut into right and left halves. Referring to FIG. The portion of the wafer 532 on the drawing side and the portion on the side facing the back of the paper are Cut in half. The surface glued at the end of each half is again, Hydrated with a mixture of water, hydrogen peroxide and ammonium hydroxide. As shown in FIG. The half part is Silicon fusion bonding is performed and annealing is performed, This process is as described above. Hole 536 is Patterned through photolithography techniques through the upper nitride masking film 534, Thereby, Wire bond vias 538 can be anisotropically etched. Via 538 It is etched all the way down to the upper PSG or thermal oxide layer 540. Upper and lower PSG or thermal oxide layers 540; 542 are each removed by etching, Leave a gap around the completed proof mass 544. this is, This is shown in FIG. Amorphous silicon seal 520 provides PSG oxide layer 540, 542, This substance Protected from HF etching, Completely remains. The structure of the hinge 522 and the guard 526 is This becomes clear. The whole wafer is Freeze-dried in T-butanol, Or As already explained, It is cut into chips and centrifuged. A shadow mask is used, Placing contact metal 546 on surface 548; Wire bonding to the substrate becomes possible. The accelerometer is now complete, Located between two silicon electrodes, It has a precisely formed pendulum or diaphragm. In the present invention, Furthermore, The epitaxial silicon layer Oxidized silicon on insulator (silicon on insulator provided, SOI) attached to the substrate wafer, The former is transferred to the latter by the bonding and etch-back method described above, Consider another example. SOI wafers Widely applicable to sensor devices such as accelerometers. An excellent way to create microstructures such as accelerometers that require small controlled gaps, Processing the SOI wafer using wafer bonding, Some etch away the oxide under the transferred epitaxial layer. The disadvantage of this method is that Part of the epitaxial layer on the substrate, As part of this epitaxial layer remains fixed after removing the oxide, There are difficulties in anchoring. Importantly, The structure used for attachment is During the sacrificial etching of the oxide layer with hydrofluoric (HF) acid, It must not be eroded or removed by etching. The present invention We provide a process to overcome these difficulties. In a preferred embodiment, The process according to the invention comprises: The SIMOX wafer described above, Or Preferably, an SOI wafer is provided. As shown in FIG. SOI wafer 606 is A front oxide layer 600; A back oxide layer 608 has been grown. Below the front oxide layer, A P-type epitaxial silicon layer about 35 microns thick; That is, There is a P epitaxial layer. Also, There is also a buried oxide layer 604. This SOI wafer 606 is It is the same as that shown in FIG. Below, This will be described in more detail. The front oxide layer 600 Etched through a mask as shown in FIGS. 19 to 23, Array of surface damping grooves, An oxide pattern having well and diaphragm contours is formed. By processes known in the art, Spun photoresist by spinning, next, The resist is patterned by a photolithography technique through a mask that blocks ultraviolet (UV) light, Develop a resist similar to the desired pattern. next, Using HF, Various regions of oxide are removed by etching, The resist is removed, An oxide pattern remains. These preliminary steps on the substrate I have already detailed it. By adding KOH, The shallow area Into the board, Cut approximately 3 to 5 microns. FIG. After performing the above steps, A schematic cross-sectional view of the SOI wafer 606 is shown. The shallow area 610. The shallow region 610 It makes it easier to spin the resist, This process is Due to the uneven formation of the resist, Also, Since resist has a tendency to stay away from sharp corners and edges, It does not easily fit into deeper trenches. in this way, The shallow region 610 Almost like a flat wafer for spin resist process, This process is It is important for high productivity. In the next step shown in FIG. Coincide with the damping groove and shallow well and diaphragm area, The shallow region 610 defined earlier is Using HF, The oxide layer 600 is removed. A layer 612 of silicon nitride (Si3N4) It is disposed using reduced pressure chemical vapor deposition (LPCVD). LPCVD nitride 612 is: Preferably, It is about 1000 angstroms thick. next, The region of ion beam sputtered silicon oxide (SiO2), preferably 500 to 1000 Angstroms thick, Located inside the shallow well 610, An oxide cap 614 is formed. next, An approximately 1000 Å thick layer of reactive ion sputtered silicon nitride (Si 3 N 4) Placed in a shallow well 610, Forming a nitride cap 616, During the following steps, Protect oxide cap 614. this is, Placed at room temperature, by this, Under the lift-off process known in the art, The film can be reverse patterned using a resist mask. The lift-off process is Lift off the resist and film in the predetermined area, The reason is, This is because the resist prevents adhesion to the substrate. After the resist is dissolved by adding acetone and the unwanted oxide / nitride film is lifted off, A stack consisting of an oxide cap 614 and a nitride cap 616 remains. In another example process (not shown), This stack It can be placed on a flat surface, It is not always in the shallow well 610 as shown in FIG. The reason for placing on a shallow well rather than a flat surface is Space for a depletion area of appropriate thickness This is because this junction can be formed in an inversely doped epitaxial growth that occupies this space or cavity in an isolated embodiment. A deep trench is formed, This is, It becomes the hinge of the accelerometer. Especially, As shown in FIG. LPCVD nitride 612 is: Using resist and plasma etching, Along with the hinge well 618, It is patterned. The former process is preferred, The reason is, No underlying surface is required, This is because it can be removed by etching. After the LPCVD nitride 612 is patterned with the hinge well 618 to form the hinge, KOH is given to the deep etch, Typically, 20 to 25 microns of material is removed to the desired depth. this is, Establish a hinge thickness of 620, this is, Distance from buried oxide layer 604 to bottom of hinge well 618. The thickness 620 of the hinge is It varies depending on the range of g required for the accelerometer and the torsional stability, Normally, It ranges from 2 to 10 microns. During plasma or phosphoric etching The nitride cap 616 Protect oxide cap 614. During KOH etching, The oxide cap 614 is Protected by nitride cap 616. LPCVD nitride 612 is: Required to protect epitaxial silicon 602 during the next oxidation step. On the other hand, The epitaxial silicon inside the hinge well 618 During KOH etching Not protected. this is, The water vapor is exposed to an oxidation process consisting of oxidizing the surface of the hinge well 618 by heating it in a furnace. This thermal oxidation process Occurs at 1000 to 1100 ° C, It is well known in the art. as a result, As shown in FIG. The growth of oxides between 2000 and 4000 angstroms thick Cover the bottom 620 and side walls 622 of the hinge well 618. The diffusion of water and oxygen By nitride 612 by LPCVD, The remaining area is blocked. The wafer structure is no longer, It is not easily photo-patternable. The reason is, Due to the depth of the hinge well 618, Spin resist This is because the contour cannot be coated properly. For this issue, As already mentioned. In the following steps, LPCVD nitride 612 and nitride cap 616, The substrate must be removed and prepared for bonding in the next step. at first, LPCVD nitride 612 and nitride cap 616 To prevent K OH from etching epitaxial silicon 602, Also, To protect bare surfaces from oxidation, Needed. At this point, But, LPCVD nitride 612 and nitride cap 616 No longer needed. next, The wafer is Immerse in 160 ° C. phosphoric acid. Hinge well 618 is Coated with oxide, Do not etch. The nitride cap 616 and all LPC VD nitrides 612 By phosphoric acid, Except for a small patch of LPCVD silicon nitride protected by an oxide cap 614, Removed. This nitride patch 624. What remained was A bare silicon surface, Oxide 620, A hinge well 618 covered by 622; An oxide cap 614 covering the LPCVD silicon nitride patch 624; It is. this is, This is shown in FIG. The next step is It is a patterned alignment bond. This includes It is necessary to use alignment marks for infrared alignment of the outline between the two structures, SOI wafer 606 and oxidized wafer 626, which will be immediately bonded. The oxidized wafer 626 is A P-type silicon substrate on which a thermal or PSG oxide layer about 1 micron thick has been grown or deposited. For more information on this type of board, As already mentioned. As shown in FIG. Slot 630 is It is formed through oxide 628 corresponding to shallow well 610. Inside each slot 630, There is a reactive ion sputtered nitride layer 642, this is, It is located via the placement / lift-off process described above. This nitride layer 642 Protect the underlying silicon. Advantageously, The matching surface 648 of the oxidized wafer 626 under current conditions Depending on the residue of the resist, It is not rough. actually, Nitride is added by CVD, next, If the surface of the silicon from which the oxide surface 648 grows must be etched to obtain the pattern, This etching process To the roughness of several Angstroms RMS, At oxide surface 648, It will cause roughness. The roughened surface 648 is Therefore, Does not have enough smoothness for strong bonding. The matching surface 650 of the SOI wafer 606 and the matching surface of the PSG oxide wafer 628 shown in FIG. For other embodiments, According to the method described above, Preparation for bonding is made. at this point, SOI wafer 606 is 10: 1 HF, The oxide cap 614 is removed. FIG. Shown is an SOI wafer 606 bonded to a PSG oxide wafer 628. The handle wafer portion of the SOI wafer 606 shown in FIG. Most are ground down (polished), With oxide 604 buried before acting as an etch stop, It has been completely etched away. The process according to the invention comprises: It has advantages that are evident in this example. For example, In FIG. 39, At the top of the bonded wafer, There are no unsupported oxides, Directly below, There is a flat, continuous silicon surface. There are no re-entrant trenches that cannot be easily cleaned and dried for unwanted liquid leakage. The diaphragm or trench that outlines the proof mass, The process does not need to be formed yet, Therefore, In this structure, Provides structural rigidity to withstand rough handling. The bonded wafer 634 of FIG. For proof mass and hinge, It looks like a flat wafer ready for resist patterning of the substrate anchor wells and trench contours. Therefore, In FIG. 40, The bonded wafer 634 is Reactive ion etching to form deep slots 636, This etching is Stop at the embedded nitride layer for the anchor, This etching is The proof mass contour stops at the buried oxide layer. An exemplary deep slot 636 is shown in FIG. here, The deep slot 636 After the silicon epitaxial process, Functions as an anchor area. The depth is In cutting through the nitride patch 624, Finished. Especially, Reactive ion etching with sulfur hexafluoride (SF6) and helium gas is used, Cut deep slots, The reason is, This type of plasma etching This is because a wall having a high etching rate and a steep slope can be cut. 40 to 41, Reactive ion etching A cut is made through the nitride patch 624. FIG. Compared to FIG. FIG. 146 is an enlarged view of a deep slot 636. In the next step, The resist from the previous step is removed, The inner wall 638 It is oxidized in a furnace according to the oxidation process already described. The inner wall 638 Thus, As shown in FIG. Covered by oxide growth 640. The reactive ion sputtered nitride 642 with the nitride patch 624 By the application of phosphoric acid (H3PO4) Removed. What remains is A bare silicon surface cavity 644 with a bare silicon bottom and a ledge that is down (overhanging) from above. According to the process of the present invention, Leave bare silicon only where silicon epitaxial processing is desired. Furthermore, Without the process of the present invention, Even with conventional oxide growth and photolithography methods, To get the cavity structure, If not impossible, Very difficult. In FIG. 42, Using selective epitaxial processes known in the art, Only in the exposed silicon area within the cavity 644, Growing single crystal silicon. Selective epitaxial growth 646 includes Grows with the substrate, The process conditions are: Etching balances placement The nucleation of polysilicon is Does not occur on oxide surfaces, What happens on bare silicon surfaces. The protrusions that form at the top interfere with subsequent bonding steps, Epitaxial growth It is important that it does not occur at the inner wall 638. Therefore, The inner wall 638 Coated with oxide 638, Such epitaxial growth is prevented. Selective epitaxial growth 646 It grows on the same crystal axis as the original silicon substrate. This selective epitaxial growth 646 Therefore, An anchor that holds the SOI epitaxial wafer 606 to the oxidized wafer 626. Summary, The steps described above are: A peak occurs in the formation of anchors that bridge the oxidized wafer 626 to the SOI epitaxial wafer 606. As shown in FIG. The bonded wafer 634 is at this point, Ready to remove the buried oxide layer 604 exposed by the back grinding and etch back procedure; Also, The sidewall oxide 622 of the hinge wall 618 is optionally removed and ready to free up the proof mass hinge. From here, Processing of wafers It can continue in the same way as in the description of FIG. In a process according to another embodiment of the invention following FIG. Using a non-selective epitaxial process, By polysilico, The sidewalls 638 may be filled upwards with optional cavities 644. surely, In another dielectrically isolated embodiment of the present invention, The SOI wafer 606 does not have a shallow well 610 that forms a cavity 644. But, The nitride patch 624 is Still used, Functions as a barrier to HF etch during undercut. Sometimes, Non-selective epitaxial process It may be preferred over the selective epitaxial process described above. In this non-selective epitaxial process, The growth of polysilicon It is not limited to only exposed silicon regions. Furthermore, Non-selective epitaxial growth It has a much higher growth rate than selective epitaxial growth, For the purpose of filling the trench all the way to the top, Works better. at this point, The polysilicon inside the trench can be removed to a desired depth by mechanical polishing or grinding. Any additional polysilicon, Etchback by a semi-selective process, It is possible to obtain a desired arrangement pattern inside the trench. FIG. Continuing from FIG. 41, This alternative embodiment is shown. Especially, This alternative embodiment is Rather than junction isolation for selective epitaxial processes, By dielectric isolation, Non-selective epitaxial growth is used. this is, Except that the oxide cap 812 remains after the surrounding LPCVD nitride has been etched away leaving the LPCVD nitride patch 810. This is the same as the previous embodiment. The reason why the oxide cap 812 remains is that The oxide cap is Because it is made up to about 600 angstroms instead of 500 angstroms, Also, Much shorter after LPCVD nitride removal before bonding 10: This is because the HF dip (soaking) of 1 is performed. This oxide cap 812 again, Serves to protect the underside of ledge 814 of the deep slot 806, which is reactive ion etched; On the other hand, The unprotected nitride 808 in the oxidized wafer 800 Removed in phosphoric acid. next, The oxide cap 812 is 10: 1 in HF. The resulting wafer is This is shown in FIG. The remnants of the nitrided patch 810 are: It still covers the underside of ledge 814, There is also bare silicon 818 in the slots 816 formed in the PSG or thermal oxide layer 804. The wafer is at this point, Ready for epitaxial and polysilicon growth. In FIG. Approximately 37 microns of silicon 822 are shown to be non-selectively disposed. But, First, Silane Initially introduced to place polysilicon 822 on all surfaces, On the other hand, With a bare silicon interface, Single crystal growth has occurred. Future growth Fast, Using trichlorosilane or dichlorosilane, Until a thickness of 37 microns is obtained on all surfaces Will be maintained. at this point, The deep slot 806 Completely filled by crystal growth from below, Integrates with the growth of polysilicon from the oxidized wall 824 of the slot 816. The approximate boundaries of the different crystalline regions are Indicated by dashed line 820. For the anticorrosion undercut after the PSG oxide layer 804, Since there may be damage to the grain boundaries of the polysilicon 822, It is preferable to have a single crystal exposed to the HF etch. In the next step, The non-selectively arranged silicon of the wafer Using standard polishing techniques used with bare silicon wafers, Chemically and mechanically, Polished again. Polishing is The silicon placed in slot 816 remains unchanged, It only reduces the top of the high spot. The wafer is Until only 2 to 5 microns of silicon 822 remain on the exposed buried oxide layer 802 Polished. The remainder of the polysilicon 822 on the buried oxide layer 802 is By etching in KOH, Or Removed by dry reactive ion etching. To ensure removal of all silicon 822 on the exposed surface of buried oxide layer 802, Excessive etching is preferred. Surface 826 of polysilicon 822 is As shown in FIG. Due to excessive etching, It is slightly concave. The wafer is here, To make an accelerometer or other device, Ready for further processing. Especially, The wafer is Patterning and reactive ion etching, A trench is formed around the contour of the proof mass. next, Oxide on the surface of the wafer is removed, The wafer is Be cut off. These two half wafers are By fusion bonding (bonding) Joined. During anticorrosion etching, Single crystal silicon, Nitride, which is etched three orders of magnitude slower than oxide in HF, Protects oxidized sidewalls from etchant. In yet another embodiment, The process, From the above process starting from FIG. Continue further. In this alternative embodiment, shown in FIG. 43, To match buried oxide 702 in SOI wafer 706 similar to that shown in FIG. Including etching the trench 700. As shown in FIG. There is no nitride patch to protect the oxide from the reactive ion etching process. next, There is oxide etching, Removing part of the buried oxide 702; Bulged wall 704, Or Make an undercut. next, The trench 700 Shadow mask In response to reactive ion sputtered nitride, Cover the side walls and bottom. There must be an oxidation step to cover part of the perimeter of the top of the upper wall. after, The nitride on the bottom of the trench 700 must be removed, Exposing the bare silicon of the underlying substrate, Enables selective epitaxial growth. After the nitride has been removed, Epitaxial silicon grows in place, Prevents adhesion. After the nitride has been removed by etching, The trench 700 By the growth of epitaxial silicon 710 in the form of plugs, It is filled. There is no epitaxial silicon growth in void 714, The reason is, The nitride is shadow masked, The oxide grows on any unprotected silicon regions. The final product is It is similar to that shown in FIG. For a new way to create solid state equipment, This has been described above. If you are skilled in the art, Utilizing the teachings of the present invention, Without departing from the scope of the invention, which is defined solely by the following claims, Change the physical dimensions of this structure, Change the method to create similar devices with similar characteristics, Further modifications can be made.

[Procedure amendment] [Submission date] September 11, 1997 [Correction contents]   The description in [Claims] is amended as follows.   [1. A method of forming a multilayer sacrificial etched silicon substrate, comprising:   Providing a silicon substrate having a multiple buried oxide layer;   Etching away the buried oxide layer;   Place the silicon substrate on a rotating fixture at a predetermined distance from its focal point Attaching (suspend) step;   Rotating the fixture around the focal point at a certain rotational speed to achieve a predetermined centrifugal force Steps   A method comprising:   2. 2. The method of claim 1, wherein the predetermined centrifugal force is between 1000 g and 30 g. A method characterized by being in the range of 00g.   3. 2. The method according to claim 1, wherein the rotation speed is between 5000 and 7000R. A method characterized by being in the PM range.   4. A method for purging a multilayer sacrificial etch silicon substrate accelerometer. What   Formed from a multi-layer sacrificial etched silicon substrate and cantilevered Providing an accelerometer including a proof mass suspended from the substrate And   Step to add etchant and remove sacrificial layer by etching And   Rotation with open top compartment at a fixed distance from the center of rotation Providing a platform;   Lining the compartment with an absorbent material;   Inserting the silicon substrate into the compartment, Are located in a plane defined by the rotational movement of the rotating platform. Steps to perform   Covering the compartment;   By spinning the platform, an etchant is applied to the substrate. Flowing out and being absorbed by the absorbent material;   A method comprising:   5. The method of claim 4, wherein   The step of inserting the silicon substrate may include the step of: Rotation of the platform on which the free end of the proof mass is spinning. Further comprising the step of pointing away from the center of the object. Way.   6. 5. The method of claim 4, wherein the step of spinning the platform. The top is such that the silicon substrate accelerometer experiences between 1000 g and 3000 g Further comprising the step of spinning the platform Law.   7. A method for purging a multilayer sacrificial etch silicon substrate accelerometer. What   Steps to provide an accelerometer formed from a multi-layer sacrificial etched silicon substrate And   Removing the sacrificial layer by adding an etchant;   A rotating platform having a compartment at a fixed radius from the center of rotation Providing the form   Lining the compartment with an absorbent material;   Mounting the accelerometer in the compartment;   Closing the compartment;   Rotating the platform to achieve a predetermined rotational acceleration of the accelerometer Steps   A method comprising:   8. The method of claim 7, wherein the radius is between 30 mm and 50 mm in length. A method comprising:   9. The method of claim 7, wherein the accelerometer has a center of gravity. The proof mass is hingedly attached to the substrate. The accelerometer is configured so that the center of gravity is on the same straight line as the radius. A method characterized by being positioned in a compartment.   10. The method of claim 7, wherein the etchant comprises HF. Features method.   11. The method of claim 7, wherein the sacrificial layer comprises an oxide material. Features method.   12. The method of claim 7, wherein the accelerometer is hinged to the substrate. Further comprising a flat (planar) proof mass mounted thereon. The roof mass is contained in the plane defined by the rotating platform A method characterized by being performed. 』

────────────────────────────────────────────────── ─── Continuation of front page    (81) Designated countries EP (AT, BE, CH, DE, DK, ES, FI, FR, GB, GR, IE, IT, L U, MC, NL, PT, SE), OA (BF, BJ, CF) , CG, CI, CM, GA, GN, ML, MR, NE, SN, TD, TG), AP (KE, LS, MW, SD, S Z, UG), UA (AM, AZ, BY, KG, KZ, MD , RU, TJ, TM), AL, AM, AT, AU, AZ , BA, BB, BG, BR, BY, CA, CH, CN, CU, CZ, DE, DK, EE, ES, FI, GB, G E, HU, IL, IS, JP, KE, KG, KP, KR , KZ, LC, LK, LR, LS, LT, LU, LV, MD, MG, MK, MN, MW, MX, NO, NZ, P L, PT, RO, RU, SD, SE, SG, SI, SK , TJ, TM, TR, TT, UA, UG, UZ, VN [Continuation of summary] And the filter paper (912), (91) 4), (916), the composite wafer (9 00) and covered by lid (918). It is.

Claims (1)

[Claims]   1. A method of forming a multilayer sacrificial etched silicon substrate, comprising:   Providing a silicon substrate having a multiple buried oxide layer;   Etching away the buried oxide layer;   Place the silicon substrate on a rotating fixture at a predetermined distance from its focal point Attaching (suspend) step;   Rotating the fixture about the focal point to achieve a predetermined centrifugal force;   A method comprising:   2. 2. The method of claim 1, wherein the predetermined centrifugal force is between 1000 g and 30 g. A method characterized by being in the range of 00g.   3. 2. The method according to claim 1, wherein the rotation speed is between 5000 and 7000R. A method characterized by being in the PM range.   4. A method for purging a multilayer sacrificial etch silicon substrate accelerometer. What   Formed from a multi-layer sacrificial etched silicon substrate and cantilevered Providing an accelerometer including a proof mass suspended from the substrate And   Removing the sacrificial layer by etching with the addition of an etchant;   Rotation with open top compartment at a fixed distance from the center of rotation Providing a platform;   Lining the compartment with an absorbent material;   Inserting the silicon substrate into the compartment, Are located in a plane defined by the rotational movement of the rotating platform. Steps to perform   Covering the compartment;   By spinning the platform, an etchant is applied to the substrate. Flowing out and being absorbed by the absorbent material;   A method comprising:   5. The method of claim 4, wherein   The step of inserting the silicon substrate may include the step of: Rotation of the platform on which the free end of the proof mass is spinning. Further comprising the step of pointing away from the center of the object. Way.   6. 5. The method of claim 4, wherein the step of spinning the platform. The top is such that the silicon substrate accelerometer experiences between 1000 g and 3000 g Further comprising the step of spinning the platform Law.   7. A method for purging a multilayer sacrificial etch silicon substrate accelerometer. What   Steps to provide an accelerometer formed from a multi-layer sacrificial etched silicon substrate And   Removing the sacrificial layer by adding an etchant;   A rotating platform having a compartment at a fixed radius from the center of rotation Providing the form   Lining the compartment with an absorbent material;   Mounting the accelerometer in the compartment;   Closing the compartment;   Rotating the platform to achieve a predetermined rotational acceleration of the accelerometer Steps   A method comprising:   8. The method of claim 7, wherein the radius is between 30 mm and 50 mm in length. A method comprising:   9. The method of claim 7, wherein the accelerometer has a center of gravity. The proof mass is hingedly attached to the substrate. The accelerometer is configured so that the center of gravity is on the same straight line as the radius. A method characterized by being positioned in a compartment.   10. The method of claim 7, wherein the etchant comprises HF. Features method.   11. The method of claim 7, wherein the sacrificial layer comprises an oxide material. Features method.   12. The method of claim 7, wherein the accelerometer is hinged to the substrate. Further comprising a flat (planar) proof mass mounted thereon. The roof mass is contained in the plane defined by the rotating platform A method characterized by being performed.