JPH104401A - Frame synchronization system and its circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To acquire a frame synchronization position more stably even when a level fluctuation takes place by excluding the effect of jitter due to a noise at a receiver side caused when frame synchronization is taken with a simple configuration. SOLUTION: A correlation section 11 obtains a correlation signal (a) between a time division multiplex digital radio transmission signal to which a synchronizing signal is inserted and a predetermined synchronization pattern. A level comparison section 12 compares the correlation signal (a) with preset threshold value VTH and provides an output of a pulse (b) having a width of a time Δt in excess of the threshold value. A width calculation section 13 obtains the time Δt equivalent to the pulse width of the pulse (b) and calculates the half Δt/2 of the time Δt. The pulse (b) outputted from the level comparison section 12 is delayed by the half Δt/2 of the time Δt at a delay section 14 to provide a frame synchronization timing signal (c) rising almost at a peak of the correlation peak waveform.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization system for detecting a frame synchronization position of a time division multiplexed digital radio transmission signal and a circuit thereof.

[0002]

2. Description of the Related Art In a TDMA (Time Division Multiple Access) system, a plurality of users use one radio channel in a time division manner. Therefore, it is necessary to synchronize each signal so that signals do not overlap. Therefore, as shown in FIG. 5, a frame synchronization signal is inserted at a predetermined position of the digital radio transmission signal a, and the reception timing is controlled when the digital radio transmission signal a is received. It has gained. A technique for obtaining the frame synchronization timing signal b is a frame synchronization method.

The frame synchronization system includes, for example, a pattern detection system. This is a system in which a synchronization pulse train composed of a plurality of bits inserted into a digital wireless transmission signal is subjected to pattern matching simultaneously as one block. Specifically, FIG.
As shown in (1), the correlation unit 11 performs a correlation process between the received signal and the synchronization pattern, and the level comparison unit 12 outputs a pulse whose correlation value a exceeds a predetermined threshold _VTH as a frame synchronization timing signal b. , The rising edge of the timing signal is detected as the synchronization pulse position of the frame.

[0004]

However, in such a conventional system, the peak position of the correlation value is slightly shifted in a situation of a mobile radio wave path where the reception level fluctuates remarkably, causing a large jitter. Becomes For example, as shown in FIG. 4, when the correlation value a fluctuates in level as a ₁ , a ₀ , a _2, the frame synchronization timing signal b detected in accordance therewith also changes in phase as b ₁ , b ₀ , b _2. Is shifted. In particular, when high-speed transmission is performed, there is a problem that optimal decoding cannot be performed due to this shift.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems in the prior art, to obtain a more reliable frame synchronization position, and to realize a frame synchronization system which can be realized with a simple configuration. A synchronous circuit is provided.

[0006]

According to a first aspect of the present invention, in the frame synchronization system, when synchronizing a frame of a digital radio transmission signal having a frame synchronization signal inserted at a predetermined position, the digital radio transmission signal and the digital radio transmission signal are synchronized. A correlation process with a predetermined synchronization pattern is performed to obtain a correlation value having a peak waveform, a peak position of the peak waveform is calculated from the correlation value, and the peak position is determined as a frame synchronization position. Frame synchronization method.

According to a second aspect of the present invention, there is provided a frame synchronization circuit for synchronizing a frame of a digital radio transmission signal in which a frame synchronization signal is inserted at a predetermined position. A correlation unit that performs correlation processing with a predetermined synchronization pattern and outputs a correlation value signal having a mountain-shaped correlation peak waveform in time series, and compares the level of the correlation value signal with a preset threshold value A level comparison unit that outputs a pulse having a time width in which the correlation peak waveform exceeds the threshold level; a width calculation unit that calculates half the time width from the pulse output; And a delay section for delaying a pulse output from the level comparison section and outputting the delayed pulse as a frame synchronization timing signal.

The operation of the circuit according to the present invention will be described. When a digital radio transmission signal is input to a correlator, a correlation process with a predetermined synchronization pattern is performed, and a correlation having a mountain-shaped correlation peak waveform is obtained. The value signal is output in time series from the correlation unit. The level of the correlation value signal is compared with a preset threshold value in the level comparing section, and a pulse having a time width in which the correlation peak waveform exceeds the level of the threshold value is output from the level comparing section. The width calculating unit calculates half the time width from the pulse output from the pulse output, adds the calculated time to the delay unit, and outputs a frame synchronization timing signal in which the pulse is delayed by that time from the delay unit. .

The frame synchronization timing signal is output after being delayed by a half of the pulse width output from the level comparing section, so that it rises substantially at the correlation peak position. Since the correlation peak position does not change even when the level of the correlation peak value changes, the frame synchronization timing is not affected by the level change. Therefore, even if the reception level fluctuates and the level of the correlation peak value shifts, a stable frame synchronization position can always be obtained, and optimal decoding can be performed even when high-speed transmission is performed.

[0010]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a frame synchronization system according to the present invention;

FIG. 1 shows an example of the configuration of a frame synchronizing circuit adopting a system in which a synchronizing pulse train composed of a plurality of bits is simultaneously detected as one block by pattern matching.
The correlation unit 11 performs a complex correlation calculation between a reception signal, which is a digital wireless transmission signal, and a predetermined synchronization pattern stored on the reception side, and outputs a correlation value signal a in a time series. The level comparing unit 12 compares the level of the correlation value signal a with a preset threshold value V _TH by utilizing the appearance of a correlation peak waveform in the correlation value signal a obtained by the correlation unit 11. Then, a pulse b having a time width Δt at which the correlation peak waveform exceeds the level of the threshold value V _TH is output.
Width calculating unit 13, the correlation value signal a from the pulse b obtained from the level comparing section 12 calculates the time Delta] t / 2 which is half the time Delta] t of level width that exceeds the threshold value V _TH. The delay unit 14 outputs the pulse b output from the level comparison unit 12
Is delayed by the time Δt / 2 obtained by the width calculation unit 13 to output a frame synchronization timing signal c to the outside of the frame synchronization circuit.

Next, the operation of the frame synchronization circuit of the present embodiment based on the above configuration example will be described with reference to FIG.
FIG. 2 is a waveform diagram in which the vertical axis represents level and the horizontal axis represents time.
a indicates a correlation value signal output from the correlation unit 11, b indicates a pulse output from the level comparison unit 12, and c indicates a frame synchronization timing signal output from the delay unit 14.

When a digital radio transmission signal in which a frame synchronization signal is inserted at a predetermined position is input to the correlation unit 11, correlation processing with a synchronization pattern stored on the receiving side is sequentially performed from the head thereof. Then, the correlation value signal a is output from the correlation unit 11 in time series. The correlation value signal a obtains a correlation peak value at a position where the frame synchronization signal is inserted, and has a substantially symmetrical chevron waveform about the correlation peak value.

When the correlation value signal a obtained by the correlation unit 11 is input to the level comparison unit 12, a portion where the correlation value signal a exceeds the threshold V _TH is detected, and the threshold V _TH is detected. A pulse b having a time width Δt exceeding the level is output from the level comparison unit 12.

This pulse b is input to the width calculating unit 13,
The time Δt of the width of the pulse b obtained by the level comparing section 12 is obtained, and from the time Δt, a time Δt / 2 of half of the correlation value signal “a” _exceeding the threshold value V _TH is calculated and delayed. It is output to the unit 14.

In the delay unit 14, the pulse b output from the level comparison unit 12 is converted into the threshold V calculated by the width calculation unit 13.
_It delays by half the time Δt / 2 of the correlation value signal “a” _{exceeding TH,} and outputs the delayed pulse as the frame synchronization timing signal “c”. Here, the frame synchronization position is indicated by a rising point of the frame synchronization timing signal c.

Since the correlation peak waveform has a substantially symmetrical chevron shape centered on the correlation peak value, if the pulse b output from the level comparison unit 12 is delayed by half the pulse width, the frame synchronization The timing signal c rises substantially at the correlation peak position. Here, it can be seen that even if the reception level remarkably fluctuates and the level of the correlation value signal a fluctuates, the position of the correlation peak value hardly changes. Therefore, even if the level fluctuates, the rise of the frame synchronization timing signal c occurs. The time point does not change, and the frame synchronization position can always be stabilized.

Since the finally detected frame synchronization position is determined to be the correlation peak position which is not affected by the level fluctuation, the timing deviation of the correlation peak waveform caused by the level fluctuation of the received signal is reduced. And a more stable frame synchronization position can be obtained. Therefore, in TDMA mobile communication, it is possible to eliminate the influence of jitter due to noise on the receiving side which occurs when synchronizing the reception timing.

[0019]

According to the method of the present invention, since the correlation peak position which is not significantly affected by the level fluctuation of the correlation peak is determined as the frame synchronization position, a more reliable frame synchronization position can be obtained. it can.

Further, according to the circuit of the present invention, the frame synchronization timing can be obtained more accurately even in a situation of a mobile radio wave path where the reception level fluctuates, with a simple configuration having only the width calculation section and the delay section. it can.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a frame synchronization circuit according to an embodiment of the present invention.

FIG. 2 is a waveform diagram of each part of the frame synchronization circuit of FIG.

FIG. 3 is a configuration diagram of a conventional frame synchronization circuit.

4 is a waveform diagram of each part of the frame synchronization circuit when the level of FIG. 3 fluctuates.

FIG. 5 is an explanatory diagram of a digital wireless transmission signal into which a frame synchronization signal is inserted and a frame synchronization timing signal.

[Explanation of symbols]

 Reference Signs List 11 correlation section 12 level comparison section 13 width calculation section 14 delay section a correlation signal b pulse c frame synchronization timing signal

Claims (2)

[Claims] When performing frame synchronization of a digital wireless transmission signal in which a frame synchronization signal is inserted at a predetermined position, a correlation process between the digital wireless transmission signal and a predetermined synchronization pattern is performed. A frame synchronization method in which a correlation value having a peak waveform is obtained from the correlation value, a peak position of the peak waveform is calculated from the correlation value, and the peak position is determined as a frame synchronization position. 2. A frame synchronization circuit for synchronizing a frame of a digital radio transmission signal in which a frame synchronization signal is inserted at a predetermined position, wherein a correlation between the digital radio transmission signal and a predetermined synchronization pattern is determined. A correlation section that performs processing and outputs a correlation value signal having a corrugated peak waveform in a time series, and compares the level of the correlation value signal with a preset threshold value, and a correlation peak waveform is generated. A level comparison unit that outputs a pulse having a time width exceeding the value level, a width calculation unit that calculates half the time width from the pulse output, and a time output from the level comparison unit for the calculated time A delay unit that delays a pulse and outputs the result as a frame synchronization timing signal.