JPH104360A - Variable length decoding method and device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize high speed processing in the case of decoding a binary data stream where a plurality of original data are compressed. SOLUTION: In the case of decoding a binary data stream where a plurality of original data are compressed, data are read into a memory from the binary data stream by a total code length of each longest code in codes corresponding to a plurality of the original data in the step S12. A plurality of the original data are decoded from the read data in the succeeding step S13. Number of bits used for decoding a plurality of the original data is obtained in the succeeding step S14 and the number of bits in use is deleted from the head of the binary data stream in the succeeding step S15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a variable length decoding method for decompressing compressed data to obtain restored data, and an apparatus therefor.

[0002]

2. Description of the Related Art One of the most widely used image compression systems at present is a so-called MPEG (Moving Picture).
Coding Experts Group) Standards.
This MPEG is ISO / IEC JTC1 / SC29
(International Organization for Standardization /
International Electrotechnical Commission, JointTe
chnical Committee 1 / Sub Committee 29: International Organization for Standardization / International Electrotechnical Commission Joint Technical Committee 1 / Special Committee 29)
There are ISO11172 as the MPEG1 standard and ISO13818 as the MPEG2 standard. In these international standards, ISO11172-1 and ISO13818-1 for multimedia multiplexing are
ISO11172-2 and ISO13818-2 are standardized for video items, and ISO11172-3 and ISO13818-3 are standardized for audio items.

[0003] As in the image coding method based on the MPEG standard, a method of compressing by utilizing the correlation with past and future images, that is, a method of compressing by performing motion compensation is highly efficient and promising. Have been.

[0004] FIG. 7 shows a code of a macroblock mode (macroblock_modes) part in MPEG2 as a part of an encoded data string compressed by MPEG2, and a number in a right column in the figure shows a bit length. I have.

[0005] The decoder receives the compressed code data sequence (input binary data sequence), looks at the codes in order from the beginning, and detects a pattern that matches the macroblock_type variable-length code pattern (not shown). Then, the decoded data corresponding to the pattern is defined as macroblock_type.

Next, spatial_temporal_weight_code_fla
g is 1 and spatial_temporal_weight_code_t
If able_index is not 0, the 2-bit code following the code for macroblock_type is changed to spatial_temporal_weigh
Set to t_code.

Next, if at least one of macroblock_motion_forward or macroblock_motion_backward is not 0, the following operation is performed. That is, picture_st
If ructure has a frame structure, frame_pred_f
If the value of rame_dct is 0, the sign of the next 2 bits is fram
If e_motion_type is set and the value of frame_pred_frame_dct is not 0, nothing is performed. picture_structure is frame
If it is not the e structure, the following 2 bit code is
Set to on_type.

Next, picture_structure has a frame structure, frame_pred_frame_dct has a value of 0, and macroblock_intra or macroblock_patte
If either of rn is not 0, the sign of the following 1 bit is dc
Set to t_type.

However, the code data sequence input before the code data sequence related to macroblock_modes
ial_temporal_weight_code_flag, spatial_temporal_w
eight_code_table_index, macroblock_motion_forward
, Macroblock_motion_backward, picture_structure
, Frame_pred_frame_dct, macroblock_intra, macrobl
ock_pattern has been decrypted.

In this manner, macroblock_modes (macr
oblock_type, spatial_temporal_weight_code, frame_m
otion_type, field_motion_type, and dct_type). Also, the bit length (No. of bits) in FIG.
In the column of, a part of such an encoded data sequence in which the length of each code is indicated, for example, a data sequence relating to macroblock_modes, a processing procedure when decoding processing is performed using a microprocessor having a memory 8 to
This will be described with reference to FIG.

FIG. 8 to FIG. 10 are flowcharts of a series of operations for this decoding. Before performing the series of operations in FIGS. 8 to 10, spatial_temporal_weight_code_f
It is assumed that lag and the like are decoded and stored in respective areas on the memory of the microprocessor.

In FIG. 8, this series of operations starts in step S401, and proceeds to step S402.

In step S402, the first 9 bits of an input binary data sequence (code data sequence) are read from the input / output port of the microprocessor, and are substituted into the variable BS area on the memory. Then, step S403
Proceed to. In step S403, the value of the BS is checked from the beginning, a pattern that matches the pattern of the variable-length code of macroblock_type is detected, and decoded data corresponding to the pattern is defined as macroblock_type. That is, the corresponding decoded data is assigned to the area of the variable macroblock_type on the memory. The detection of the matching pattern is performed by a logic operation circuit of the microprocessor. Further, the length of the matched pattern (the number of bits used in decoding) is assigned to the area of the variable UB on the memory. macroblock_type
The minimum code length is 1 bit and the maximum is 9 bits (see FIG. 7). Therefore, it is always possible to decode (UB =
1-9). Next, the process proceeds to step S404. Step S4
In step 04, UB bits are deleted from the head of the input binary data string, and the UB + 1 bit is set as the head. Specifically, this means that when the input binary data string is read from the beginning thereafter, it is read from the UB + 1st bit. Then, the process proceeds to step S405.

In step S405, the variable spat in the memory
ial_temporal_weight_code_flag, spatial_temporal_w
Examine eight_code_table_index, spatial_temporal_wei
ght_code_flag is 1 and spatial_temporal_w
Check whether eight_code_table_index is not 0.
This check is performed by the logical operation circuit. If true, the process proceeds to step S406, and if false, the process proceeds to step S409 in FIG. In step S406, the first two bits of the input binary data string are read from the input / output port and assigned to the area of the variable BS on the memory 32.
Then, the process proceeds to step S407. Step S407
Then, spatial_temporal_weight_code is obtained from the value of BS. Specifically, the value of BS, which is 2-bit data, is
Just copy it to the variable spatial_temporal_weight_code in memory. Then, the process proceeds to step S408. In step S408, two bits are deleted from the head of the input binary data string, and the third bit is set as the head. Then, the process proceeds to step S409 in FIG.

At step S409 in FIG. 9, variables macroblock_motion_forward, macroblock_motion_ba
Check ckward and check if at least one of macroblock_motion_forward or macroblock_motion_backward is 0
Check if it is not. If true, step S410
If it is false, the process proceeds to step S418 in FIG.
In step S410, the variable picture_structur on the memory
Check e and check if picture_structure is a frame structure. If true, the process proceeds to step S411, and if false, the process proceeds to step S415. Step S4
At 11, check the variable frame_pred_frame_dct on the memory,
Check whether the value of frame_pred_frame_dct is not 0. If true, the process proceeds to step S412, and if false, the process proceeds to step S418 in FIG. In step S412,
The first two bits of the input binary data string are read from the input / output port, and are substituted into the variable BS area on the memory. Then, the process proceeds to step S413. Step S
At 413, frame_motion_type is obtained from the value of BS.
Specifically, the value of the BS, which is 2-bit data, may be copied to the variable frame_motion_type on the memory. Then, the process proceeds to step S414. In step S414,
Delete 2 bits from the beginning of the input binary data string,
The bit is the head. Then, step S4 in FIG.
Proceed to 18. In step S415, the first two bits of the input binary data string are read from the input / output port, and are substituted into the area of the variable BS on the memory. Then, the process proceeds to step S416. In step S416, B
Field_motion_type is obtained from the value of S. In particular,
The value of BS, which is 2-bit data, is stored in a variable fi on the memory.
Just copy it to eld_motion_type. Then, the process proceeds to step S417. In step S417, two bits are deleted from the head of the input binary data string, and the third bit is set as the head. Then, the process proceeds to step S418 in FIG.

At step S418 in FIG. 10, the variables picture_structure, frame_pred_frame_dct,
Check oblock_intra and macroblock_pattern,
structure is a frame structure and frame_pred
It is checked whether the value of _frame_dct is 0 and either macroblock_intra or macroblock_pattern is not 0. If true, the process proceeds to step S419, and if false, the process proceeds to step S422. In step S419,
From the input / output port 33, the first 1
The bits are read and assigned to the area of the variable BS on the memory 32. Then, the process proceeds to step S420. In step S420, dct_type is obtained from the value of BS. Specifically, the value of BS, which is 1-bit data, may be copied to the variable dct_type on the memory 32. Then, the process proceeds to step S421. In step S421, one bit is deleted from the head of the input binary data string, and the second bit is set as the head. Then, the process proceeds to step S422. Then, in step S422, this series of processing ends.

In this manner, the decoding relating to macroblock_modes is performed using the microprocessor.

[0018]

By the way, if true in all the branches of the above steps S405, S409, S410, S411, and S418, step S402, step S40
6, the input binary data string must be read from the input / output port 33 at four locations in step S412 and step S419. Since the reading process takes time, there is a disadvantage that the decoding process cannot be performed at high speed.

That is, in the conventional decoding method,
Since it is necessary to read the input binary data sequence once to decode one value, there is no answer to the demand for high-speed decoding.

The present invention has been made in view of such circumstances, and has a variable length decoding method capable of performing high-speed decoding when decoding a binary data string obtained by compressing a plurality of original data. And a variable-length decoding device.

[0021]

According to the variable length decoding method of the present invention, a binary data string obtained by compressing a plurality of original data is input, and decoding is performed from the binary data string. In the variable-length decoding method for restoring the code, the total code length (for example, 1) when each code is the longest code among the codes corresponding to the plurality of original data.
4 bits), the data is read from the binary data string, the plurality of original data are decoded from the read data, and the number of bits (UB) used in decoding the plurality of original data is obtained. The above-described problem is solved by deleting the number of bits from the beginning of the binary data string.

Further, according to the variable length decoding device of the present invention, a binary data string obtained by compressing a plurality of original data is input, decoding is performed from the binary data string, and the variable length decoding apparatus restores the plurality of original data. In the long decoding device, data is read from the binary data string by a total code length when each code is the longest code among the codes corresponding to the plurality of original data, and the read data is stored. And a restoration data generation circuit for decoding the plurality of original data from the read data stored in the storage element and obtaining the number of bits used in decoding the plurality of original data. The above-mentioned problem is solved by providing a data deletion circuit for deleting the number of used bits from the beginning of the binary data string.

According to the variable length decoding method and the variable length decoding device of the present invention, an input binary data sequence is read from the beginning of the input data sequence once more (for example, about 8 to 128 bits), and is read. It is stored in the area of the variable BS on the memory 32. Then, decoding of a plurality of data is performed from the BS, the total number of bits used in each decoding is obtained, and the value of the total number is deleted from the head of the input binary data string. Thereby, decoding of a plurality of data can be performed by reading the input binary data sequence once, and the decoding process can be performed at high speed.

[0024]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram for explaining an embodiment of the present invention. In the embodiment of the present invention, a binary data string obtained by compressing a plurality of original data is input,
A variable length decoding method for decoding from the binary data sequence and restoring the plurality of original data is assumed.

In FIG. 1, when the decoding process is started in step S11, in a first step S12, a total code when each code is the longest code among the codes corresponding to the plurality of original data. Only the length is read from the binary data string into the memory. In the next step S13, the plurality of original data are decoded from the read data. In the next step S14, the number of bits used in decoding the plurality of original data is obtained, and the process proceeds to the next step S15, where the number of used bits is deleted from the beginning of the binary data string, and the next step S16 Ends the processing. Here, the order of steps S13, S14, and S15 may be changed.

FIG. 2 shows an example of a hardware configuration for realizing such processing.

FIG. 2 shows the internal configuration of a general microprocessor, which has a logical operation circuit 31, a memory 32, an input / output port 33, a bus line 34, and a control circuit 35. It is configured. Data is input from the input / output port 33 and is taken into the memory 32 via the bus line 34. The captured data is
The data is supplied from the memory 32 to the logical operation circuit 31 via the bus line 34, the logical operation circuit (ALU) 31 performs desired processing, and is fed back to the memory 32. When all processing is completed, the result is output to the input / output port 33 via the bus line 34. These controls are performed by the control circuit 35. In this manner, the data is subjected to desired processing by the microprocessor.

Next, a description will be given of a specific example of a processing procedure for decoding the above-described embodiment of a code data string which has been compression-encoded by the so-called MPEG2.

FIGS. 3 to 5 show the M shown in FIG.
Macroblock mode (ma) in PEG2 encoded data
2 shows a procedure for decoding the code of the part of (croblock_modes), for example, a processing procedure when performing variable length decoding by the microprocessor shown in FIG.

In this specific example, before performing the series of operations shown in FIGS. 3 to 5, spatial_temporal_weight_co
It is assumed that de_flag and the like are decoded and stored in respective areas on the memory 32 in FIG.

In FIG. 3, this series of operations starts in step S101, and proceeds to step S102.

In step S102, the leading 14 bits of the input binary data sequence (code data sequence) are read from the input / output port 33 of FIG. 2 and are substituted into the variable BS area on the memory 32. Then, the process proceeds to step S103. In step S103, the value of the BS is checked from the beginning, a pattern that matches the pattern of the variable-length code of macroblock_type is detected, and decoded data corresponding to the pattern is defined as macroblock_type. That is, the corresponding decoded data is assigned to the area of the variable macroblock_type on the memory 32. This matching pattern is detected by the logical operation circuit 31. Further, the length of the matched pattern (the number of bits used in decoding) is assigned to the area of the variable UB on the memory 32. The minimum code length for macroblock_type is 1 bit and the maximum is 9 bits (FIG. 7).
), It is always possible to decode from only the BS value obtained by copying the 14-bit data (code) (UB = 1 to
9). Next, the process proceeds to step S104. Step S104
To delete UB bits from the head (left end) of the BS,
Shift by bits. As a result, UB bits are deleted from the beginning of the input binary data string, and the UB + 1-th bit is set to "14-from the beginning of the input binary data string.
The value of the UB bit "and the value of the BS match. And
Proceed to step S105.

In step S105, the variables in the memory 32
spatial_temporal_weight_code_flag, spatial_tempor
Examine al_weight_code_table_index and find spatial_temporal
_weight_code_flag is 1 and spatial_tempor
Check if al_weight_code_table_index is not 0. This check is performed by the logical operation circuit 31. If true, the process proceeds to step S106, and if false, the process proceeds to step S109 in FIG. In step S106, spatial_temporal_weight_code is determined from the value of BS. Specifically, the head (left end) 2-bit data of the BS may be copied to the variable spatial_temporal_weight_code on the memory 32. Then, the process proceeds to step S107. In step S107, UB + 2 is newly set as UB. Then, the process proceeds to step S108. In step S108, two bits are deleted from the head of the BS and shifted by two bits. Then, the process proceeds to step S109 in FIG.

At step S109 in FIG. 4, the variables macroblock_motion_forward, macroblock_motion
Check _backward and check if at least one of macroblock_motion_forward or macroblock_motion_backward is not 0. If true, step S11
0, and if false, the process proceeds to step S118 in FIG.
In step S110, the variable picture_stru in the memory 32
Examine cture and check if picture_structure is a frame structure. If true, the process proceeds to step S111, and if false, the process proceeds to step S115. Step S
At 111, the variable frame_pred_frame_dct on the memory 32 is checked to see if the value of frame_pred_frame_dct is not zero. If true, the process proceeds to step S112, and if false, the process proceeds to step S118. In step S112, the BS
Find frame_motion_type from the value of. Specifically, B
The first two bits of S are stored in the variable fram
Just copy it to e_motion_type. Then, the process proceeds to step S113. In step S113, UB + 2 is newly set as UB. Then, the process proceeds to step S114. In step S114, two bits are deleted from the head of the BS, and
Shift by bits. Then, step S118 in FIG.
Proceed to. Also, in step S115, fiel is calculated from the value of BS.
Find d_motion_type. Specifically, the first two bits of BS data are stored in the variable field_motion_typ
Just copy it to e. Then, the process proceeds to step S116. In step S116, UB + 2 is newly set as UB. Then, the process proceeds to step S117. Step S11
In step 7, two bits are deleted from the head of the BS and shifted by two bits. Then, the process proceeds to step S118 in FIG.

At step S118 in FIG. 5, the variables picture_structure, frame_pred_frame_dct, ma
Examine croblock_intra and macroblock_pattern,
structure is a frame structure and frame_pred
It is checked whether the value of _frame_dct is 0 and either macroblock_intra or macroblock_pattern is not 0. If true, the process proceeds to step S119, and if false, the process proceeds to step S121. In step S119,
Dct_type is obtained from the value of BS. In particular,
The data of the first bit of BS is stored in the variable dc on the memory 32.
Just copy it to t_type. Then, step S120
Proceed to. In step S120, UB + 1 is newly set as UB. Then, the process proceeds to step S121.

In step S121, UB bits are deleted from the head of the input binary data string, and the UB + 1 bit is set as the head. Specifically, this means that in another decoding after macroblock_modes, when the input binary data string is read from the head, it is read from the UB + 1th bit. Then, the process proceeds to step S122. In step S122, this series of processing ends.

In this manner, decoding relating to macroblock_modes is performed by, for example, a microprocessor as shown in FIG.

Here, a description will be given of how the 14 bits are taken from the input binary data string and read into the memory 32 in step S102.

As can be seen from FIG. 7, macroblock_m
The code related to odes is the longest, "the length of the longest code of macroblock_type" + "spatial_
code length of temporal_weight_code "+" frame_motion_typ
The code length of e or the code length of field_motion_type "
+ “Code length of dct_type” = 9 + 2 + 2 + 1 = 14 bits. Therefore, by reading 14 bits in step S102, all decoding can be performed even if the longest case is considered. That is, in step S102, only the number of bits in consideration of the longest case is read.

As described above, in the embodiment of the present invention, the input binary data sequence is read once more (for example, about 8 to 128 bits) in step S102, and is read into the area of the variable BS on the memory 32. Store.
Then, decoding of a plurality of data is performed from the contents of the BS, and the total number of bits (UB) used in each decoding is obtained. In step S121, the value of the total number is deleted from the head of the input binary data string. doing. Thereby, decoding of a plurality of data can be performed by reading the input binary data sequence once, and the decoding process can be performed at high speed.

Depending on the type of microprocessor, the configuration shown in FIG. 2 may further include a register file. The register file is connected to the bus line 34 in FIG. 2 and can access the memory 32 and the logical operation circuit 31. Since the reading and writing of the memory 32 is relatively slow, a register file is provided between the memory 32 and the logical operation circuit 31 for high-speed access. In this case, by making the value of the BS, that is, the data read from the input binary data string reside on the register file,
Further, high-speed processing becomes possible.

The embodiment of the present invention as described above can be applied to other portions of the MPEG2 encoded data. As another specific example, the motion vector (motion_vector) portion of the encoded data is used. Will be described with reference to FIG.

FIG. 6 shows the motion of MPEG2 encoded data.
The sign of the _vector part is shown. This motion_vector
Is a motion_code [r] [s] [0] which is first coded into a code of 1 to 11 bits. Then, f_code
If [s] [0] is not 1 and motion_code [r] [s] [0] is not 0, the motion encoded into a 1- to 8-bit code
There is _residual [r] [s] [0]. Next, when dmv is 1, there is dmvector [0] encoded in a code of 1 to 2 bits.

Next, there is motion_code [r] [s] [1] encoded into a code of 1 to 11 bits. Next, when f_code [s] [1] is not 1 and motion_code [r] [s] [1] is not 0, motion_residua encoded into a 1- to 8-bit code
There is l [r] [s] [1]. Next, when dmv is 1, 1-2
There is dmvector [1] encoded as a bit code.

When the embodiment of the present invention is applied to this part, first, the maximum possible length is 11 + 8 +
2 + 11 + 8 + 2 = 42 bits are read from the head of the input binary data string. Then, from the read data, first, motion_code [r] [s] [0] is decoded, and then, if necessary, motion_residual [r] [s] [0] is decoded. Decrypts dmvector [0] according to. further,
Decode motion_code [r] [s] [1] and then, if necessary,
Decode motion_residual [r] [s] [1] and then, if necessary, dmvector [1]. Then, the total number of bits used for the decoding is deleted from the head of the input binary data sequence. In this way, decoding of a plurality of data can be performed by reading the input binary data sequence once, and the decoding process can be performed at high speed.

The present invention is of course not limited to decoding of MPEG2 encoded data.

[0048]

According to the present invention, when decoding a binary data string obtained by compressing a plurality of original data, data corresponding to the plurality of original data is read from the binary data string. Can be obtained, the number of times of reading data can be reduced, and the decoding process can be performed at high speed.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a basic embodiment of the present invention.

FIG. 2 is a block diagram illustrating a schematic configuration of an example of hardware to which an embodiment of the present invention is applied;

FIG. 3 is a flowchart illustrating a specific example of a decoding processing procedure according to the embodiment of the present invention.

FIG. 4 is a flowchart showing a continuation of FIG. 3 of a specific example of a decoding processing procedure according to the embodiment of the present invention;

FIG. 5 is a flowchart showing a specific example of a decoding processing procedure according to the embodiment of the present invention, which is continued from FIG. 4;

FIG. 6 shows a motion vector (moti) of MPEG2 encoded data.
FIG. 14 is a diagram illustrating reference numerals of (on_vector).

FIG. 7 is a diagram illustrating codes of a macroblock mode (macroblock_modes) portion of MPEG2 encoded data.

FIG. 8 is a flowchart showing a specific example of a conventional decoding processing procedure.

FIG. 9 is a flowchart showing a continuation of FIG. 8 of a specific example of a conventional decoding processing procedure.

FIG. 10 is a flowchart showing a continuation of FIG. 9 of a specific example of the decoding processing procedure of the conventional example.

[Explanation of symbols]

31 logic operation circuit, 32 memory, 33 input / output port, 34 bus line, 35 control circuit

Claims (5)

[Claims] 1. A variable length decoding method for receiving a binary data string obtained by compressing a plurality of original data, decoding the binary data string, and restoring the plurality of original data, comprising the steps of: A data reading step of reading data corresponding to the original data of the above; from the read data, decoding the plurality of original data, obtaining the number of bits used in decoding the plurality of original data, And deleting the data from the beginning of the binary data string. 2. The data reading step reads data from the binary data sequence by a total code length when each of the codes corresponding to the plurality of original data is the longest code. The variable length decoding method according to claim 1, wherein 3. The variable length decoding method according to claim 1, wherein said decoding is performed using a microprocessor, and said read data is resident in a register file in said microprocessor. 4. When the first original data of the plurality of original data is decoded from the read data,
The first part of the read data is deleted by the number of bits used for the first original data, and shifted by the number of bits used for the first original data. The processing data created by adding meaningless data to the rear by the number of bits used, and the second original data of the plurality of original data is decoded using the processed data. 2. The variable length decoding method according to claim 1. 5. A variable length decoding apparatus which receives a binary data string obtained by compressing a plurality of original data, decodes the binary data string, and restores the plurality of original data. Memory means for reading data from the binary data string by the total code length when each code is the longest code, and storing the read data; and the reading means stored in the storage means. From the data
A decoding means for decoding the plurality of original data and obtaining the number of bits used in decoding the plurality of original data; and a data deleting means for deleting the number of used bits from the beginning of the binary data string. Variable length decoding device characterized by having