JPH1041325A - Lug lead frame - Google Patents
Lug lead frameInfo
- Publication number
- JPH1041325A JPH1041325A JP19615896A JP19615896A JPH1041325A JP H1041325 A JPH1041325 A JP H1041325A JP 19615896 A JP19615896 A JP 19615896A JP 19615896 A JP19615896 A JP 19615896A JP H1041325 A JPH1041325 A JP H1041325A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- lead frame
- semiconductor chip
- insulating adhesive
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83009—Pre-treatment of the layer connector or the bonding area
- H01L2224/83051—Forming additional members, e.g. dam structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置に用い
られるリードフレーム、特に、ＬＯＣ構造でモールドパ
ッケージが施される半導体装置に用いられるＬＯＣ用リ
ードフレームに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame used for a semiconductor device, and more particularly to a LOC lead frame used for a semiconductor device having a mold package having a LOC structure.
【０００２】[0002]
【従来の技術】高密度実装が可能なＬＯＣ（Lead On Ch
ip）構造等の半導体装置に用いられるリードフレームと
して、その片面または両面に熱可塑性や熱硬化性の接着
層の塗布された高耐熱絶縁フィルムを貼着し、この高耐
熱絶縁フィルムに半導体チップを加熱及び加圧して搭載
する方式のリードフレームがある。2. Description of the Related Art LOC (Lead On Ch
ip) As a lead frame used for a semiconductor device having a structure or the like, a high-heat-resistant insulating film coated with a thermoplastic or thermosetting adhesive layer is adhered to one or both surfaces thereof, and a semiconductor chip is attached to the high-heat-resistant insulating film. There is a lead frame that is mounted by heating and pressing.
【０００３】この方式のリードフレームの場合、高耐熱
絶縁フィルムには、通常、ポリイミド系フィルムが用い
られている。そして、リードフレームへの貼り付け方法
としては、金型による打ち抜き貼り付け方法が採用され
ている。具体的には、リール状に巻かれたフィルムを金
型で所定の形に打ち抜き、これをリードフレームに加熱
及び加圧することにより貼付している。In the case of this type of lead frame, a polyimide-based film is usually used as the high heat-resistant insulating film. As a method of attaching to a lead frame, a punching and attaching method using a die is adopted. Specifically, a film wound in a reel shape is punched into a predetermined shape by a mold, and the film is attached to a lead frame by heating and pressing.
【０００４】しかし、この方法によると、フィルムを金
型で打ち抜き、この打ち抜きフィルムをリードフレーム
の所定位置に貼付しているため、テープの使用量が多く
なるのでコストアップを招くほか、フィルムの打ち抜き
カスが生じるので材料に無駄を生じる。また、ポリイミ
ドフィルムの吸湿によって、パッケージクラックを発生
する恐れもある。However, according to this method, since the film is punched by a mold and the punched film is stuck to a predetermined position of the lead frame, the amount of tape used is increased, so that the cost is increased, and the film is punched. Since waste is generated, the material is wasted. In addition, moisture absorption of the polyimide film may cause a package crack.
【０００５】このような不具合を解消するため、ディス
ペンサを用いてリードフレーム上の半導体チップの搭載
領域（インナーリードの先端部等）にワニス状の接着剤
を塗布する方法が開発されている。特に、リードの先端
部に接着剤を塗布する場合、点塗布方式が用いられる。
この方法は、必要量をリードフレーム上に塗布するのみ
であるため、材料に余りが発生せず、かつ高価な金型も
必要としないので、製造コストを低減できるという利点
がある。In order to solve such a problem, a method has been developed in which a varnish-like adhesive is applied to a mounting region of a semiconductor chip on a lead frame (a tip portion of an inner lead or the like) using a dispenser. In particular, when an adhesive is applied to the tip of the lead, a spot application method is used.
This method has an advantage that the production cost can be reduced since only a necessary amount is applied on the lead frame, so that there is no excess in the material and no expensive mold is required.
【０００６】ワニス状の接着剤（例えば、接着性の樹脂
を溶媒で溶いたもの）の塗布は、リードフレーム上に細
管状のニードル（又はノズル）を移動させながら接着剤
をニードルからリードフレームの所定部分に空気圧によ
って吐出することにより行われる。図４は絶縁性接着剤
を塗布した従来のリードフレームを示す平面図である。
リードフレーム１は半導体チップの搭載部に集中し、且
つ両方向から対向するように配設されたインナーリード
２、このインナーリード２の夫々に接続され且つ平行す
るように設けられたアウターリード３、このアウターリ
ード３の樹脂封止後に露出する部分にリード間を連結す
るように設けられたタイバー４、タイバー４を支持する
ようにして両側に設けられる枠部５を備えている。[0006] The application of a varnish-like adhesive (for example, a solution obtained by dissolving an adhesive resin in a solvent) is performed by moving the adhesive from the needle to the lead frame while moving a thin tubular needle (or nozzle) on the lead frame. This is performed by discharging air to a predetermined portion by air pressure. FIG. 4 is a plan view showing a conventional lead frame coated with an insulating adhesive.
The lead frame 1 is concentrated on the mounting portion of the semiconductor chip and is disposed so as to be opposed from both directions. The outer lead 3 which is connected to each of the inner leads 2 and is provided so as to be parallel. A tie bar 4 is provided at a portion of the outer lead 3 that is exposed after resin sealing to connect the leads, and frame portions 5 provided on both sides to support the tie bar 4 are provided.
【０００７】このような構造のリードフレームにおい
て、インナーリード２の先端部には、絶縁性接着剤６が
上記した方法により塗布される。このようなインナーリ
ード２をヒータで加熱しながら絶縁性接着剤６上に半導
体チップを位置決め固定し、インナーリード２と半導体
チップを加熱及び加圧すれば、半導体チップは接着固定
される。In the lead frame having such a structure, an insulating adhesive 6 is applied to the tip of the inner lead 2 by the above-described method. If the semiconductor chip is positioned and fixed on the insulating adhesive 6 while heating the inner lead 2 with a heater, and the inner lead 2 and the semiconductor chip are heated and pressed, the semiconductor chip is bonded and fixed.
【０００８】[0008]
【発明が解決しようとする課題】しかし、従来の接着剤
塗布方法によると、容器にワニス状の接着剤を収納し、
これに対して空気圧により吐出を行っているが、接着剤
層の厚みを大きくすることが難しい。更に、ワニス状の
絶縁性接着剤が塗布されるリードの幅と隣接リードとの
間隔が同一或いは近い値でないと膜厚のばらつきが大き
くなる。膜厚にばらつきが生じると、半導体チップをリ
ードフレームに接着する際、厚く塗布されたリードのみ
に半導体チップが接着され、膜厚の薄いリードには半導
体チップが接着されないケースが生じる。また、ワイヤ
ボンディングが不安定になる恐れもある。However, according to the conventional adhesive applying method, a varnish-like adhesive is stored in a container,
On the other hand, ejection is performed by air pressure, but it is difficult to increase the thickness of the adhesive layer. Further, unless the width of the lead to which the varnish-like insulating adhesive is applied and the distance between adjacent leads are equal or close to each other, the variation in film thickness increases. When the thickness of the semiconductor chip is varied, when the semiconductor chip is bonded to the lead frame, the semiconductor chip is bonded only to the thickly applied lead, and the semiconductor chip is not bonded to the thin lead. In addition, wire bonding may become unstable.
【０００９】なお、各リードに膜厚が均一になるように
接着剤が塗布されたとしても、膜厚が薄い場合、半導体
チップのリードフレームへの接着条件出しが困難になる
ばかりでなく、接着時の衝撃が大きくなる。また、半導
体チップとリードフレームの距離が近すぎた場合、半導
体チップ搭載後のモールド時にレジンが間に流れ込め
ず、空洞になる恐れがあるばかりでなく、半導体装置と
しての信頼性に悪影響を与える可能性がある。[0009] Even if the adhesive is applied to each lead so as to have a uniform film thickness, when the film thickness is small, not only is it difficult to determine the bonding conditions of the semiconductor chip to the lead frame, but also the bonding is difficult. The impact at the time increases. Further, if the distance between the semiconductor chip and the lead frame is too short, the resin cannot flow into the space at the time of molding after mounting the semiconductor chip, which may not only cause a cavity but also adversely affect the reliability of the semiconductor device. there is a possibility.
【００１０】そこで本発明は、絶縁性接着剤の塗布量の
ばらつきを低減し、半導体チップの固定やワイヤボンデ
ィングが安定に行えるようにするＬＯＣ用リードフレー
ムを提供することを目的としている。SUMMARY OF THE INVENTION It is an object of the present invention to provide a LOC lead frame capable of reducing variations in the amount of insulating adhesive applied and stably fixing a semiconductor chip and stably performing wire bonding.
【００１１】[0011]
【課題を解決するための手段】上記の目的を達成するた
めに、本発明は、インナーリードの半導体チップの搭載
領域に前記半導体チップを接着固定するための絶縁性接
着剤が塗布されたＬＯＣ用リードフレームにおいて、前
記インナーリードは、前記絶縁性接着剤の塗れ広がりを
制限する溝が前記絶縁性接着剤の塗布範囲の境界に設け
た構成にしている。SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a LOC for an LOC coated with an insulating adhesive for bonding and fixing the semiconductor chip to a mounting area of the semiconductor chip of an inner lead. In the lead frame, the inner lead has a configuration in which a groove for restricting spread of the insulating adhesive is provided at a boundary of an application range of the insulating adhesive.
【００１２】この構成によれば、インナーリードに絶縁
性接着剤を塗布した際、塗布後の絶縁性接着剤が塗れ広
がろうとしても、溝によって塗布面に傾斜面が形成され
ているために接着剤の流れは溝で停止する。この結果、
塗布膜を厚く且つ均一に形成することができ、半導体チ
ップの固定やワイヤボンディングが安定に行えるように
なる。According to this structure, when the insulating adhesive is applied to the inner lead, even if the applied insulating adhesive tends to spread, the inclined surface is formed on the application surface by the groove. The flow of the adhesive stops at the groove. As a result,
The coating film can be formed thickly and uniformly, and the semiconductor chip can be fixed and the wire bonding can be stably performed.
【００１３】前記溝は、前記絶縁性接着剤が塗布される
部分のリード幅に応じて設置位置を変えることができ
る。この構成によれば、リードの形状やリード間隔が不
揃いであっても、これに応じて溝を設ければ（例えば、
リード幅が広い時にはリード長さ方向の塗布長さを短く
し、リード幅が狭い時には塗布長さを長くする）、各リ
ードに均一な厚みに膜厚を形成することができる。The position of the groove can be changed according to the lead width of the portion where the insulating adhesive is applied. According to this configuration, even if the shapes and the lead intervals of the leads are not uniform, if the grooves are provided in accordance therewith (for example,
When the lead width is wide, the coating length in the lead length direction is shortened, and when the lead width is narrow, the coating length is lengthened), so that a uniform film thickness can be formed on each lead.
【００１４】前記溝は、半円形の断面形状を有する構造
にすることができる。この構成によれば、加工が容易で
ありながら、リードの破断を生じ難くくすることができ
る。The groove may have a semicircular cross section. According to this configuration, the breakage of the lead can be made hard to occur while the processing is easy.
【００１５】[0015]
【発明の実施の形態】以下、本発明の実施の形態につい
て図面を基に説明する。図１は本発明によるＬＯＣ用リ
ードフレームを示す平面図である。リードフレーム１０
は、インナーリード１１及びアウターリード１２を主体
に構成されている。インナーリード１１は半導体チップ
の搭載領域に向けて両側から対向するように２列に平行
配設され、他端はアウターリード１２に向かうにつれて
拡がりを持つように展開し、終端はアウターリード１２
に連結されている。アウターリード１２は一定間隔をも
って平行配置され、端部がタイバー１３で相互に結合さ
れている。更に、インナーリード１１の先端部には、絶
縁性接着剤１４が塗布される領域に隣接させて、リード
に直交する方向に溝１５が形成されている。なお、１６
は枠部である。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing a LOC lead frame according to the present invention. Lead frame 10
Is mainly composed of an inner lead 11 and an outer lead 12. The inner leads 11 are arranged in two rows in parallel so as to face the mounting area of the semiconductor chip from both sides, and the other end is developed so as to expand toward the outer leads 12.
It is connected to. The outer leads 12 are arranged in parallel at regular intervals, and their ends are connected to each other by tie bars 13. Further, a groove 15 is formed at the tip of the inner lead 11 in a direction perpendicular to the lead, adjacent to a region where the insulating adhesive 14 is applied. Note that 16
Is a frame portion.
【００１６】図２は、図１におけるII−II断面図を示し
ている。インナーリード１１の先端部には絶縁性接着剤
１４が塗布されるが、この絶縁性接着剤１４の後端（ア
ウターリード１２側）に隣接させて、溝１５が半円断面
形状に設けられている。この溝１５は、ワニス状樹脂の
表面張力を利用することにより、塗布されたワニス状樹
脂がリード表面を塗れ広がるのを制限するために設けら
れるもので、溝にワニス状樹脂を溜め込むことにより塗
れ広がりを防止するものではない。FIG. 2 is a sectional view taken along the line II-II in FIG. An insulating adhesive 14 is applied to the tip of the inner lead 11, and a groove 15 is provided in a semicircular cross-sectional shape adjacent to the rear end of the insulating adhesive 14 (outer lead 12 side). I have. The groove 15 is provided to limit the spread and spread of the applied varnish resin on the lead surface by using the surface tension of the varnish resin. It does not prevent spread.
【００１７】このため、溝１５の形状で最も重要なこと
は角度であり、急峻な角度を有するほど表面張力の効果
を高め、塗れ広がり防止の効果は高めることができる。
また、溝１５を効果的に使用する方法として、ワニス状
の絶縁性接着剤にフィラー等を混入させ、ワニス状の絶
縁性接着剤の表面張力を増加させることも有効である。For this reason, the most important thing in the shape of the groove 15 is the angle. The steeper angle increases the effect of the surface tension and the effect of preventing the spread of the paint can be enhanced.
As a method of effectively using the groove 15, it is also effective to mix a filler or the like into the varnish-like insulating adhesive to increase the surface tension of the varnish-like insulating adhesive.
【００１８】このように、リード上に絶縁性接着剤１４
の塗れ広がりを制限する溝１５を設けたことにより、絶
縁性接着剤１４が塗布されるリードの間隔が同一でなく
とも均一な膜厚を得ることができる。この結果、半導体
チップの固定やワイヤボンディングが安定して行えるよ
うになり、半導体装置の信頼性を向上させることが可能
になる。また、このような特性のリードフレームを低価
格に製造することができる。As described above, the insulating adhesive 14 is provided on the leads.
By providing the groove 15 for limiting the spread of the coating, a uniform film thickness can be obtained even if the intervals between the leads to which the insulating adhesive 14 is applied are not the same. As a result, the semiconductor chip can be fixed and the wire bonding can be stably performed, and the reliability of the semiconductor device can be improved. Further, a lead frame having such characteristics can be manufactured at low cost.
【００１９】図３は本発明によるＬＯＣ用リードフレー
ムの他の実施の形態を示す平面図である。図１のリード
フレームは、絶縁性接着剤１４が塗布されるリードの形
状（幅等）及び間隔が同一（又は近似）であったが、図
３のリードフレームは絶縁性接着剤１４が塗布されるリ
ードの形状（幅等）及び間隔が同一（又は近似）でない
場合である。すなわち、インナーリード１１のうち、リ
ード幅が広いリードには先端から近い位置に溝１５を設
ける。つまり、溝１５を設ける位置（リード先端面から
の距離）がリード幅に応じて異なる構成にしている。こ
のような構成により、均一で厚い膜厚の接着剤層を形成
することができる。FIG. 3 is a plan view showing another embodiment of the LOC lead frame according to the present invention. The lead frame of FIG. 1 has the same shape (width or the like) and the interval of the leads to which the insulating adhesive 14 is applied (or similar), but the lead frame of FIG. 3 has the insulating adhesive 14 applied. This is a case where the lead shapes (width and the like) and the intervals are not the same (or approximate). That is, among the inner leads 11, a groove 15 is provided at a position close to the tip of a lead having a wide lead width. That is, the position where the groove 15 is provided (the distance from the lead tip surface) is different depending on the lead width. With such a configuration, an adhesive layer having a uniform and thick film thickness can be formed.
【００２０】[0020]
【実施例】次に、本発明の実施例について説明する。絶
縁性接着剤１４として、ガラス転移温度が２２０℃の熱
可塑性の絶縁性接着剤を溶媒でワニス状に溶かしたもの
を用いた。その粘度は１０，０００ｃｐであり、樹脂分
は２０％である。リードフレーム１０には、４２％Ｎｉ
−Ｆｅ合金、厚さ０．１５ｍｍ、リード先端の幅、及び
間隔は０．３ｍｍのものを用い、溝１５はフレームの約
１／２の深さをエッチングにより形成した。そして、リ
ードフレーム１０への接着剤塗布は、ワニス状の絶縁性
接着剤１４をディスペンサを用いて行った。Next, an embodiment of the present invention will be described. As the insulating adhesive 14, a material obtained by dissolving a thermoplastic insulating adhesive having a glass transition temperature of 220 ° C. in a varnish shape with a solvent was used. Its viscosity is 10,000 cp and the resin content is 20%. The lead frame 10 has 42% Ni
The groove 15 was formed by etching to a depth of about の of the frame by using an Fe alloy, a thickness of 0.15 mm, a width of a lead tip and a gap of 0.3 mm. Then, the application of the adhesive to the lead frame 10 was performed using a varnish-like insulating adhesive 14 using a dispenser.
【００２１】比較例として、図４に示す従来構成による
溝無しリードフレームを用意し、このインナーリード２
にワニス状の絶縁性接着剤を塗布した。その結果、リー
ドの最先端部に塗布してもワニス状絶縁性接着剤は塗れ
広がってしまい、溶媒の乾燥後に得られた膜厚は約１５
μｍであった。一方、図１に示す溝付きの本発明による
リードフレームにワニス状の絶縁性接着剤を比較例と同
一量に塗布した。その結果、リード先端からの距離が比
較例のリードフレームの約１／２のところで塗布した接
着剤を止めることができた。そして、膜厚は比較例の約
２倍の３０μｍを得ることができた。As a comparative example, a grooveless lead frame having a conventional structure shown in FIG.
Then, a varnish-like insulating adhesive was applied. As a result, the varnish-like insulating adhesive spreads even when applied to the forefront portion of the lead, and the film thickness obtained after drying the solvent is about 15
μm. On the other hand, a varnish-like insulating adhesive was applied to the grooved lead frame shown in FIG. 1 in the same amount as in the comparative example. As a result, the applied adhesive could be stopped when the distance from the lead tip was about 1/2 of the lead frame of the comparative example. Then, a film thickness of 30 μm, which is about twice that of the comparative example, could be obtained.
【００２２】なお、溝１５は、加工が容易でリードの破
断を招き難い半円形の断面形状にしたが、これに限定さ
れるものではなく、例えば、Ｖ字形、Ｗ字形、台形、四
角形等の断面形状であってもよい。また、溝１５は、リ
ードを完全に横断するように形成したが、点線状態又は
一部に溝を有しない状態で設けてもよい。また、平行さ
せて２本以上を設けることもできる。さらに、溝１５は
直線状態のほか、波形、ギザギザ状等であってもよい。The groove 15 has a semicircular cross-sectional shape that is easy to work and hardly causes breakage of the lead. However, the present invention is not limited to this. It may have a cross-sectional shape. Although the groove 15 is formed so as to completely cross the lead, the groove 15 may be provided in a dotted line state or a state in which a part of the groove is not provided. Also, two or more can be provided in parallel. Further, the groove 15 may have a waveform, a jagged shape, or the like in addition to a linear state.
【００２３】[0023]
【発明の効果】以上より明らかな如く、本発明によれ
ば、絶縁性接着剤が塗布されるインナーリードは、絶縁
性接着剤の塗布範囲の境界に溝を設けるようにしたの
で、塗布後の絶縁性接着剤が塗れ広がろうとしても、溝
によって塗布面に傾斜面が形成されているために接着剤
の流れは溝で停止させることができ、各リードには塗布
膜を厚く且つ均一に形成でき、半導体チップの固定やワ
イヤボンディングが安定に行えるようになる。As is apparent from the above, according to the present invention, the inner lead to which the insulating adhesive is applied is provided with a groove at the boundary of the application range of the insulating adhesive. Even if the insulating adhesive is applied and spreads, the flow of the adhesive can be stopped at the groove because the inclined surface is formed by the groove, and the coating film is thick and uniform on each lead. Thus, the semiconductor chip can be fixed and the wire bonding can be stably performed.
【図１】本発明によるＬＯＣ用リードフレームを示す平
面図である。FIG. 1 is a plan view showing a LOC lead frame according to the present invention.
【図２】図１におけるII−II断面図である。FIG. 2 is a sectional view taken along the line II-II in FIG.
【図３】本発明におけるＬＯＣ用リードフレームの他の
実施の形態を示す平面図である。FIG. 3 is a plan view showing another embodiment of the LOC lead frame according to the present invention.
【図４】絶縁性接着剤を塗布した従来のリードフレーム
を示す平面図である。FIG. 4 is a plan view showing a conventional lead frame coated with an insulating adhesive.
１０ リードフレーム １１ インナーリード １２ アウターリード １４ 絶縁性接着剤 １５ 溝 DESCRIPTION OF SYMBOLS 10 Lead frame 11 Inner lead 12 Outer lead 14 Insulating adhesive 15 Groove
───────────────────────────────────────────────────── フロントページの続き (72)発明者 米本 隆治 茨城県土浦市木田余町3550番地 日立電線 株式会社システムマテリアル研究所内 (72)発明者 吉岡 修 茨城県土浦市木田余町3550番地 日立電線 株式会社システムマテリアル研究所内 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Ryuji Yonemoto 3550 Kida Yomachi, Tsuchiura City, Ibaraki Prefecture Within Hitachi Cable System Materials Research Laboratories (72) Inventor Osamu Yoshioka 3550 Kida Yomachi, Tsuchiura City, Ibaraki Hitachi Cable Inside System Materials Laboratory
Claims (3)
に前記半導体チップを接着固定するための絶縁性接着剤
が塗布されたＬＯＣ用リードフレームにおいて、 前記インナーリードは、前記絶縁性接着剤の塗れ広がり
を制限する溝が前記絶縁性接着剤の塗布範囲の境界に設
けられていることを特徴とするＬＯＣ用リードフレー
ム。1. A LOC lead frame in which an insulating adhesive for bonding and fixing the semiconductor chip is applied to a mounting area of the semiconductor chip of the inner lead, wherein the inner lead is spread by applying the insulating adhesive. Characterized in that a groove for limiting the distance is provided at the boundary of the application range of the insulating adhesive.
部分のリード幅に応じて設置位置を変えることを特徴と
する請求項１記載のＬＯＣ用リードフレーム。2. The LOC lead frame according to claim 1, wherein the position of the groove is changed according to a lead width of a portion to which the insulating adhesive is applied.
を特徴とする請求項１又は２記載のＬＯＣ用リードフレ
ーム。3. The LOC lead frame according to claim 1, wherein said groove has a semicircular cross-sectional shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19615896A JPH1041325A (en) | 1996-07-25 | 1996-07-25 | Lug lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19615896A JPH1041325A (en) | 1996-07-25 | 1996-07-25 | Lug lead frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1041325A true JPH1041325A (en) | 1998-02-13 |
Family
ID=16353179
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19615896A Pending JPH1041325A (en) | 1996-07-25 | 1996-07-25 | Lug lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1041325A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2020077747A (en) * | 2018-11-07 | 2020-05-21 | 新光電気工業株式会社 | Lead frame, semiconductor device, and lead frame manufacturing method |
-
1996
- 1996-07-25 JP JP19615896A patent/JPH1041325A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2020077747A (en) * | 2018-11-07 | 2020-05-21 | 新光電気工業株式会社 | Lead frame, semiconductor device, and lead frame manufacturing method |
| US11791250B2 (en) | 2018-11-07 | 2023-10-17 | Shinko Electric Industries Co., Ltd. | Lead frame, semiconductor device, and lead frame manufacturing method |
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