JPH103449A - Data transfer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To vary the number of transfer data and also to decide the number of data by providing a 2nd data transfer device which counts up an address counter when the transmitted contents are the data. SOLUTION: A 1st data transfer device 30 compares the preceding address with the present address which are received from a bus master 10. Then the device 30 outputs no address to a local bus 40 and unilaterally outputs data when those compared addresses continuously vary. A 2nd data transfer device 50 judges whether the signal sent via the bus 40 is an address or data. If the signal is judged to be an address, this address is loaded. Meanwhile, the address is updated if the data are judged. When the data are received (this case can be judged by the data strobe), these data are counted up. Thus, the coincidence is secured between the counter length and the address length, and the number of block transfer data is never limited. Therefore, the data transfer efficiency is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data transfer system for transferring digital data between modules in a measurement or control system including a computer, and more particularly to an improvement in data transfer efficiency.

[0002]

2. Description of the Related Art In a data transfer system which has been well known, the address width and the data width tend to be longer in recent years, but in accordance with this, the demand for downsizing of hardware is also increasing.

[0003]

Incidentally, in the conventional data transfer system, there are some lines in which the address and the data are separate lines (signal lines). When the width of the address and the data becomes long, each module is connected. The number of signal lines also increases, which hinders miniaturization.

[0004] Some conventional data transfer devices employ a system in which address and data are multiplexed and data is transferred using a common address and data line. In this method, although the number of signal lines can be reduced, the overall transfer speed is reduced because addresses and data are sent alternately. As a method for solving this, there is a block transfer method for continuously transmitting only data when addresses are continuous.

However, in this transfer method,
Since the number of data is fixed, if the number of data having continuous addresses is smaller than the fixed number of data, it is necessary to send useless data, and there is a disadvantage that transfer efficiency is poor.

SUMMARY OF THE INVENTION In view of the foregoing, it is an object of the present invention to provide a data transfer apparatus capable of changing the number of data to be transferred and determining the number of data to increase the data transfer efficiency in block transfer. It is in.

[0007]

According to the present invention, there is provided a data transfer system in which a bus master and a bus slave are connected by a local bus and data is transferred via the local bus. And is connected to the bus master side, compares the previous address from the bus master with the current address, determines whether the address is continuously changing, and does not continuously change the address. In this case, the address and data are output to the local bus.
A first data transfer device that unidirectionally outputs data without outputting an address to a bus, and whether the content transmitted via the local bus is an address or data connected to the bus slave side And a second data transfer device that counts up an address counter when the data is data and outputs the address as it is when the data is an address.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 1 is a configuration diagram showing one embodiment of a data transfer system according to the present invention. In FIG. 1, reference numeral 10 denotes a bus master, such as a central processing unit (CPU) module. Reference numeral 30 denotes a bus via the host bus 20.
The first data transfer device 50 connected to the master 10 is connected to the first data transfer device 30 via the local bus 40.
A second data transfer device 70 connected to the second data transfer device 50 is connected to the second data transfer device 50 via the bus 60. The bus slave 70 is, for example, a memory module or the like. The present invention aims to reduce the number of signal lines of the local bus 40 and improve the efficiency of data transfer transferred via the local bus 40.

The first data transfer device 30 is a device that compares the previous address from the bus master 10 with the current address and determines whether or not to output an address based on the result of the comparison. The second data transfer device 50 determines whether the signal transmitted via the local bus 40 is an address or data, updates the address in the case of data, and loads the address in the case of an address. It is a device to do.

The first data transfer device 30 will be described in more detail with reference to FIG. In FIG. 2, reference numeral 31 denotes a latch circuit for latching the previous address, and reference numeral 32 denotes a comparator for comparing whether a value obtained by adding 1 to the previous address matches the current address. Reference numeral 33 denotes a first control circuit which outputs a result of the comparator 32, a write signal of the host bus,
In response to the address strobe signal and the data strobe signal, enable control of the address buffer 36 and transmission direction (DIRECTION) of the data transceiver 37 are performed.
And enable control.

Reference numeral 34 denotes a second control circuit for controlling the timing of the address strobe and data strobe of the local bus, and reference numeral 35 denotes an acknowledgment for generating an acknowledgment signal to be output to the host bus based on the data acknowledgment signal from the local bus. It is a control circuit.

FIG. 3 is a block diagram showing the details of the second data transfer device 50. In the figure, reference numeral 51 denotes a counter for supplying an address. When an address comes to an address / data line (determined by an address strobe), the address is loaded. When data comes (a data strobe can be determined), a counter is counted. By increasing the counter length to the address length in the circuit to be increased, the number of block transfer data is not limited.

Reference numeral 52 denotes a control circuit which receives a data strobe, an address strobe and a write signal of a local bus and transmits the data in a transmission direction (DIRE) of a data transceiver 53.
CTION) and enable control.

The operation in such a configuration will be described below with reference to the timing charts of FIGS. When data is transferred (or fetched) to a module connected to the local bus 40 (corresponding to the write cycle in FIG. 4), the address from the host bus 20 is compared with the previous address from the host bus 20. Then, the operation is divided into the following operations.

[0015] 1) address may not be continuously (address from A _i to A _j, or if from A _{j + 1} change to the A _k) is output to the address and the address strobe local bus 40. The data and the data strobe are output to the local bus 40 (data fetch). 2) When addresses are continuous (when the address changes from A _j to A _{j + 1} ) Data and data strobe are output to the local bus 40 (data fetch).

The acknowledgment is a signal returned from the slave side to the master side, and notifies the end timing of the cycle. In the read cycle, the operation is separated in the same manner as described above depending on whether or not addresses are continuous. Each operation is the same as that in the case of the write cycle, and the description is omitted.

The following table shows a comparison of the number of data transfers between the transfer method of the present invention and the conventional transfer method.

It is to be noted that the above description of the present invention has been presented by way of illustration and example only of a particular preferred embodiment. Thus, it is apparent that the present invention can be modified and changed in many ways without departing from the essence thereof.

[0019]

As described above, according to the present invention, the data transfer efficiency on the local bus between the first data transfer device and the second data transfer device can be easily increased. The number of signal lines of the local bus can be easily reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of a data transfer system according to the present invention.

FIG. 2 is a configuration diagram of a first data transfer device;

FIG. 3 is a configuration diagram of a second data transfer device.

FIG. 4 is a timing chart of a write cycle.

FIG. 5 is a timing chart of a read cycle.

[Explanation of symbols]

 Reference Signs List 10 bus master 20 host bus 30 first data transfer device 31 latch circuit 32 comparator 33 first control circuit 34 second control circuit 35 acknowledge control circuit 36 buffer 37 transceiver 40 local bus 50 second data Transfer device 51 counter 52 control circuit 53 transceiver 60 bus

Claims (1)

[Claims] 1. A data transfer system for connecting a bus master and a bus slave by a local bus and performing data transfer via the local bus, wherein the data transfer system is connected to the bus master and is connected to the bus master. The previous address is compared with the current address to determine whether the address changes continuously.If the address does not change continuously, the address and data are output to the local bus, and the address is A first data transfer device that unidirectionally outputs data without outputting an address to the local bus when the address changes to a local bus, and a content that is connected to the bus slave side and transmitted via the local bus. Judge whether it is an address or data, and if it is data, count up the address counter. Data transfer system characterized by comprising a second data transfer device that outputs the.