JPH10341261A - Offset elimination circuit and offset eliminating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate an offset of a reference level independently of whether or not serial data are DC-balanced. SOLUTION: Serial data are given to a PLL circuit 2, a DFF 7 and a phase comparator 8 via a receiver 1. The PLL circuit 2 generates reception clock synchronously with output data from the receiver 1 and gives it to the phase comparator 8. The phase comparator 8 samples the received clock according to output data from the receiver 1 to detect a phase difference of the data and it is fed to a charge pump circuit 9. The charge pump circuit 9 converts the phase difference from the phase comparator 8 into a voltage and given to the receiver 1 via a low pass filter 10 as a compensation signal. The receiver 1 compensates the input offset according to the compensation signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an offset removing circuit and an offset removing method, and more particularly to, for example, generating a clock from data obtained by comparing serial data with a predetermined reference level, and generating a data according to the clock. The present invention relates to an offset elimination circuit and an offset elimination method that can remove an offset of a reference level that causes jitter and the like when sampling is performed.

[0002]

2. Description of the Related Art FIG. 6 shows a case where a clock is generated from serial data (Din), and serial data is sampled in accordance with the clock to obtain received data (R).
2 shows an example of a configuration of a conventional receiving apparatus that obtains xData).

[0003] Serial data is received by a receiver (Recei).
ver) 61. The receiver 61 amplifies the serial data and outputs the data based on a magnitude relationship with a predetermined reference level. The data output from the receiver 61 is supplied to a PLL (Phase Lock Loop) circuit 2 and a DFF (D flip-flop) 7.

The PLL circuit 2 includes a phase comparator (PD) 3,
Low-pass filter (LPF) 4, voltage controller (VC0)
5 and a frequency divider (# 2) 6 to generate a clock (reception clock) (RxClk) synchronized with the serial data from the receiver 61.

That is, the serial data from the receiver 61 and the output of the frequency divider 6 are supplied to the phase comparator 3, and the phase comparator 3 compares these phases. The comparison result is supplied to the low-pass filter 4. The low-pass filter 4 includes the phase comparator 3
, And outputs the filtering result to the voltage controller 5. The voltage controller 5 generates a voltage corresponding to the output of the low-pass filter 4,
Output to The frequency divider 6 divides the output cycle of the voltage controller 5 by, for example, twice and supplies the frequency to the phase comparator 3.
As a result, the phase difference between the output of the receiver 61 and the output of the frequency divider 6 input to the phase comparator 3 from the voltage controller 5 becomes zero.
Is output as a reception clock.
This reception clock is supplied to the DFF 7.

[0006] Serial data output from the receiver 61 is supplied to an input terminal (D) of the DFF 7, and a reception clock output from the PLL circuit 2 (voltage controller 5) is supplied to a clock terminal (CK) thereof. Supplied. DFF
At 7, the serial data supplied to the input terminal from the receiver 61 is sampled in accordance with the reception clock from the PLL circuit 2 supplied to the clock terminal, that is, the serial data from the receiver 61 is received. It is latched at the timing of the clock, and is output from its output terminal (Q) as received data (RxData).

In the above-described receiving apparatus, when there is no offset in the reference level used in the receiver 61, the output is as shown in FIG.

That is, FIG. 7A shows the relationship between the reference level without offset and the serial data, and FIG. 7B shows the output of the receiver 61 in that case. The receiver 61 outputs an H level when the serial data is equal to or higher than a predetermined reference level, and outputs an L level when the serial data is equal to or lower than the predetermined reference level. As shown in FIG. 3B, a pulse having a constant pulse width is output. PL
The L circuit 2 generates a reception clock synchronized with the rising edge and the falling edge of the data (pulse).

[0009]

The receiver 6
The characteristics of the parts that make up 1 do not exactly match the ideal ones, and therefore the predetermined reference level generally includes an offset.

[0010] For example, as shown on the left side of FIG. 8A, when there is an offset for raising the reference level (hereinafter referred to as a plus offset as appropriate), the output of the receiver 61 is shown in FIG. It becomes as shown in. That is, in this case, the output of the receiver 61 has a rising edge
It appears at a position later than the original timing (the portion shown by the thin line in FIG. 7B), and the falling edge appears at a position earlier than the original timing. On the other hand, for example, as shown on the right side of FIG. 8A, when there is an offset for lowering the reference level (hereinafter, appropriately referred to as a negative offset), the output of the receiver 61 is as shown in FIG. The rising edge
It appears at a position advanced from the original timing and a falling edge appears at a position delayed from the original timing.

As described above, in the receiving device, since the PLL circuit 2 generates a reception clock synchronized with the output of the receiver 61, the offset of the reference level appears as jitter of the received data. This jitter increases in proportion to the magnitude of the offset, for example, as shown in FIG. Further, since the jitter has the same frequency as that of the serial data, it is difficult to perform compensation in the PLL circuit 2.

On the other hand, the slew rate of serial data cannot be increased so much due to problems such as unnecessary radiation.
It is preferable that the amplitude of the serial data is as small as possible from the viewpoint of radiation and power consumption. Therefore, as the serial data rate increases, jitter due to the offset of the reference level becomes more problematic. That is, as the serial data rate increases, bit errors due to jitter increase.

By the way, in order to reduce the size of the circuit, FIG.
Is a CMOS (Complementary)
High-speed communication using such a CMOS receiver is expected to increase in importance in the future, so jitter, that is, offset of a reference level, is expected. It is very important to remove (reduce).

Therefore, some CMOS receiving devices stop the receiving operation and compensate for the offset. In a receiving apparatus that needs to operate continuously, offset compensation is performed by devising its layout. However, it has generally been the limit to reduce the offset to about 20 mV only by devising the layout.

Therefore, as a method of further reducing the offset, for example, Dao-Long Chen, Michael O. Baker, FP 1
5.3: A 1.25Gb / s, 460mW CMOS Transceiver for Sirial
DataCommunication, 1997 IEEE International Solid-S
Figure 1 for the tate Circuits Conference, pp242-243, etc.
0 is disclosed. In this receiving apparatus, when serial data is DC-balanced such as an 8B / 10B converted code,
Utilizing this, the offset is continuously compensated. That is, as shown in FIG.
If there is a positive offset, the period during which the data is at the H level is shorter than the period during which the data is at the L level. Conversely, if there is a negative offset, the data is at the H level. Is longer than the L level. In the receiver shown in FIG. 10, the difference between the H-level period and the L-level period is determined by a charge pump and a low-pass filter.
, And is fed back to a buffer (Buffer Stage) corresponding to a part of the receiver 61 to remove the offset.

However, in the receiving apparatus of FIG. 10, since it is assumed that the serial data is DC-balanced, it is difficult to remove the offset when serial data that is not DC-balanced is input. Met. Here, in practice, serial data that is not correctly DC-balanced is often used.

SUMMARY OF THE INVENTION The present invention has been made in view of such a situation, and is capable of removing the reference level offset (reduced from the prior art) regardless of whether the serial data is DC-balanced. Is what you do.

[0018]

According to a first aspect of the present invention, there is provided an offset removing circuit for outputting data based on a magnitude relation between an input signal and a predetermined reference level, and generating a clock from the data. Means, detecting means for detecting a phase difference between data and clock, and removing means for removing an offset included in a predetermined reference level based on the phase difference detected by the detecting means. .

According to a third aspect of the present invention, there is provided an offset removing method,
Based on the magnitude relationship between the input signal and a predetermined reference level,
Data is output, a clock is generated from the data, a phase difference between the data and the clock is detected, and an offset included in a predetermined reference level is removed based on the phase difference.

In the offset removing circuit according to the first aspect, the output means outputs data based on a magnitude relationship between the input signal and a predetermined reference level, and the generating means generates a clock from the data. Has been made. The detecting means detects a phase difference between the data and the clock, and the removing means removes an offset included in a predetermined reference level based on the phase difference detected by the detecting means.

According to a third aspect of the present invention, there is provided an offset removing method, wherein data is output based on a magnitude relationship between an input signal and a predetermined reference level, a clock is generated from the data, and a phase difference between the data and the clock is determined. Detected, and based on the phase difference, an offset included in a predetermined reference level is removed.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below. Before that, the principle of the present invention will be described with reference to FIG.

FIG. 1A shows serial data as an input signal, and FIG. 1B shows data output from a conventional receiver 61 when the serial data is input. . FIG. 3C shows a reception clock. Note that FIG. 1A or FIG.
8 is the same as FIG. 8A or FIG. 8B, respectively.

Now, in the conventional receiver 61, FIG.
When the serial data of (A) is input, the reception clock (FIG. 1) is generated at the timing of the rising edge and the falling edge of the data (FIG. 1 (B)) output therefrom.
Consider sampling (C)).

When there is no offset in the reference level, when the reception clock is sampled at the timing of the rising edge and the falling edge of the data output from the conventional receiver 61, the rising edge portion of the reception clock is sampled at any timing. Is done.

On the other hand, when there is an offset in the reference level, when the reception clock is sampled at the timing of the rising edge and the falling edge of the data output by the conventional receiver 61, the portion indicated by a circle in FIG. Sampled. That is, when there is a positive offset, at the rising edge timing of the data output from the receiver 61, the H level of the portion a that is delayed from the position where sampling should be originally performed is originally at the falling edge timing. The L level of the portion b that is ahead of the position to be sampled is respectively sampled. On the other hand, when there is a negative offset, the receiver 6
1 at the rising edge timing of the data output, the L level of the portion c that is ahead of the position to be sampled is lower than that of the portion d that is later than the sampling position at the falling edge timing. Each H level is sampled.

As described above, when the reception clock is sampled at the timing of the rising edge or the falling edge of the data output from the conventional receiver 61, the sampling position should be originally sampled in accordance with the offset. Deviates from position. The displacement of the sampled position represents the phase difference between the rising edge or falling edge of the data output from the conventional receiver 61 and the rising edge of the received clock, and this phase difference corresponds to the offset. Therefore, if the reference level is compensated so that the phase difference becomes 0, the offset can be removed.

FIG. 2 shows a configuration example of an embodiment of a receiving apparatus for removing an offset based on the above principle. In the figure, parts corresponding to those in FIG. 6 are denoted by the same reference numerals, and hereinafter,
The description is omitted as appropriate. That is, in this receiving apparatus, a receiver 1 (removal means) is provided instead of the receiver 61, and a phase comparator (PD) 8 (detection means), a charge pump circuit (CP) 9, and a low-pass filter (LPF) The configuration is basically the same as that of the receiving apparatus of FIG. 6 except that a receiving apparatus 10 is newly provided.

The receiver 1, like the receiver 61, amplifies the serial data (Din) supplied thereto,
In addition to outputting data based on the magnitude relationship with a predetermined reference level, an offset included in the predetermined reference level is output to a compensation signal (Vadju) from the low-pass filter 10.
st). The phase comparator 8 includes data output from the receiver 1 (hereinafter, appropriately referred to as output data) and the PLL circuit 2 (generation means).
Is supplied with the received clock (RxClk), where the received clock is sampled according to the output data to detect the phase difference between them as described with reference to FIG. It has been made to be. The phase difference between the received clock and the output data is supplied to the charge pump circuit 9. The charge pump circuit 9 converts the phase difference from the phase comparator 8 into a voltage and supplies the voltage to the low-pass filter 10. The low-pass filter 10
The output of the charge pump circuit 9 is filtered and supplied to the receiver 1 as a compensation signal.

The receiving apparatus shown in FIG.
S.

Next, the operation will be described.

The serial data is transmitted via the receiver 1
It is supplied to the PLL circuit 2, the DFF 7, and the phase comparator 8. In the PLL circuit 2, as described above, the receiver 1
A reception clock synchronized with the output data from is generated,
It is supplied to the clock terminal of DFF7. In DFF7,
The output data of the receiver 1 supplied to the input terminal is
The signal is sampled according to the reception clock from the PLL circuit 2 supplied to the clock terminal, and is output from the output terminal (Q) as reception data.

On the other hand, the received clock output from the PLL circuit 2 is also supplied to the phase comparator 8. In the phase comparator 8, the received clock is sampled in accordance with the output data, whereby the phase difference between them is detected and supplied to the charge pump circuit 9. In the charge pump circuit 9, the phase difference from the phase comparator 8 is converted into a voltage,
The signal is supplied to the receiver 1 as a compensation signal through the low-pass filter 10. In the receiver 1, the reference level is changed in accordance with the compensation signal, whereby the offset contained therein is removed.

FIG. 3 shows an example of the configuration of the receiver 1 of FIG.

[0035] In FIG. 2, the serial data supplied to the receiver 1 (Din) includes a common-mode input voltage v _a, and a differential input voltage v _d, to represent respectively, V _in + = v _a +
a first signal represented by v _d / 2, and V _in− = v _a −v _d / 2
And the first signal Vin _{+
Alternatively,} the second signal _Vin- is inputted to the gate (G) of the FET (field effect transistor) 21 or 22 respectively. The sources (S) of the FETs 21 and 22 are both grounded, and the respective drains (D) are connected to the drains of the FETs 23 and 24.

The sources of the FETs 23 and 24 are both connected to the power supply Vcc, and the respective gates are provided with NOT gates 25 or 26. The NOT gates 25 and 26 are connected, and the connection point is connected to the connection point between the drain of the FET 22 and the drain of the FET 24.

Here, the above-described FETs 21 to 24 and NOT gates 25 and 26 constitute a differential amplifier 31.

The connection point between the drain of the FET 21 and the drain of the FET 22 is connected to the gate of the FET 28. The drain of the FET 28 is connected to the drain of the FET 27, and the source of the FET 27 is connected to the power supply Vcc. The gate of the FET 27 has NO
A T gate 30 is provided.
Is connected to the gate of the FET 28.

The source of the FET 28 is connected to the drain of the FET 29, and the source of the FET 29 is grounded. The gate of the FET 29 is supplied with a compensation signal (Vadjust) from the low-pass filter 10.

Here, FETs 27 and 28 and NO
The T gate 30 constitutes the inverter 32, and inverts the output of the differential amplifier 31 and outputs the inverted signal. The FET 29 is connected to the F
The gate voltage when the ETs 27 and 29 are turned on / off is shifted in accordance with the compensation signal, so that the offset of the reference level is removed (reduced).

In FIG. 3, for example, N
FE provided with OT gates 25 to 27 respectively
T23, 24, or 27 is a P-channel MOS, and the other FETs 21, 22, 28, and 29 are N-channel MOSs.

In the receiver 1 configured as described above,
In the differential amplifier 31, the first signal Vin ₊ and the second signal Vin ₊
Serial data composed of signal V _in- of the differential amplifier is supplied to the inverter 32. In the inverter 32, the output of the differential amplifier 31 is inverted and output. The gate voltage when the FETs 27 and 28 constituting the inverter 32 are turned on / off is the reference level.
V _in + = V _in- equal to its V _{in +} and V _in- at the time of.

On the other hand, the FET 29 is a low-pass filter 1
It operates according to the compensation signal from 0, thereby turning on / off the FETs 27 and 28 constituting the inverter 32.
The gate voltage at the time of turning off, that is, the reference level is shifted according to the compensation signal. Thereby, the inverter 3
2 outputs data in which the offset of the reference level is compensated.

FIG. 4 shows a configuration example of the phase comparator 8 of FIG.

Unlike the phase comparator 3 constituting the PLL circuit 2, the phase comparator 8 samples a reception clock (RxClk) from the PLL circuit 2 in accordance with output data (Receiver output) from the receiver 1. Thus, the phase difference between them is detected.

That is, the reception clock (RxClk) from the PLL circuit 2 is supplied to the input terminals (D) of the DFFs 41 and 42, and the output data (Receiver output) from the receiver 1 is received.
Are the clock terminal (CK) of the DFF 41 and the delay circuit (d
elay) 45, XOR (Exclusive OR) gate 46,
And a NOT gate 49.

The DFF 41 latches the reception clock supplied to its input terminal at the timing of the output data supplied to its clock terminal, and supplies it from its output terminal (Q) to one input terminal of the OR gate 43. It has been made to be. Further, the DFF 41 supplies the inverted value of the latched value to its one input terminal of the OR gate 44 from its inverted output terminal (in FIG. 4, a minus sign is added to the upper part of Q). It has been made like that.

In the preceding stage of the clock terminal of the DFF 42, N
An OT gate 49 is provided, so that its clock terminal is supplied with inverted output data. The DFF 42 latches the reception clock supplied to the input terminal thereof at the timing of the inverted output data supplied to the clock terminal, and supplies the received clock to the other input terminal of the OR gate 44 from the output terminal (Q). It has been made to be. Furthermore, DFF42
Is supplied from the inverted output terminal to the other input terminal of the OR gate 43.

The OR gate 43 calculates the logical sum of the signal from the output terminal of the DFF 41 and the signal from the inverted output terminal of the DFF 42, and outputs the calculation result to the AND gate 47.
Is supplied to one of the input terminals. OR
The gate 44 calculates the logical sum of the signal from the inverted output terminal of the DFF 41 and the signal from the output terminal of the DFF 42, and supplies the calculation result to one input terminal of the AND gate 48. .

The delay circuit 45 delays the output data by a time corresponding to, for example, a half cycle of the reception clock and supplies the output data to one input terminal of the XOR gate 46. The other input terminal of the XOR gate 46 is supplied with output data. The XOR gate 46 is connected to the output data and the delay circuit 45.
Of the exclusive OR with the output of
The other input terminals of the ND gates 47 and 48 are supplied. The AND gate 47 calculates the logical product of the output of the OR gate 43 and the output of the XOR gate 46. AND gate 48 is OR
A logical AND between the output of the gate 44 and the output of the XOR gate 46 is calculated.

In the phase comparator 8 configured as described above, the reception clock is sampled (latched) at the rising edge of the output data in the DFF 41, and the sampled value is input to one input terminal of the OR gate 43. Supplied to Further, in the DFF 41, an inverted version of the sample value is supplied to one input terminal of the OR gate 44. That is, in the DFF 41, FIG.
In (C), the sample values indicated by a and c are latched, and the sample values a and c are output to the OR gate 43 as they are. The OR gate 44 outputs the inverted values of the sample values a and c.

On the other hand, in the DFF 42, the reception clock is
The sampling is performed at the timing of the falling edge of the output data, and the sampled value is supplied to the other input terminal of the OR gate 44. Further, in the DFF 42, the inverted value of the sample value is supplied to the other input terminal of the OR gate 43. That is, in the DFF 42, FIG.
In (C), the sample values indicated by b and d are latched, and the OR gate 43 outputs the inverted values of the sample values b and d. The OR gate 44 outputs the inverted values of the sample values b and c.

In the OR gate 43, the logical sum of the signal from the output terminal of the DFF 41 and the signal from the inverted output terminal of the DFF 42 is calculated.
The logical sum of the signal from the inverted output terminal of F41 and the signal from the output terminal of DFF42 is calculated. Where OR
Operation result of gate 43 or 44 (each output is H
Level) is the phase difference between the output data and the receive clock (whether the rising or falling edge of the output data is ahead or behind the rising edge of the receive clock),
That is, it indicates whether there is a positive offset or a negative offset.

On the other hand, in the delay circuit 45, the output data is
The signal is delayed by a very short time and supplied to the XOR gate 46. In the XOR gate 46, an exclusive OR of the delayed output data from the delay circuit 45 and the delayed output data is calculated, whereby at least the rising edge and the falling edge of the output data are calculated. A pulse having an H level near the edge is generated.

Then, in the AND gate 47, the logical product of the operation result of the OR gate 43 and the operation result of the XOR gate 46 is calculated, and the calculation result reduces the reference level, thereby removing the positive offset. Offset down pulse (Voffset dow)
n). Also, in the AND gate 48,
The logical product of the result of the operation of the OR gate 44 and the result of the operation of the XOR gate 46 is calculated, and the result of the logical operation is increased by increasing the reference level, thereby obtaining an offset up pulse (Voffset) for removing a negative offset.
up).

FIG. 5 shows a configuration example of the charge pump circuit 9 of FIG.

The negative terminal of the current source 51 is connected to the power supply Vcc.
And its plus terminal is connected to a switch (S
W) It is connected to the minus terminal of the current source 52 via 53 and 54. The negative terminal of the current source 52 is grounded.

The connection point between the switches 53 and 54 is connected to one end of a capacitor 55, and the other end of the capacitor 55 is grounded. Then, the voltage between both ends of the capacitor 55 is used as the compensation signal (Vadjust) via the low-pass filter 10 through the FET 2 in the receiver 1.
9 (FIG. 3).

The switch 53 or 54 is turned on / off in accordance with the offset down pulse or the offset up pulse from the phase comparator 8, respectively.

The current sources 51 and 5
2, and switches 53 and 54 constitute a charge pump.

In the charge pump circuit 9 configured as described above, the switch 53 is turned off when the offset down pulse is at the L level, and is turned on when it is at the H level. In this case, a current flows through the capacitor 55 via the current source 51 and the switch 53, whereby the capacitor 55 is charged. Therefore, when there is a positive offset, the voltage of the compensation signal increases.

On the other hand, the switch 54 is turned off when the offset up pulse is at the L level, and turned on when the offset up pulse is at the H level. In this case, the electric charge charged in the capacitor 55 flows through the switch 54 and the current source 52, whereby the capacitor 55 is discharged. Therefore, when there is a negative offset, the voltage of the compensation signal decreases.

As described above, such a compensation signal is
Through the low-pass filter 10, F
As applied to the gate of ET 29 (FIG. 3), if there is a positive or negative offset, the reference level of inverter 32 is shifted higher or lower, respectively, thereby removing the offset. You.

As described above, since the reference level is shifted based on the phase difference between the output data and the reception clock, regardless of whether the DC balance is achieved,
The offset of the reference level can be removed (reduced compared to the related art).

The case where the present invention is applied to the receiving apparatus has been described above. Such a receiving apparatus is, for example, an IEEE13.
For example, the present invention can be applied to the case of performing data transfer conforming to H.94 or the like.

In the present embodiment, the phase comparator 8 detects the phase difference between the received clock and the output data by sampling the received clock with the output data. Is not limited to this. Furthermore, the present invention is not limited to the embodiment shown in FIGS.

In this embodiment, the reception clock is sampled at both the rising edge and the falling edge of the output data. However, the sampling of the reception clock is performed at the rising edge or the falling edge of the output data. It is also possible to perform one of them.

[0068]

According to the offset removing circuit according to the first aspect and the offset removing method according to the third aspect, data is output based on the magnitude relationship between the input signal and the reference level, and the clock is output from the data. Is generated. Then, a phase difference between the data and the clock is detected, and an offset included in the reference level is removed based on the phase difference. Therefore, the offset of the reference level can be removed (reduced).

[Brief description of the drawings]

FIG. 1 is a timing chart for explaining the principle of the present invention.

FIG. 2 is a block diagram illustrating a configuration example of an embodiment of a receiving device to which the present invention has been applied.

FIG. 3 is a circuit diagram illustrating a configuration example of a receiver 1 of FIG. 2;

FIG. 4 is a circuit diagram showing a configuration example of a phase comparator 8 of FIG. 2;

FIG. 5 is a circuit diagram showing a configuration example of a charge pump circuit 9 of FIG. 2;

FIG. 6 is a block diagram illustrating a configuration of an example of a conventional receiving apparatus.

FIG. 7 is a waveform diagram showing serial data and an output of a receiver 61 without offset.

FIG. 8 is a waveform diagram showing serial data and an output of a receiver 61 having an offset.

FIG. 9 is a diagram showing that offset and jitter are proportional.

FIG. 10 is a block diagram illustrating a configuration of another example of a conventional receiving device.

[Explanation of symbols]

1 receiver (removal means), 2 PLL circuit (generation means), 3 phase comparator, 4 low-pass filter,
5 voltage controller, 6 frequency divider, 7 DFF, 8
Phase comparator (detection means), 9 charge pump circuit,
10 low-pass filter, 21 to 24 FETs,
25, 26 NOT gate, 27 to 29 FE
T, 30 NOT gate, 41, 42 DFF,
43, 44 OR gate, 45 delay circuit, 46 X
OR gate, 47,48 AND gate, 51,5
2 Current source, 53, 54 switch, 55 capacitor

Claims (3)

[Claims] An output unit that outputs data based on a magnitude relationship between an input signal and a predetermined reference level; a generation unit that generates a clock from the data; and a phase difference between the data and the clock. Detecting means, based on the phase difference detected by the detecting means,
Removing means for removing an offset included in the reference level. 2. The offset removing circuit according to claim 1, wherein said detecting means detects said phase difference by sampling said clock in accordance with said data. 3. A method for outputting data based on a magnitude relationship between an input signal and a predetermined reference level, generating a clock from the data, detecting a phase difference between the data and the clock, and And removing an offset included in the predetermined reference level.