JPH10341222A - Phase adjustment device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the phase adjustment device whose circuit scale is reduced with high flexibility with respect to design and development. SOLUTION: A load value setting means 40 sets a load value to a frequency divider circuit 31 in a system where a pulse signal frequency-divided by the frequency divider circuit 31 in a high speed processing section 30 is sent to a medium speed processing section 20 and a low speed processing section 10. A delay element 50 delays an output of the frequency divider circuit 31 to generate a delayed pulse signal and sends it to the medium speed processing section 20. Through the constitution above, a phase of a low speed interface is adjusted between the medium speed processing section 20 and the low speed processing section 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase adjusting apparatus, and more particularly to a system for transmitting a pulse signal divided by a frequency dividing circuit in a high-speed processing section to a medium-speed processing section and a low-speed processing section. A phase adjusting device for adjusting a phase of a low-speed interface between the processing unit and the low-speed processing unit, and a system for transmitting a pulse signal divided by a frequency dividing circuit in the high-speed processing unit to a medium-speed processing unit, The present invention relates to a phase adjustment device that adjusts the phase of a medium-speed interface between a processing unit and a high-speed processing unit.

[0002]

2. Description of the Related Art In digital transmission, digital information is multiplexed in order to effectively use a transmission medium and transmit information economically.

[0003] SDH / SONE at the core of multiplexing technology
The T optical transmission system defines an interface for effectively multiplexing various high-speed services and existing low-speed services, and is standardized by ITU-T.

On the other hand, recent SDH / SONET optical transmission systems are required to have a large-scale multiplexing processing capability in accordance with an increase in the capacity of lines to be handled. As a result, functional division into a large number of LSIs becomes indispensable. I have.

For example, a plurality of low-speed large-scale LSIs are arranged in parallel in a pointer processing unit having a large circuit scale. In addition, a large-scale LSI that operates at a medium speed is arranged in a multiplex processing unit that requires batch processing by one chip.
Furthermore, high-speed interface units such as optical modules
A high-speed, small-scale LSI is arranged.

In such an LSI stacked in multiple stages, P
/ S (parallel / serial) conversion is performed for each output stage.
Gradually increase the interface speed. Therefore, the LSI having the highest speed interface becomes the master LSI relating to the device timing. The master clock is frequency-divided, and clock / frame pulses are distributed to middle / low speed LSIs.

Therefore, the configuration of the timing system for adjusting the phase of the interface between the LSIs greatly affects the entire device development from the development stage of each LSI and the design stage of the printed circuit board to the device evaluation stage. This is one of the most important considerations.

As a conventional phase adjustment technique, a high-speed LSI
The phase distribution of the clock distributed from is controlled by providing a delay buffer inside each medium / low speed LSI. Or high /
A clock switching memory is provided inside the medium-speed LSI to absorb a phase difference between a clock for taking in input data and a master clock, thereby performing phase adjustment.

[0009]

However, in the above-mentioned prior art in which a delay buffer is provided inside a middle / low speed LSI to adjust the phase, the phase regulation in the device must be established from an early stage of development. Therefore, there is a problem that the burden on the design and development is very heavy.

Further, there is a problem that it is difficult to evaluate an interface between LSIs, and when only a certain LSI is transferred to another device in the future, the conventional standard must be inherited as it is.

On the other hand, in the prior art in which a memory for clock changeover is provided inside a high / medium speed LSI to perform phase adjustment,
Since a memory is required for each LSI, there is a problem that the circuit scale is increased, resulting in an increase in power consumption and a rise in temperature.

Further, a clock for writing input data to the memory other than the master clock is required for the interface, and there is a problem that the number of input / output pins increases.
The present invention has been made in view of such a point, and an object of the present invention is to provide a phase adjustment device that reliably satisfies a phase standard at the time of design and has a reduced circuit scale.

[0013]

In order to solve the above-mentioned problems, the present invention provides a phase adjusting device as shown in FIG. In contrast to a system that transmits the pulse signal divided by the frequency dividing circuit 31 in the high-speed processing unit 30 to the medium-speed processing unit 20 and the low-speed processing unit 10, the phase adjustment device according to the present invention includes the medium-speed processing unit 20 The phase of the low-speed interface between the low-speed processing units 10 is adjusted.

The load value setting means 40 sets a load value in the frequency dividing circuit 31. The delay element 50 delays the output of the frequency dividing circuit 31 to generate a delayed pulse signal, and transmits the signal to the middle-speed processing unit 20.

Here, the load value setting means 40 adjusts the phase of the low speed interface between the middle speed processing unit 20 and the low speed processing unit 10 by setting the load value in the frequency dividing circuit 31. The delay element 50 finely adjusts the phase of the low-speed interface between the medium-speed processing unit 20 and the low-speed processing unit 10 by delaying the output of the frequency dividing circuit 31 and transmitting the delayed output to the medium-speed processing unit 20.

Further, a phase adjusting device as shown in FIG. 2 is provided. In contrast to a system in which the pulse signal divided by the frequency dividing circuit 31 in the high-speed processing unit 30a is transmitted to the medium-speed processing unit 20, the phase adjustment device according to the present invention uses Adjust the phase of the medium speed interface.

The delay element 50a delays the pulse signal turned back in the middle speed processing section 20 to generate a delayed pulse signal. The read clock generation circuit 32 re-divides the pulse signal to generate a read clock. The write clock generation circuit 33 generates a write clock by dividing the frequency of the delay pulse signal. The load value setting means 40a
The load value is set in the read clock generation circuit 32.
The phase difference absorption memory 34 is provided in the high-speed processing unit 30a and receives a write clock and a read clock to absorb a phase difference.

Here, the phase difference absorption memory 34 receives the write clock and the read clock and absorbs the phase difference. The delay element 50a adjusts the phase of the write clock, and the load value setting means 40a adjusts the phase of the read clock.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a principle diagram of a first embodiment of a phase adjusting device according to the present invention. In the first embodiment, the phase adjustment of the low-speed interface between the middle-speed processing unit 20 and the low-speed processing unit 10 is performed.

The overall system configuration to which the first embodiment is applied includes a low-speed processing unit 10, a medium-speed processing unit 20, and a high-speed processing unit 30. The low-speed processing unit 10 outputs low-speed data, the medium-speed processing unit 20 outputs medium-speed data, and the high-speed processing unit 30 outputs high-speed data. And the high-speed processing unit 3
The frequency divider 31 within 0 receives the master clock from the oscillator 60 and divides the frequency. The frequency-divided pulse signal is transmitted to the delay element 50 and the low-speed processing unit 10 described later.

The load value setting means 40 sets a load value in the frequency dividing circuit 31. As a configuration for setting a load value, a load value of 2 ⁿ or less is set using ⁿ external setting pins. For example, the dividing value of the dividing circuit 31 is 1/4,
If the load value has four values of 00, 01, 10, and 11, it can be set by two external setting pins.

The load value can be set by inputting these four values to the frequency dividing circuit 31 as serial data. The delay element 50 is a delay line or the like,
The output of the frequency dividing circuit 31 is delayed to generate a delayed pulse signal, which is transmitted to the medium speed processing unit 20.

As described above, in the first embodiment of the present invention, the load value of the frequency dividing circuit 31 is set by the load value setting means 40, and the output of the frequency dividing circuit 31 is
The configuration is such that the phase adjustment of the low-speed interface between the medium-speed processing unit 20 and the low-speed processing unit 10 is performed with a delay of 0. This allows the load value setting means 40 to perform the phase adjustment in pulse units and the delay element 50 to perform a small amount of phase adjustment.
It becomes possible to design with high flexibility.

Next, a second embodiment will be described.
FIG. 2 is a principle diagram of a second embodiment of the phase adjusting device according to the present invention. In the second embodiment, the phase adjustment of the middle speed interface between the middle speed processing unit 20 and the high speed processing unit 30a is performed.

The overall system configuration to which the second embodiment is applied comprises a medium speed processing unit 20 and a high speed processing unit 30a. The medium speed processing unit 20 outputs medium speed data, and the high speed processing unit 30a outputs high speed data. And the high-speed processing unit 3
The frequency dividing circuit 31 in Oa receives the master clock from the oscillator 60 and divides the frequency. The frequency-divided pulse signal is transmitted to the medium-speed processing unit 20 and the read clock generation circuit 32.

The delay element 50a is a delay line or the like, and generates a delayed pulse signal by delaying the pulse signal turned back in the middle speed processing section 20. The read clock generation circuit 32 re-divides the pulse signal to generate a read clock. The write clock generation circuit 33 generates a write clock by dividing the frequency of the delay pulse signal. Further, an external monitor pin for monitoring the write clock and the read clock may be provided.

The load value setting means 40a sets a load value in the read clock generation circuit 32. The phase difference absorption memory 34 is provided in the high-speed processing unit 30a and receives a write clock and a read clock to absorb a phase difference.

As described above, according to the second embodiment of the present invention, the load value of the read clock generation circuit 32 is set by the load value setting means 40a, and the write clock of the write clock generation circuit 33 is set by the delay element 50a. Is delayed to operate the phase difference absorption memory 34.
Thus, the load value setting unit 40a can perform the phase adjustment in a pulse unit, and the delay element 50a can perform a small amount of phase adjustment, so that a highly flexible design can be performed.

Next, a third embodiment will be described.
The third embodiment has a configuration in which a monitoring device that monitors a write clock and a read clock is provided in a high-speed processing unit.

FIG. 3 is a block diagram of a high-speed processing unit according to the third embodiment. Monitoring device 3 in high-speed processing unit 30b
5 monitors the phases of the write clock output from the write clock generation circuit 33 and the read clock output from the read clock generation circuit 32. Other configurations are the same as those in FIG.

Next, the operation of the monitoring device 35 based on the writing and reading operations of the phase difference absorption memory 34 will be described. FIG. 4 is a timing chart showing the write operation of the phase difference absorption memory 34. Phase difference absorption memory 3
4, the medium speed data from the medium speed processing unit 20 is written using the rising edge of the write clock from the write clock generation circuit 33.

As shown in the figure, at the time of writing, a setup time ts and a hold time th are defined, and the monitoring device 35 monitors whether the write clock satisfies the setup time ts and the hold time th.

FIG. 5 is a timing chart showing the read operation of the phase difference absorption memory 34. The medium speed data from the medium speed processing unit 20 is read into the phase difference absorption memory 34 using the rising edge of the read clock from the read clock generation circuit 32.

As shown in the figure, at the time of reading, a setup time ts and a hold time th are specified, and the monitoring device 35 monitors whether the read clock satisfies the setup time ts and the hold time th.

FIG. 6 is a diagram showing a prohibited area of the read timing with respect to the write timing. In the figure, the section from the rising edge of the write clock to the rising edge of the read clock is a prohibited area, which corresponds to four periods of the sampling pulse.

The monitoring device 35 determines the prohibited area section from the number of cycles of the sampling pulse. That is, the monitoring device 35 determines whether or not the read timing is at an improper position with respect to the write timing based on the number of cycles of the sampling pulse. In that case, the monitoring device 35 gives an alarm notification. Alternatively, the number of cycles of the sampling pulse may be monitored.

For example, in the figure, if the read clock rises within a period of four cycles of the sampling pulse from the rise of the write clock, the monitoring device 35 issues an alarm notification assuming that the read clock is within the prohibited area. Do.

Further, the load value setting means 40a may be configured to receive the alarm notification and automatically set the load value of the read circuit 32. As described above, in the third embodiment of the present invention, the monitoring device 35 is provided to monitor the phases of the write clock and the read clock used in the phase difference absorption memory 34. Thereby, the verification between the interfaces can be easily performed, and the evaluation efficiency can be improved.

Next, a case where the first and second embodiments are applied to a specific system will be described. FIG. 7 shows the first
FIG. 2 is a diagram illustrating a system configuration using the second embodiment.

The low-speed processing unit, the medium-speed processing unit, and the high-speed processing unit described above are each implemented as an LSI in the system shown in FIG. In this system, the clock divided by the frequency dividing circuit in the high-speed LSI 30c is transmitted to the medium-speed LSI 20a and the low-speed LSIs 10a to 10d, and the multiplexed data is connected to the high-speed interface.

Next, the flow of data in the entire system will be described. In the low-speed LSI 10a, the pointer processing unit 11
The pointer processing of data is performed in a. The FF 12a latches the data after the pointer processing and outputs low-speed data DT1 of 78 Mbps. The same applies to the low-speed LSIs 10b to 10d. However, from the low-speed LSI 10b, F
Also outputs P (frame pulse).

In the middle speed LSI 20a, the FF 21 receives and latches the low speed data DT1. Multiplex processing unit 22
Multiplexes the data of each of the low-speed LSIs 10a to 10d after the latch. The P / S 23 converts the multiplexed data into serial data and outputs 155 Mbps medium speed data DT2.

In the high-speed LSI 30c, the MEM 34c corresponding to the phase difference absorption memory described above
T2 is received, and data is output based on the read clock. After that, various signal processing is performed by the signal processing unit 38, and the signal is converted into serial data by the P / S 39.
Mbps high-speed data DT3 is output.

Next, the flow of control signals such as clocks and frame pulses will be described. The oscillator 60 transmits the master clock to the frequency dividing circuit (1/2) 31a, the P / S 39, and the delay line 70. The delay line 70
Receives the master clock looped back in the high-speed LSI 30c and delays and outputs the master clock.

The frequency dividing circuit (1/2) 31a divides the master clock by 2, and transmits the master clock to the frequency dividing circuit (1/4) 31c, the frequency dividing circuit (1/2) 31b, and the signal processing section 38. .
The frequency divider (1/4) 31c receives the load value from the load value setting means 40 described with reference to FIG.
2) The output of 31a is further frequency-divided by 4 to generate clk1, which is transmitted to low-speed LSIs 10a to 10d. Also CTR
37 generates an FP from clk1 and outputs the low-speed LSI 10a to
Send to 10d.

Pointer processing unit 11 in low-speed LSI 10a
a receives clk1 and FP, and FF12a receives clk1
To receive. The same applies to the low-speed LSIs 10b to 10d.

On the other hand, the frequency dividing circuit (1/2) 31b further divides the signal divided by 2 by the frequency dividing circuit (1/2) 31a into two to generate clk2, and generates the delay line 50 and the CTR.
36 and the dividing circuit (1/3) 32c.

The delay line 50 delays clk2 and sends it to the frequency dividing circuit (1/2) 24 and the P / S 23.
The frequency divider (１ ／) 24 divides the output of the delay line 50 by two, and transmits the result to the FF 21 and the multiplex processing unit 22.

The CTR 36 generates a TP (timing pulse) having a phase different from that of the FP from the clk 2 and transmits it to the delay line 51. The delay line 51 has a delayed T
P is transmitted to the frequency dividing circuit (1/2) 24 as a load value. Further, the delay line 50a receives the clk2 turned back inside the medium-speed LSI 20a, and further delays it.
The signal is transmitted to the frequency dividing circuit (1/3) 33c.

The frequency dividing circuit (1/3) 33c is a medium speed LSI 2
Using the TP turned back at 0a as a load value, the output from the delay line 50a is frequency-divided by 3 to generate a write clock, which is transmitted to the MEM 34c.

The frequency dividing circuit (1/3) 32c receives the load value from the load value setting means 40a described with reference to FIG. 2, and divides the output from the frequency dividing circuit (1/2) 31b by 3 to read it. It is generated as a clock and transmitted to the MEM 34c.

As described above, a multiplexing system including a plurality of low-speed LSIs 10a to 10d for performing pointer processing, a medium-speed LSI 20a for performing multiplexing processing, a high-speed interface with an optical module, and a high-speed LSI 30c for performing timing distribution is described. The first and second embodiments are applied. As a result, while minimizing the increase in the line scale and the number of input / output pins of each LSI, the constraints on the design and development of individual LSIs are reduced, and the verification and debugging efficiency of each interface at the device level is increased. It becomes possible.

[0053]

As described above, in the phase adjusting apparatus for adjusting the phase of the low-speed interface according to the present invention, the load value of the frequency divider is set by the load value setting means, and the output of the frequency divider is set to the delay element. With a delay. This makes it possible to easily perform the phase adjustment on a pulse basis by the load value setting means and the minute phase adjustment by the delay element, thereby reliably meeting the phase standard at the time of design.

In the phase adjusting apparatus for adjusting the phase of the medium-speed interface according to the present invention, the load value of the read clock generating circuit is set by the load value setting means, and the write clock of the write clock generating circuit is delayed by the delay element. Thus, the configuration is such that the phase difference absorption memory is operated. This allows the load value setting means to adjust the phase in pulse units,
A minute amount of phase adjustment can be easily performed by the delay element, and the phase standard at the time of design can be surely satisfied. Further, since the phase difference absorption memory only needs to be provided in the high-speed processing section, the circuit scale can be reduced.

[Brief description of the drawings]

FIG. 1 is a principle diagram of a first embodiment of a phase adjustment device according to the present invention.

FIG. 2 is a principle diagram of a second embodiment of the phase adjustment device according to the present invention.

FIG. 3 is a block diagram of a high-speed processing unit according to a third embodiment.

FIG. 4 is a timing chart showing a write operation of the phase difference absorption memory.

FIG. 5 is a timing chart showing a read operation of the phase difference absorption memory.

FIG. 6 is a diagram showing a prohibited area of a read timing with respect to a write timing.

FIG. 7 is a diagram showing a system configuration using the first and second embodiments.

[Description of Signs] 10 Low-speed processing unit 20 Medium-speed processing unit 30 High-speed processing unit 31 Divider circuit 40 Load value setting means 50 Delay element 60 Oscillator

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI // H03K 5/135 H03K 19/00 101N

Claims (10)

[Claims] 1. A system for transmitting a pulse signal divided by a frequency dividing circuit in a high-speed processing section to a medium-speed processing section and a low-speed processing section, wherein a low-speed interface between the medium-speed processing section and the low-speed processing section is provided. And a load value setting means for setting a load value in the frequency dividing circuit, a delay pulse signal generated by delaying an output of the frequency dividing circuit, and transmitting the delayed pulse signal to the medium speed processing unit. A phase adjustment device, comprising: 2. The phase adjustment device according to claim 1, wherein the load value setting means sets the load value of 2 ⁿ or less using n external setting pins. 3. The phase adjustment device according to claim 1, wherein the load value setting means sets the load value by serial data from outside the high-speed processing unit. 4. A system for transmitting a pulse signal frequency-divided by a frequency dividing circuit in a high-speed processing unit to a medium-speed processing unit, wherein a phase adjustment of a medium-speed interface between the medium-speed processing unit and the high-speed processing unit is performed. A delay element that delays the pulse signal to generate a delayed pulse signal; a read clock generation circuit that re-divides the pulse signal to generate a read clock; and divides the delayed pulse signal. A write clock generation circuit that generates a write clock by performing the above operation; a load value setting unit that sets a load value in the read clock generation circuit;
And a phase difference absorption memory for receiving the read clock and absorbing a phase difference. 5. The phase adjustment device according to claim 4, wherein an external monitor pin for monitoring the write clock and the read clock is provided. 6. The phase adjustment device according to claim 4, wherein a monitoring device that monitors whether or not the read clock with respect to the write clock is applied to a prohibited area is included in the high-speed processing unit. 7. The phase adjustment device according to claim 6, wherein the monitoring device monitors the section of the prohibited area based on the number of cycles of a sampling pulse. 8. The phase adjusting device according to claim 7, wherein the monitoring device externally monitors the number of cycles of the sampling pulse. 9. The phase adjustment device according to claim 6, wherein the monitoring device issues an alarm notification when the read clock corresponding to the write clock is applied to the prohibited area. 10. The phase adjustment device according to claim 9, wherein the load value setting means receives the alarm notification and automatically sets the load value.