JPH10335604A - Semiconductor storage device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the level of integration and capacitor capacitance, by providing a capacitor with a lower electrode having a side surface which is vertical to a semiconductor substrate surface and has a height longer than the short side width of the upper surface, and an upper electrode which faces a capacitor dielectric film and the upper surface and the side surface of the lower electrode. SOLUTION: A transistor(Tr) 37 constituted of a gate electrode 34, a source region 35 and a drain region 36 is formed on a semiconductor substrate 31. An interlayer insulating film 41, polysilicon 42 and barrier metal 43 are formed on the Tr 37, A lower electrode 44a is formed on the barrier metal 43. The lower electrode 44a has a side surface which is vertical to the semiconductor substrate 31 surface and has a height longer than the short side width of the upper surface. On the upper surface and the side surface of the lower electrode 44a, a plate capacitor 47 constituted of a capacitor dielectric film 45 and an upper electrode 46 is formed. When the Tr 37 is turned on and off by an input voltage of the gate electrodep 34, electric charge of the capacitor 47 is charged and discharged, and information is stored.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device capable of forming a large-capacity capacitor with a small element area and a method of manufacturing the semiconductor memory device.

[0002]

2. Description of the Related Art FIGS.
FIG. 10 is a cross-sectional view showing a step of a conventional method for manufacturing a semiconductor memory device described in Japanese Patent Publication No. 100; In FIG. 9, a gate oxide film 3 and a gate electrode 4 are formed on a semiconductor substrate 1 divided into an active region and an isolation region by a field oxide film 2 by an ordinary method. Next, a source region 5 and a drain region 6 are formed on the substrate 1, and a transistor 7 including the gate electrode 4 and the source region 5 and the drain region 6 is formed. Further, a first insulating film 8 is formed on the gate electrode 4.

Next, a bit line 9 covered with a second insulating film 10 is formed on the source region 5. Next, a planarization layer 11 of an insulating film is formed over the transistor 7. Next, a contact hole 12 is formed from the surface of the planarization layer 11 to the surface of the drain 6 by etching. A conductive material is buried in the contact hole 12 to form a conductive plug 13. The low dielectric pattern 1 is formed on the conductive plug 13.
4 is formed.

Next, as shown in FIG. 10, a barrier conductive layer 15 is formed by depositing titanium Ti or titanium nitride TiN on the conductive plug 13 and the low dielectric pattern 14 by a sputtering method. On this, platinum P is formed by sputtering.
t is deposited to form the capacitor lower electrode 16a. SOG is applied thickly on the capacitor lower electrode 16a to form a flat material layer 17.

[0005] Next, as shown in FIG.
The lower electrode 16a is formed by polishing until the surface of the low dielectric pattern 14 is exposed by the MP method.

[0006] Next, as shown in FIG.
And B, which is a high dielectric film 18 on the low dielectric pattern 14,
An ST film is deposited by a CVD method. Furthermore, high dielectric film 1
Platinum is deposited on 8 to form a capacitor upper electrode 19.

Since the low dielectric layer 14 is provided between the capacitor lower electrodes 16a in this manner, electromagnetic coupling between adjacent capacitor lower electrodes 16a is small, and malfunction can be prevented.

[0008]

SUMMARY OF THE INVENTION However, FIGS.
In the conventional method of manufacturing a semiconductor memory device shown in FIG. 12, when a high-density semiconductor memory of, for example, 64 MB or more is formed, the area of an electrode forming a capacitor of the memory is drastically reduced, and a predetermined capacitor capacity cannot be obtained. There is.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a semiconductor memory device having a highly integrated and large capacity capacitor and a method of manufacturing the same.

[0010]

According to a first aspect of the present invention, there is provided a semiconductor memory device which is connected to a source or a drain of a transistor on an interlayer insulating film formed on a transistor formed on a semiconductor substrate. A lower electrode having a side surface perpendicular to the semiconductor substrate surface and having a height longer than the short side width of the upper surface; a capacitor dielectric film formed on the upper surface and the side surface of the lower electrode; An upper electrode facing the upper and side surfaces of the lower electrode with the capacitor dielectric film interposed therebetween.

A semiconductor memory device according to a second aspect of the present invention includes a capacitor having a height of a side surface of the lower electrode higher than a short side width of an upper surface of the lower electrode and lower than twice the short side width. is there.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, comprising: a transistor formed on a semiconductor substrate; an interlayer insulating film formed on the transistor; and a source or drain of the transistor on the interlayer insulating film. Forming a molding insulating film on an interlayer insulating film, and etching the molding insulating film perpendicularly to a surface of the semiconductor substrate. Forming an opening surrounded by the insulating film and the interlayer insulating film, forming a conductive film thicker than the opening in the opening, and forming the conductive film until the surface of the molding insulating film is exposed. Polishing to form a lower electrode,
A step of etching and removing the insulating film for molding, and a step of forming a capacitor dielectric film on the upper surface and side surfaces of the lower electrode,
Forming an upper electrode over the capacitor dielectric film.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. FIG. 1 is a sectional view of the semiconductor memory device according to the first embodiment. In FIG. 1, 31 is a semiconductor substrate,
32 is a field oxide film formed on the semiconductor substrate. 33 is a gate oxide film formed on a semiconductor substrate, 3
4 is a gate electrode formed on the gate oxide film 33, 35
Is a source region formed on the semiconductor substrate 31, 36 is a drain region formed on the semiconductor substrate 31, and 37 is a transistor including a gate electrode 34, a source region 35, and a drain region 36. Reference numeral 38 denotes a first oxide film formed on the gate electrode 34.

39 is a bit line connected to the source region 35, 40 is a second oxide film formed covering the bit line 39, 41 is an interlayer insulating film formed on the transistor 37 on the semiconductor substrate 31. is there. Reference numeral 42 denotes a polysilicon plug which is a conductive plug connected to the drain region 36 and formed up to the surface of the interlayer insulating film 41. Reference numeral 43 denotes a barrier metal connected to the polysilicon plug 42 and formed on the surface of the interlayer insulating film 41, for preventing mutual diffusion of material atoms of the polysilicon plug 42 and a lower electrode 44a described later.

A lower electrode 44a is formed on the interlayer insulating film 41 on the polysilicon plug 42 via the barrier metal 43 and is perpendicular to the surface of the semiconductor substrate 31 and lower electrode 4a.
The lower electrode 4a has a side surface having a height longer than the short side width of the lower electrode defined by the minimum distance between the parallel surfaces when the upper surface shape is sandwiched between the parallel surfaces. For example, in the case of a 1 G (gigabit) semiconductor memory device, the lower electrode is formed of a Pt film, the short side width is 0.1 μm, the pitch is 0.15 μm, and the height of the side surface of the lower electrode is 0.3 to 0.3 μm. It is about 4 μm. Reference numeral 45 denotes a capacitor dielectric film, which is a high dielectric film such as TiBaO3 or PZT that covers the upper surface and side surfaces of the lower electrode 44a. Reference numeral 46 denotes an upper electrode which is opposed to the upper surface and side surfaces of the lower electrode 44a with the capacitor dielectric film 45 interposed therebetween. 4
Reference numeral 7 denotes a capacitor, which is a plate-type capacitor including a lower electrode 44a, a capacitor dielectric film 45, and an upper electrode 46.

In the semiconductor memory device of the first embodiment, the transistor 37 is turned on / off by the input voltage to the gate electrode 34 of the transistor 37, and the charge of the capacitor 47 is charged / discharged according to the potential of the bit line 39 to store information. Things. The ability of the capacitor 47 to accumulate charges is proportional to the area of the lower electrode 44a and the upper electrode 46 facing each other.

In the first embodiment, it is possible to obtain a semiconductor memory device having a capacitor with a large storage capacity by increasing the film thickness of the lower electrode 44a and increasing the side area of the lower electrode 44a as a part of the counter electrode. it can. As the dimensions and shape of the lower electrode 44a, the height of the lower electrode / the width of the short side of the lower electrode is about 1.5 to 2. This is 1GDRA
In the M element, this is a range where the capacitor dielectric film 45 can be uniformly formed on the side surface of the lower electrode by the CVD method. The upper limit of the height of the lower electrode is based on the reality of the manufacturing technique capable of uniformly forming the capacitor dielectric film 45 on the side surface of the lower electrode, and the lower limit of the height of the lower electrode is the design value of the capacitance value of the capacitor. Is a value appropriately obtained by In addition, since the side surface of the lower electrode 44a is perpendicular to the surface of the semiconductor substrate 31, it is possible to prevent unnecessary spread in the direction of an adjacent element and to increase the density.

Embodiment 2 FIG. 2 to 8 are process cross-sectional views illustrating a method for manufacturing the semiconductor memory device of the second embodiment. 2 to 8 show DRAMs of 1 G (gigabit) or more.
It is an example in the case of forming. 2 to 8, the same reference numerals as in FIG. 1 are the same as those in FIG. In FIG. 2, a transistor 3 on a semiconductor substrate 31
7, an interlayer insulating film 41 is formed by an ordinary method.
Next, a polysilicon plug 42 is formed up to the surface of the interlayer insulating film 41 so as to connect to the drain region 36 of the transistor 37 in the same manner as in the conventional technique.

Next, as shown in FIG. 3, Ti is deposited on the interlayer insulating film 41 and the polysilicon plug 42 by sputtering.
A barrier metal 43 made of N is formed. Next, the film thickness 20
A molding insulating film 51 having a thickness of 00 to 5000 ° is formed by a thermal CVD method. As the material of the molding insulating film 51, SiO2 or a material obtained by adding P or B impurities to SiO2 is used.

Next, as shown in FIG.
A resist pattern 55 is formed thereon. Using the resist pattern 55 as a mask, Cl is vertically applied to the semiconductor substrate 31 from above by RIE (Reactive Ion Etching).
The molding insulating film 51 is anisotropically etched by irradiating a 2 or CF4 ion beam (not shown) to form a semiconductor substrate 31.
A molding pattern 51a having a side surface perpendicular to the surface is formed, and an opening 52 surrounded by the interlayer insulating film 41 and the side surface of the molding pattern 51a is formed as shown in FIG. The size of the opening 52 is approximately determined by adding a height of a lower electrode 44a to be described later and a polishing amount by a CMP method (chemical mechanical polishing) after forming a first conductive film to be described later.

Next, as shown in FIG. 6, a film thickness 20 thicker than the depth of the opening 52 is formed on the opening 52 by sputtering.
A platinum layer serving as the first conductive film 44 having a thickness of 00 to 5000 is formed.

Next, as shown in FIG. 7, the platinum layer 44 is polished by a CMP method until the surface of the molding pattern 51a appears, thereby forming a lower electrode 44a.

In FIG. 8, using the lower electrode 44a as a mask, the molding pattern 51a and the barrier metal 42 are removed by anisotropic etching.

The next step will be described with reference to FIG. As shown in FIG. 1, at a temperature of 500 to 700 ° C.,
Thickness 2 made of a high dielectric substance of tTiO3 or BaTiO3
A capacitor dielectric film 45 of 00 ° is formed on the upper and side surfaces of the lower electrode 44a. Next, a film thickness of 300 as a second conductive film covering the capacitor dielectric film 45 by a sputtering method.
A platinum layer of Å is formed and used as an upper electrode 46.

The dimension and shape of the lower electrode are such that the height of the lower electrode / the width of the short side of the lower electrode is about 1.5 to 2. This is a range where the capacitor dielectric film 45 can be uniformly formed on the side surface of the lower electrode by the CVD method in the 1GDRAM device. For example, if the width of the short side of the lower electrode is 0.
When the thickness is 2 μm, the height of the lower electrode is set to 0.3 to 0.4 μm.

In the method of manufacturing a semiconductor memory device according to the second embodiment, first, a molding pattern 51a of a deep opening 51b whose side surface is perpendicular to the semiconductor substrate 31 is formed, and the opening 51b is filled with platinum. Lower electrode 44a
Formed, it is possible to easily form the lower electrode 44a having a high height and a vertical side surface using platinum which is difficult to process, and then remove the molding pattern 51a to remove the side portion of the lower electrode. Since the counter electrode is also used as the counter electrode, a capacitor with a high degree of integration and a large capacitance can be obtained.

[0027]

The present invention has the following effects. According to the semiconductor memory device of the first and second aspects of the invention, since the lower electrode having the vertical and high side surface is formed,
A capacitor with a high degree of integration and a large capacitance can be obtained.

According to the method of manufacturing a semiconductor memory device according to the third aspect of the present invention, an opening having a side surface perpendicular to the substrate surface is formed by a molding insulating film, and a metal is filled in the opening to form a lower electrode. Since the molding insulating film is removed and the side of the lower electrode is also used as a counter electrode, a capacitor with a high degree of integration and a large capacitance can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor memory device according to a first embodiment of the present invention;

FIG. 2 is a process chart showing a method of manufacturing a semiconductor memory device according to a second embodiment of the present invention;

FIG. 3 is a process chart showing a method of manufacturing a semiconductor memory device according to a second embodiment of the present invention;

FIG. 4 is a process chart illustrating a method for manufacturing a semiconductor memory device according to a second embodiment of the present invention;

FIG. 5 is a process chart showing a method of manufacturing a semiconductor memory device according to Embodiment 2 of the present invention;

FIG. 6 is a process chart illustrating a method for manufacturing a semiconductor memory device according to a second embodiment of the present invention.

FIG. 7 is a process chart showing a method of manufacturing a semiconductor memory device according to Embodiment 2 of the present invention;

FIG. 8 is a process chart showing a method of manufacturing a semiconductor memory device according to Embodiment 2 of the present invention;

FIG. 9 is a plan view showing steps of a conventional method for manufacturing a semiconductor memory device.

FIG. 10 is a plan view showing steps of a conventional method for manufacturing a semiconductor memory device.

FIG. 11 is a plan view showing steps of a conventional method for manufacturing a semiconductor memory device.

FIG. 12 is a plan view showing steps of a conventional method for manufacturing a semiconductor memory device.

[Explanation of symbols]

31 semiconductor substrate, 32 field oxide film, 33
Gate oxide film, 34 gate electrode, 35 source region, 36 drain region, 37 transistor,
38, 40 oxide film, 39 bit line, 41 interlayer insulating film, 42 polysilicon plug, 43 barrier metal, 44a lower electrode, 45 capacitor dielectric film, 46 upper electrode, 47 capacitor,
51 insulating film for molding, 51a pattern for molding,
52 opening, 55 resist pattern.

Claims (3)

[Claims] 1. A semiconductor memory device comprising a transistor formed on a semiconductor substrate, an interlayer insulating film formed on the transistor, and a capacitor formed on the interlayer insulating film and connected to a source or a drain of the transistor. Wherein the capacitor has a lower electrode having a side surface perpendicular to the semiconductor substrate surface and having a height longer than a short side width of the upper surface; a capacitor dielectric film formed on the upper surface and the side surface of the lower electrode; A semiconductor memory device comprising: an upper electrode facing an upper surface and a side surface of the lower electrode with a body film interposed therebetween. 2. The semiconductor memory device according to claim 1, wherein the height of the side surface of the lower electrode is higher than the width of the short side of the upper surface of the lower electrode and lower than twice the width of the short side. 3. A semiconductor memory device including a transistor formed on a semiconductor substrate, an interlayer insulating film formed on the transistor, and a capacitor formed on the interlayer insulating film and connected to a source or a drain of the transistor. Forming a molding insulating film on the interlayer insulating film; and etching the molding insulating film perpendicularly to the semiconductor substrate surface to form the molding insulating film and the interlayer insulating film. Forming an enclosed opening; forming a conductive film thicker than the depth of the opening in the opening; polishing the conductive film until the surface of the molding insulating film is exposed; Performing a step of etching the molding insulating film; forming a capacitor dielectric film on an upper surface and side surfaces of the lower electrode; and forming the capacitor dielectric film. The method of manufacturing a semiconductor memory device which comprises a step of forming an upper electrode over.