JPH10334080A - Fast fourier transformation arithmetic unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an FFT arithmetic unit capable of generating a rotator index string to perform a butterfly operation of a cardinal number 4 and performing FFT arithmetic operation of the cardinal number 4 as a result. SOLUTION: Evry progression obtained by arranging rotator indexes of four rotators to be supplied to an arithmetic operation part 12 in the order of size from small to large in each butterfly operation is an arithmetic progression whose initial member is zero and a progression obtained by arranging tolerances of each arithmetic progression is also provided with regularity when an executing order of the butterfly operation is properly selected. Therefore, an increment equivalent to the tolerance of each arithmetic progression is generated by every clock by an increment generating circuit 102 and the increment is added to the rotator index of one clock before the present one stored in a register 105 by an adder 104. On the other hand, the rotator indexes of the rotators to be supplied for every butterfly operation are successively generated by initializing a value which is held to zero for every four clocks by the register 105 by a rotator index generating circuit 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a fast Fourier transform operation device, and more particularly, to a fast Fourier transform operation device for performing a radix-4 fast Fourier transform operation.

[0002]

2. Description of the Related Art In recent years, digitalization of broadcasting technology has been rapidly advanced, and in the field of television broadcasting and audio broadcasting, OFDM (Orthogonal Frequency) has also been used.
Practical use of digital terrestrial television broadcasting, mobile satellite digital broadcasting, and the like that employs a modulation method called cyDivision Multiplexing is being studied. Since OFDM modulation and demodulation is performed by Fast Fourier Transform (FFT), there is a need to develop an FFT operation device capable of higher-speed processing.

The FFT is an algorithm for executing a discrete Fourier transform at a high speed by repeatedly performing a basic operation called a butterfly operation while changing input values and coefficients. Performing a discrete Fourier transform on N input values typically requires N ² complex multiplications, but using a radix-2 FFT algorithm reduces the number of multiplications to ｛(N /
2) The number of operations can be reduced to log ₂ N｝ times, so that high-speed processing can be performed. The radix-2 FFT operation can also be executed by a general-purpose computer or digital signal processor, but is often executed by dedicated hardware, especially when high-speed operation processing is required. Conventionally, various configurations of such hardware have been proposed, but in general, the configuration can be reduced to the configuration described in Japanese Patent Application Laid-Open No. 60-147839, "Computing Device". Hereinafter, the operation of the conventional FFT operation device represented by the “operation device” will be described.

The above-mentioned conventional FFT operation device includes an operation section for executing a butterfly operation, a coefficient memory in which coefficients necessary for the butterfly operation (hereinafter referred to as a rotator, which will be described later), and a rotator in a coefficient memory. And an address generating circuit for generating an address for reading from the memory. A required rotator is read from the coefficient memory for each butterfly operation and is supplied to the operation unit.

FIG. 15 is a signal flow chart showing an example of a radix-2 FFT operation. The calculation shown in FIG.
6 (= 2 ⁴ ), which is an FFT operation called a time thinning-out type.
By performing the butterfly computations in the order of numbers (0 to 31), 16 output values of F (0) to F (15) are obtained for 16 input values of f (0) to f (15). Value.

That is, in the first stage, first, for input values f (0) and f (8), f (0) + W ⁰ ・
f (8), f (0 ) -W 0 Calculate f (8) (number 0
Butterfly operation), and then input values f (4) and f
For (12), f (4) + W ⁰ ・ F (12), f
(4) -W ⁰ Calculate f (12) (butterfly operation of number 1), and thereafter perform similar butterfly operations in the order of numbers 3 to 7. In the second stage, similar butterfly operations are performed in the order of numbers 8 to 15 using the values obtained by the butterfly operation of the first stage as input values. In the third and fourth stages, if similar butterfly operations are performed, F (0) to F (0) to F
The 16 output values of (15) are obtained.

Here, W ⁿ And n (n = 0, 1, 2,
, N-1) are called a rotator and a rotator index, respectively. In general, the number of sample points (the number of input values) is N
(Where N is a positive integer) and has the relationship shown in the following equation (1). W ⁿ = exp (−ω · 2πn / N) = cos (2πn / N) −ω · sin (2πn / N) (where ω is an imaginary unit) (1)

In each butterfly operation, W⁰And (in the figure
This W⁰), W⁰~ W⁷With one of
, Each requires two rotors, but from FIG.
Obviously, the order of the latter rotor has regularity.
You. Therefore, the FFT operation shown in FIG.
When the rotor W is to be driven, the rotor W given by the above equation (1)
ⁿ Is stored in the address n of the coefficient memory.
A rotor similar to that of FIG.
Index columns are created sequentially using this regularity.
If this is the case, the necessary rotator will be
Can be supplied.

FIG. 16 shows the result of the FFT operation shown in FIG.
FIG. 7 is a diagram for explaining a relationship between an execution order of butterfly operations and a rotor index of a rotor required for each butterfly operation. However, the butterfly execution order is decimal,
The rotator indices are each represented by a binary number (3 bits). In FIG. 16, when the butterfly execution order (0 to 31) is displayed in binary, the lower 3 bits are extracted in the fourth stage, and the lower 2 bits are extracted in the third stage and 0 is added to the lower bits. In the stage, the lower one bit is extracted and 00 is added to the lower bit, and each of the lower bits matches the rotator index. In addition,
Although the description is omitted here, almost the same relationship holds in an FFT operation called a radix-2 frequency thinning-out type.

The rotator index generation circuit of the conventional FFT operation device pays attention to this relationship and performs a predetermined bit operation on the butterfly execution order, thereby forming a rotator index sequence similar to that of FIG. Has been generated. For example, a circuit combining a binary counter that counts the number of executions of a butterfly operation and a shift register that performs a predetermined bit operation on a value obtained by counting the binary counter is disclosed in Japanese Patent Application Laid-Open No. SHO 51-105246. Address operation circuit of Fourier transform digital processor "
Is disclosed. In addition, a circuit using a register capable of stepping by ± 1 and 2 (see Japanese Patent Application Laid-Open No. 62-175866)
Publication "Signal Processor"), a circuit combining a selector and a JK flip-flop (Japanese Patent Laid-Open No. 22-22 / 1990)
No. 0172, “Address Generation Circuit for Butterfly Operation in Fast Fourier Transform”, etc. are also known.

[0011]

By the way, conventionally, FF
As the T algorithm, for example, a radix-4 algorithm other than the radix-2 algorithm is known. By performing a radix-4 FFT operation, the number of complex multiplications can be reduced to {(3N / 8) log ₂ N}. This is ３ of the number of multiplications when the radix-2 FFT is performed. Therefore, if there is an FFT operation device capable of performing a radix-4 FFT operation, it can be expected that high-speed processing as required in the above-mentioned OFDM is realized. However, conventionally, an FFT operation device that performs a radix-4 FFT operation has not been provided since the above-described high-speed processing has not been required.

As described above, the conventional FF
In the T operation device, the rotator Wn is stored in the address ⁿ of the coefficient memory, and the rotator index generation circuit operates as shown in FIG.
By sequentially generating a rotor index sequence similar to that of the above, the necessary rotor was supplied to the calculation unit for each butterfly calculation. At that time, the rotator index generation circuit generates the rotator index by directly performing a predetermined bit operation on the butterfly execution order, that is, a numerical value that advances in each butterfly operation.

That is, in the conventional FFT operation device, the rotator index generation circuit controls the rotation of one of the two rotators required for each butterfly operation except for W ⁰ required for all butterfly operations. Only child indexes,
What is necessary is just to generate | occur | produce for every butterfly operation, for this reason, a rotor index was easily able to be generated by performing a predetermined bit operation on the butterfly execution order. However, radix 4
In order to perform the FFT operation, three rotators are required for each butterfly operation, and three different rotors are required even if W ⁰ required for all butterfly operations is excluded. Therefore,
In a conventional FFT operation device that generates a rotator index by performing a bit operation on a butterfly execution order, a rotator index sequence for performing a radix-4 butterfly operation cannot be easily generated. FFT operation cannot be performed.

Therefore, an object of the present invention is to provide an FFT operation device capable of sequentially generating a rotator index sequence for performing a radix-4 butterfly operation, and consequently performing a radix-4 FFT operation. It is to be.

Further, the conventional FFT arithmetic unit, instead of allowed to store the rotor W ⁿ itself address n coefficient memories, cos (2πn / N) and sin (2 [pi] n /
N) (N is the number of sample points, n = n ₀ , n ₀ +1, n ₀ +2,
..; N ₀ is an arbitrary integer) is stored as a pair, and a rotator is often generated by the above equation (1) based on the trigonometric function values. In this case, the capacity of the coefficient memory can be reduced by using the periodicity and symmetry of the trigonometric function.

As such an FFT operation device, for example, a device in which a coefficient memory stores a pair of cosine and 周期 cycle of the sine function value (Japanese Patent Application Laid-Open No. SHO 51-51)
No. 4,1931, “Fourier transform address generation circuit”), instead of storing the cosine and sine function values as a pair,
One that stores ne function values (Japanese Unexamined Patent Publication No. Hei 5-324697)
Publication "Twirl Factor Generation Circuit for Fast Fourier Transform Operation")
Etc. are known.

As described above, if the rotator is generated using the periodicity and symmetry of the trigonometric function, there is an advantage that the capacity of the coefficient memory can be reduced. However, as in the above “Fourier transform address generation circuit”, cosine and si
Even if one-eighth cycle of the ne function value is stored as a pair, the number of accesses to the coefficient memory is the same as the number of accesses when one cycle is entirely stored. In the above “Fast Fourier transform calculation twiddle factor generation circuit”,
Since two accesses to the coefficient memory are required to generate one rotator, the number of accesses is doubled.

That is, neither the "Fourier transform address generation circuit" nor the "Fast Fourier transform calculation twiddle factor generation circuit" takes care to reduce the number of accesses to the coefficient memory. There is a problem that the power consumption is large and the processing speed is slow.

Therefore, another object of the present invention is to reduce the number of accesses to the coefficient memory during butterfly computation,
As a result, an object of the present invention is to provide an FFT operation device that can perform an FFT operation with less power consumption and at a higher processing speed.

[0020]

Means for Solving the Problems and Effects of the Invention A first invention is an apparatus for performing a fast Fourier transform operation, wherein a plurality of rotors different from each other are attached to the plurality of rotors. The storage means stored in each of the addresses related to the index and a predetermined butterfly execution order are set, and the calculation means for executing a plurality of butterfly operations in accordance with the order, and the storage means for each of the plurality of butterfly operations. Rotor index generating means for sequentially generating a rotor index of a predetermined number of rotors to be read and supplied to the arithmetic means, wherein the rotor index generating means relates to a clock. A clock counting means for outputting a clock value such that the clock value is incremented; an increment value generating means for generating an increment value in association with the clock value output by the clock counting means; A clear signal generating means for generating a clear signal in a cycle, an adding means for adding the previously output rotor index and the increment value generated by the increment value generating means, and a rotation obtained by adding the adding means. Holding means for temporarily holding and outputting the child index and initializing the held rotor index in response to the clear signal generated by the clear signal generating means.

As described above, in the first aspect, the storage means stores the plurality of rotors in the memory at the addresses where the rotors are stored, and the rotor index assigned to each of the rotors. Are stored in association with each other. A predetermined butterfly execution order is set in the arithmetic unit, and the arithmetic unit executes a plurality of butterfly operations in accordance with the order. The rotor index generating means sequentially generates, for each butterfly operation, a rotor index of a predetermined number of rotors to be supplied to the arithmetic means among the rotors stored in the storage means. At this time, the clock counting means outputs a clock value which advances in relation to the clock, and the increment value generation means generates an increment value in relation to the clock value output by the clock counting means. The adding means adds the previously output rotator index and the increment value generated by the increment value generating means. The holding means temporarily holds and outputs the rotor index obtained by the adding means, and also holds the rotor index held by the clear signal generating means in response to a clear signal generated at a predetermined cycle. Initialize the box.

As described above, the sequence obtained by arranging the rotor indexes of the predetermined number of rotors to be supplied to the calculating means in each butterfly operation in ascending order is an arithmetic sequence having 0 as a first term. In addition, if the butterfly execution order is appropriately selected, focusing on the fact that the sequence obtained by arranging the tolerances of each arithmetic sequence also has a predetermined regularity, the increment value corresponding to the tolerance of each arithmetic sequence is taken into account. Generate Then, by repeating the operation of adding the increment value to the retained previous rotor index and outputting the value, and initializing the retained value to 0 at a predetermined cycle, for each butterfly operation, Rotor indexes of a predetermined number of rotors to be supplied to the arithmetic means can be sequentially generated, and as a result, FFT operation can be performed.

According to a second aspect of the present invention, in the first aspect, the clear signal generating means obtains a clear signal generation timing based on a clock value output from the clock counting means.

Thus, the clear signal generating means can easily obtain the timing for generating the clear signal.

According to a third aspect of the present invention, in the first aspect, the butterfly execution order set in the arithmetic means is such that butterfly operations such that a predetermined number of rotors to be supplied to the arithmetic means all coincide are continuous. The order is such that the order is executed.

As described above, in the third aspect of the present invention, the butterfly computations in which all of the required predetermined number of rotors are all executed continuously are performed, so that the frequency at which the increment value changes is reduced. As a result, power consumption is reduced.

According to a fourth aspect of the present invention, there is provided an apparatus for performing a radix-4 fast Fourier transform operation, wherein a plurality of different rotators are provided at addresses associated with rotator indexes assigned to the plurality of rotators. Each of the stored memory means and a predetermined butterfly execution order are set, and an arithmetic means for executing a plurality of butterfly operations in accordance with the order, and for each of the plurality of butterfly operations, read from the storage means and read to the arithmetic means. Rotor index generating means for sequentially generating rotor indexes of the four rotors to be supplied, wherein the rotor index generating means outputs a clock value such that it increments every clock. Clock counting means, an increment value generating means for generating an increment value in relation to the clock value output by the clock counting means, and a clear signal every four clocks. Rear signal generating means, adding means for adding the rotor index output one clock before, and the increment value generated by the increment value generating means, and a rotor index obtained by adding the adding means; Holding means for holding and outputting one clock and initializing the held rotor index in response to the clear signal generated by the clear signal generating means.

As described above, in the fourth aspect of the present invention, the storage means stores a plurality of rotors at the addresses where the rotors are stored and the rotor indexes assigned to the rotors. Are stored in association with each other. A predetermined butterfly execution order is set in the arithmetic unit, and the arithmetic unit executes a plurality of butterfly operations in accordance with the order. The rotor index generation means sequentially generates, for each butterfly operation, rotor indexes of four rotors to be supplied to the calculation means among the rotors stored in the storage means. At this time, the clock counting means is 1
A clock value is output so as to be incremented every clock, and the increment value generation means generates an increment value in relation to the clock value output by the clock counting means. The adding means adds the rotor index output one clock before and the increment value generated by the increment value generating means. The holding means holds the rotor index obtained by the addition means for one clock and outputs it, and the clear signal generation means holds the rotor index in response to a clear signal generated every four clocks. Initialize the index.

As described above, the sequence obtained by arranging the rotor indices of the four rotors to be supplied to the calculating means in each butterfly operation in ascending order is an arithmetic progression having 0 as a first term. If the butterfly execution order is appropriately selected, paying attention to the fact that a sequence obtained by arranging the tolerances of each arithmetic sequence also has a predetermined regularity, an increment value corresponding to the tolerance of each arithmetic sequence is calculated. Generate. By repeating the operation of adding the increment value to the retained rotor index one clock before and outputting the value, and initializing the retained value to 0 every four clocks, In addition, the rotor indexes of the four rotors to be supplied to the arithmetic means can be sequentially generated, and as a result, a radix-4 FFT operation can be performed.

According to a fifth aspect of the present invention, in the fourth aspect, the clear signal generating means obtains the generation timing of the clear signal based on the clock value output from the clock counting means.

Thus, the clear signal generating means can easily obtain the timing for generating the clear signal.

In a sixth aspect based on the fourth aspect, the butterfly execution order set in the arithmetic means is such that butterfly operations such that all four rotors to be supplied to the arithmetic means coincide with each other are continuously performed. It is characterized by the order in which they are executed.

As described above, in the sixth aspect of the present invention, the butterfly computations in which all of the required predetermined number of rotors are all executed continuously are performed, so that the frequency at which the increment value changes is reduced. As a result, power consumption is reduced.

In a seventh aspect based on the sixth aspect, the radix-4 Fast Fourier Transform operation is an operation having a sampling point of 4 ^m (where m is an arbitrary integer of 2 or more). In the k-th operation stage (k = 1,..., M), the lower 2 bits of the remaining 2 (m−1) bits are removed after removing the lower 2 bits of the 2m-bit clock value output by the clock counting means. mk) bits are each replaced with 0 to generate an increment value.

If the number of sample points is 4 ^m , the increment value generation means removes the lower two bits of the 2m-bit clock value output by the clock counting means at the k-th stage (k = 1,..., M). Thereafter, the lower 2 (m−k) bits of the remaining 2 (m−1) bits are each replaced with 0, thereby easily generating an increment value.

An eighth aspect of the present invention is an apparatus for performing a fast Fourier transform operation, wherein a pair of trigonometric function values ΔA for １ ／ cycle are provided.
cos (2πn / N), Asin (2πn / N)｝ (A
Is a positive constant, N is the number of sample points, n = n ₀ +1, n ₀ +
2,..., N ₀ + N / 8; n ₀ = r · N / 8, where r is an arbitrary integer), and a predetermined butterfly execution order is set, and a predetermined butterfly execution order is set. Calculating means for performing a plurality of butterfly operations in accordance with the order, and rotor index generation for sequentially generating, for each of the plurality of butterfly operations, rotor indexes of a predetermined number of rotors to be supplied to the calculating means. Means and the rotor index generated by the rotor index generating means is N / 4
Specific trigonometric function value generating means for generating a pair of trigonometric function values predetermined in relation to r, when the integral multiple of r
Conversion means for converting the rotor index into an address value indicating the address of the storage means when the rotor index generated by the rotor index generation means is not an integral multiple of N / 4; A rotator for generating a rotator based on a pair of trigonometric function values generated by the means or a pair of trigonometric function values stored in an address of the storage means corresponding to the address value obtained by conversion by the conversion means; Generating means.

As described above, in the eighth aspect, the storage means
Has a pair of trigonometric function values ｛Acos (2
πn / N), Asin (2πn / N)｝ (n = n₀+
1, n ₀ +2, ..., n₀ + N / 8) is related to n
It is stored at consecutive addresses. The arithmetic means has a predetermined
The fly execution order is set, and the arithmetic means
Perform butterfly operations in that order. Rotor b
The index generator generates an operation method for each butterfly operation.
Rotor index of a given number of rotors to be supplied to the stage
Generated sequentially. The specific trigonometric function value generation means
Rotor index generated by trochanter index generator
Is a predetermined number of pairs, where N is an integral multiple of N / 4.
Generates a trigonometric function value of. The conversion means is a rotor indy
The rotor index generated by the motor generator is N / 4
Remember the rotator index if it is not an integer multiple
It is converted into an address value indicating any address of the means. Times
The trochanter generating means is the one generated by the specific trigonometric function value generating means.
The conversion function of the pair of trigonometric function values or the storage means is converted
Stored in the address that matches the address value obtained
A rotator is generated based on a pair of trigonometric function values.

As described above, a pair of trigonometric function values １ ／ Acos (2πn / N) and Asin (2πn /
N)｝ (n = n ₀ +1, n ₀ +2,..., N ₀ + N / 8)
Is stored in the address associated with n in the storage means, while the rotor index generation means sequentially generates a required number of rotor indexes of the required number of rotors for each butterfly operation. When the generated rotator index is an integral multiple of N / 4, the specific trigonometric function value generation unit generates a pair of trigonometric function values. , Converts the rotator index into an address value indicating any address of the storage means. Further, the rotator generating means may convert the pair of trigonometric function values generated by the specific trigonometric function value generating means or the pair of trigonometric function values stored at an address corresponding to the address value obtained by conversion by the converting means. By generating a rotator based on this, an FFT operation can be performed. In addition, at this time, since a pair of trigonometric function values are stored for 周期 cycle, the capacity of the storage means may be small. Furthermore, since the specific trigonometric function value generation unit generates a pair of trigonometric function values that are frequently referred to,
The number of accesses to the storage unit can be reduced as compared with reading and storing the value, and as a result, power consumption can be reduced and the processing speed can be increased.

In a ninth aspect based on the eighth aspect, the rotator index generating means comprises: a clock counting means for outputting a clock value which advances in relation to the clock; and a clock output by the clock counting means. Increment value generating means for generating an increment value in relation to the value, clear signal generating means for generating a clear signal at a predetermined cycle, a rotor index output last time, and an increment value generated by the increment value generating means And a rotor that temporarily holds and outputs the rotor index obtained by the addition, and that is held in accordance with the clear signal generated by the clear signal generator. Holding means for initializing the index.

As described above, in the ninth aspect of the present invention, the rotator index generating means determines, for each butterfly operation, a predetermined number of rotors to be supplied to the arithmetic means among the rotors stored in the storage means. The rotor index of the rotor is generated sequentially. At this time, the clock counting means outputs a clock value which advances in relation to the clock, and the increment value generation means generates an increment value in relation to the clock value output by the clock counting means. The adding means adds the previously output rotator index and the increment value generated by the increment value generating means. The holding means temporarily holds and outputs the rotor index obtained by the addition means,
The clear signal generating means initializes the held rotor index according to a clear signal generated at a predetermined cycle.

As described above, the sequence obtained by arranging the rotor indices of a predetermined number of rotors to be supplied to the calculating means in each butterfly operation in ascending order is an arithmetic sequence having 0 as a first term, In addition, if the butterfly execution order is appropriately selected, focusing on the fact that the sequence obtained by arranging the tolerances of each arithmetic sequence also has a predetermined regularity, the increment value corresponding to the tolerance of each arithmetic sequence is taken into account. Generate Then, by repeating the operation of adding the increment value to the retained previous rotor index and outputting the value, and initializing the retained value to 0 at a predetermined cycle, for each butterfly operation, Rotor indexes of a predetermined number of rotors to be supplied to the arithmetic means can be sequentially generated.

According to a tenth aspect, there is provided an apparatus for performing a fast Fourier transform operation, comprising a pair of trigonometric function values ｛Acos (2π
n / N), Asin (2πn / N)｝ (A is a positive constant,
N is the number of sample points, n = n ₀ , n ₀ +1, n ₀ +2,
...; n ₀ is an arithmetic means for performing storage means arbitrary integer) is stored in the address associated with the n respective predetermined butterfly execution order is set, a plurality of butterfly operations in accordance with the order, a plurality A rotor index generating means for sequentially generating a rotor index of a predetermined number of rotors to be supplied to the calculating means for each of the butterfly operations, and a rotor index generated by the rotor index generating means. To the address value indicating the address of the storage means, and a rotator based on a pair of trigonometric function values stored in the storage means of the storage means at an address corresponding to the address value obtained by the conversion means. Rotator generating means for generating, the rotator generating means having sign bit adding means for adding sign bits indicating positive and negative to a pair of trigonometric function values stored in the storage means. And Nde.

As described above, in the tenth aspect, the storage means stores a pair of trigonometric function values ｛Acos (2πn / N),
Asin (2πn / N)｝ (n = n ₀ , n ₀ +1, n ₀
+2,...) Are stored at addresses associated with n. A predetermined butterfly execution order is set in the arithmetic unit, and the arithmetic unit executes a plurality of butterfly operations in accordance with the order. The rotor index generating means includes:
For each butterfly operation, a rotor index of a predetermined number of rotors to be supplied to the operation means is sequentially generated.
The converting means converts the rotator index generated by the rotator index generating means into an address value indicating any address of the storage means. The rotator generation means generates a rotator based on a pair of trigonometric function values stored in the storage means at an address corresponding to the address value obtained by the conversion by the conversion means. At this time, the sign bit adding means adds sign bits indicating positive and negative to each of the pair of trigonometric function values.

Thus, a pair of trigonometric function values ｛Acos
(2πn / N), Asin (2πn / N)｝ (n =
_{n 0, n 0 + 1,} n 0 + 2, ... an), while allowed to store the address associated with n in each storage means, the rotor-index generating means, for each butterfly operation, rotated by a predetermined number of required Generate child rotator indexes sequentially.
Then, the conversion means converts the rotor index into an address value indicating any address of the storage means. Further, the rotator generation means can perform the FFT operation by generating a rotator based on a pair of trigonometric function values stored at an address corresponding to the address value obtained by conversion by the conversion means. Moreover, when the rotator is generated, a sign bit indicating positive or negative is added to each of the pair of trigonometric function values, so that the scale of the apparatus can be reduced as compared with inverting the sign of each of the pair of trigonometric function values. This is for the following reason. That is, when a rotator is generated by inverting the sign of a pair of trigonometric function values, two 2's complementing circuits for inverting the sign are required, and the generated rotator and input value are used at the time of butterfly operation. Therefore, one two's complement circuit is required for complex multiplication with, so that a total of three two's complement circuits are required. On the other hand, if a rotator is generated by adding a sign bit to a pair of trigonometric function values, if there are two two's complement circuits for complex multiplication of the generated rotator and the input value at the time of butterfly operation, Good. In the circuit for adding the sign bit and the two's complement circuit, since the two's complement circuit is larger in scale, compared to generating the rotator by inverting the sign of the trigonometric function value, The size of the device can be reduced.

According to an eleventh aspect, in the tenth aspect,
The rotator index generating means includes: a clock counting means for outputting a clock value that advances in relation to the clock; and an increment value generating means for generating an increment value in relation to the clock value output by the clock counting means. A clear signal generating means for generating a clear signal at a predetermined cycle, an adding means for adding a previously output rotor index, and an increment value generated by the increment value generating means, Holds and outputs the rotator index temporarily, and
Holding means for initializing the held rotor index in response to the clear signal generated by the clear signal generating means.

As described above, in the eleventh aspect, the rotor index generating means includes a predetermined number of rotors to be supplied to the calculating means among the rotors stored in the storing means for each butterfly calculation. The rotor index of the rotor is generated sequentially. At this time, the clock counting means outputs a clock value which advances in relation to the clock, and the increment value generation means generates an increment value in relation to the clock value output by the clock counting means. The adding means adds the previously output rotator index and the increment value generated by the increment value generating means. The holding means temporarily holds and outputs the rotor index obtained by the adding means, and also holds the rotor index held by the clear signal generating means in response to a clear signal generated at a predetermined cycle. Initialize the box.

As described above, any sequence obtained by arranging the rotor indexes of a predetermined number of rotors to be supplied to the calculating means in each butterfly operation in ascending order is an arithmetic sequence having 0 as a first term, In addition, if the butterfly execution order is appropriately selected, focusing on the fact that the sequence obtained by arranging the tolerances of each arithmetic sequence also has a predetermined regularity, the increment value corresponding to the tolerance of each arithmetic sequence is taken into account. Generate Then, by repeating the operation of adding the increment value to the retained previous rotor index and outputting the value, and initializing the retained value to 0 at a predetermined cycle, for each butterfly operation, Rotor indexes of a predetermined number of rotors to be supplied to the arithmetic means can be sequentially generated.

[0048]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the fast Fourier transform operation device according to the first embodiment of the present invention. 1 includes a rotator index generation circuit 10, a table 11, and a calculation unit 12. The rotator index generation circuit 10 includes a clock counter 101, an increment value generation circuit 102, a clear signal generation circuit 103, an adder 104, and a register 105.
including.

The table 11 (coefficient memory) stores rotators. The operation unit 12 performs a butterfly operation. The rotator index generation circuit 10 sequentially generates rotator indexes of the rotators to be supplied to the arithmetic unit 12 among the rotators stored in the table 11. The clock counter 101 outputs a clock value that increases by one clock. Incremental value generation circuit 1
02 generates an increment value in relation to the clock value. The adder 104 adds the rotor index output one clock before and the increment value. Clear signal generation circuit 1
03 generates a clear signal every four clocks. The register 105 sets the rotor index obtained by the addition to 1
The clock is held and output, and the held rotor index is initialized according to the clear signal.

FIG. 2 is a signal flow chart showing an example of a radix-4 FFT operation. The calculation shown in FIG.
(= 4 ³⁾ a time FFT operation called thinning type, respectively 16 times in the first to third stage, the butterfly operation of a total of 48 times, by executing number (0-47) in this order, f (0) 64 output values of F (0) to F (63) are obtained for 64 input values of f (63) to f (63).

FIG. 3 is a diagram showing the rotor index of the rotor used in each butterfly operation (execution order 0 to 47) of the operation of FIG. 2 and 3
, The butterfly execution order and the rotator index are both displayed in decimal, and in FIG. 2, the necessary four rotator indexes are all 0, and the rotator index ( That is,
0) is omitted.

The operation of performing the operation of FIG. 2 by the apparatus of FIG. 1 will be described below with reference to FIGS. In order to perform the FFT operation of FIG. 2 with the apparatus of FIG. 1, for each butterfly operation,
The four rotors as shown in FIG.
Need to be supplied. Therefore, in the apparatus of FIG. 1, all the rotors to be supplied are stored in the table 11 in advance. At that time, the rotor index added to each rotor is stored so that the address where each rotor is stored matches. On the other hand, if the rotor index generation circuit 10 sequentially generates four rotor indexes similar to those shown in FIG. 3 for each butterfly operation, the rotor index generation circuit 10 stores the rotor indexes stored in the table 11. Of these, the rotator stored at the address corresponding to the generated rotator index is read out and supplied to the calculation unit 12, so that the calculation in FIG. 2 can be performed.

Here, as is clear from FIG. 3, the sequence obtained by arranging the rotor indices of the four rotors necessary for each butterfly operation in ascending order is an arithmetic sequence with 0 as the first term. is there. In the operation of FIG. 2, since the butterfly execution order is appropriately selected, the sequence obtained by arranging the tolerances of the arithmetic progression sequences has regularity.

Therefore, the clock counter 101 outputs a clock value that advances by one clock, and the increment value generation circuit 102 corresponds to the above-described tolerance in relation to the clock value output by the clock counter 101. To generate an increment value. The adder 104 adds the rotator index output one clock before and the increment value generated by the increment value generation circuit 102. On the other hand, the clear signal generation circuit 10
3 generates a clear signal every four clocks,
Reference numeral 05 denotes a rotor index obtained by the addition by the adder 104, which is held for one clock and is output, and the held rotor index is held in response to the clear signal generated by the clear signal generating circuit 103. Initialize to 0. Accordingly, the rotor index generation circuit 10 sequentially outputs the rotor indices of the four rotors to be supplied to the operation unit 12, that is, the rotor index sequence similar to that in FIG. Can be generated.

The timing at which the clear signal generating circuit 103 should generate a clear signal, that is, the time interval of four clocks, can be obtained by NORing the lower two bits of the clock value (Negation of logical sum).

FIG. 4 shows a case where the FFT operation of FIG. 2 is performed.
The values (10) transmitted at points a to d of the apparatus of FIG.
6 is a timing chart showing a temporal change of a hexadecimal display).
As shown in FIG. 4, the numerical value (clock value) transmitted at the point a increases by 1 every clock with the initial value being 0,
Initialized to 0 for each operation stage. The numerical values (increment values) transmitted at the point b are all 0 in the first stage, and in the second stage, the initial value is 0, and 4, 8, 12, 0, 4, 8, 12 every 4 clocks. , ..., 0,4,8,1
It changes to 2. Also, in the third stage, the initial value changes to 1, 2,..., 15 every four clocks with the initial value being 0. At point c, a pulse signal (clear signal) is transmitted every four clocks.

The adder 104 calculates the rotator index one clock before and the increment value (b) held in the register 105.
) And the result is given to the register 105 again. on the other hand,
The register 105 stores the given rotator index in 1
The clock is held and output, but the held rotor index is initialized to 0 according to the clear signal (point c). Therefore, in the first stage, the rotor index transmitted at point d is {0, 0, 0, 0},.
{0,0,0,0}, in the second stage, {0,0,
0, 0}, {0, 4, 8, 12}, {0, 8, 16, 2
4}, {0, 12, 24, 36}, ..., {0, 0, 0,
0}, {0, 4, 8, 12}, {0, 8, 16, 2}
4}, {0, 12, 24, 36}, in the third stage,
{0, 0, 0, 0}, {0, 1, 2, 3}, {0, 2,
4, 6},..., {0, 15, 30, 45}.

As described above, the operation unit 1 is used in each butterfly operation.
The sequence obtained by arranging the rotor indices of the four rotors to be supplied to 2 in ascending order is an arithmetic progression with 0 as a first term, and the butterfly execution order is appropriately selected. For example, focusing on the fact that a sequence obtained by arranging the tolerances of each arithmetic sequence also has a predetermined regularity, an increment value corresponding to the tolerance of each arithmetic sequence is generated every clock,
The increment value is added to the rotator index one clock before. By initializing the rotor index thus obtained to 0 every four clocks, the rotor index generation circuit 10 sequentially generates a rotor index sequence equivalent to that of FIG. 3 for each butterfly operation. Can be generated automatically.

Incidentally, the increment value generation circuit 102 can generate an increment value based on the clock value output from the clock counter 101 as follows. That is, in the first stage, after removing the lower 2 bits of the 6-bit clock value output by the clock counter 101, the remaining 4 bits are replaced with 0, respectively. In the second stage, the 6 bits output by the clock counter 101 are output. After removing the upper 2 bits of the clock value of the bit, the lower 2 bits of the remaining 4 bits are replaced with 0, respectively. In the third stage, the lower 2 bits of the 6-bit clock value output by the clock counter 101 are removed. do it. The progress of the operation stage can be determined based on the clock value.

As described above, according to the present embodiment, FIG.
A rotator index sequence similar to that of the above can be sequentially generated, and as a result, a radix-4 FFT operation can be performed.

In the present embodiment, the FFT operation is of the time thinning type, but may be of the frequency thinning type.

In the apparatus shown in FIG.
By inverting all the signs of the imaginary part of the rotator stored in, the inverse FFT operation can be performed.

In addition to the radix-4 FFT operation,
In the T operation, generally, a sequence obtained by arranging the rotor indexes of a predetermined number of rotors to be supplied to the operation unit 12 in each butterfly operation in ascending order is an arithmetic sequence having 0 as a first term, and If the butterfly execution order is appropriately selected, the sequence obtained by arranging the tolerances of the arithmetic progression sequences also has a predetermined regularity. Therefore, as described above, the operation of generating an increment value corresponding to the tolerance of each arithmetic progression, adding the increment value to the held previous rotor index, and outputting the result is repeated. Then, by initializing the held value to 0 at a predetermined cycle, each time the butterfly operation is performed,
Rotor indices of a predetermined number of rotors to be supplied to the operation unit 12 can be sequentially generated, and as a result, FFT operation of an arbitrary radix can be performed.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. FIG.
FIG. 6 is a block diagram illustrating a configuration of a fast Fourier transform operation device according to a second embodiment of the present invention. The device of FIG.
In the apparatus of FIG. 1, the rotor index generation circuit 10
And a rotor index generation circuit 10a. The rotator index generation circuit 10a further includes a stage counter 501 in the rotator index generation circuit 10 of FIG.
, An incremental value generation circuit 102a is included.

The stage counter 501 outputs a stage value such as to advance for each operation stage. The increment value generation circuit 102a generates an increment value in association with the clock value and the stage value. Other components perform operations similar to the corresponding ones in FIG.

FIG. 6 is a signal flow chart showing another example of the radix-4 FFT operation. The operation in FIG. 6 is similar to the operation in FIG. 2 except that the order of butterfly execution in the second stage is different. FIG. 7 is a diagram illustrating a rotor index of the rotor used in each butterfly operation (execution order 0 to 47) of the operation in FIG. 6. 6 and 7, the butterfly execution order and the rotor index are all displayed in decimal.
, The required four rotor indexes are all 0
The description of the rotor index (that is, 0) is omitted in the butterfly operation of (1).

The operation of performing the operation of FIG. 6 by the apparatus of FIG. 5 will be described below with reference to FIGS. In order to perform the operation of FIG. 6 with the apparatus of FIG. 5, four rotors as shown in FIG. 7 need to be supplied to the operation unit 12 for each butterfly operation. Therefore, in the apparatus of FIG. 5, all the rotors to be supplied are stored in the table 11 in advance. At that time, the rotor index added to each rotor is stored so that the address where each rotor is stored matches. On the other hand, if the rotor index generation circuit 10a can sequentially generate four rotor indexes similar to the one shown in FIG. The rotator stored at the address corresponding to the generated rotator index is read out and supplied to the arithmetic unit 12.

Here, as is clear from FIG. 7, the sequence obtained by arranging the rotor indices of the four rotors necessary for each butterfly operation in ascending order is an arithmetic progression with 0 as the first term. is there. In the operation shown in FIG. 6, the butterfly execution order is selected so that the butterfly operation in which all the necessary four rotators match is performed continuously, and the tolerances of the arithmetic progression are arranged. The obtained sequence has regularity for each operation stage.

Therefore, the clock counter 101 outputs a clock value that advances by one clock, and
The stage counter 501 outputs a stage value that advances by one operation stage. Increment value generation circuit 102
“a” generates an increment value corresponding to the above-mentioned tolerance in relation to the clock value output from the clock counter 101 and the stage value output from the stage counter 501. The adder 104 adds the rotator index output one clock before and the increment value generated by the increment value generation circuit 102a. On the other hand, the clear signal generation circuit 103 generates a clear signal every four clocks, the register 105 holds the rotor index obtained by the addition by the adder 104 for one clock, outputs the held rotor index, and generates the clear signal. Circuit 103
The stored rotor index is initialized to 0 in response to the clear signal in which. Accordingly, the rotor index generation circuit 10a generates, for each butterfly operation, the rotor indexes of the four rotors to be supplied to the operation unit 12, that is, the rotor index sequence similar to that of FIG. Can be generated sequentially.

The timing at which the clear signal generation circuit 103 should generate a clear signal, that is, the time interval of four clocks, can be obtained by taking the NOR (negation of logical sum) of the lower two bits of the clock value.

FIG. 8 is a timing chart showing the time change of the numerical values (decimal notation) transmitted to the points a to e of the apparatus of FIG. 5 when the operation of FIG. 6 is performed. FIG.
Numerical value transmitted at point a (stage value) as shown in
Increases by one for each operation stage with the initial value set to 0. The numerical value (clock value) transmitted at the point b is incremented by 1 every clock with the initial value being 0, and is initialized to 0 for each operation stage. Numeric value (incremental value) transmitted at point c
Are all 0 in the first stage, and in the second stage, the initial value is 0, and 4, 8, 12
And change. Also, in the third stage, the initial value changes to 1, 2,..., 15 every four clocks with the initial value being 0. Also,
At point d, a pulse signal (clear signal) is transmitted every four clocks.

The adder 104 calculates the rotator index one clock before and the increment value (c) held in the register 105.
) And the result is given to the register 105 again. On the other hand, the register 105 holds the given rotor index for one clock and outputs the same, but the clear signal (point d)
, The held rotor index is initialized to zero. Therefore, in the first stage, the rotor index transmitted at point e is {0, 0, 0, 0},.
{0,0,0,0}, in the second stage, {0,0,
0,0} four times, then {0,4,8,12} four times, and {0,8,16,24} four times, and {0,1
2, 24, 36} four times, and in the third stage, {0,
0, 0, 0}, {0, 1, 2, 3}, {0, 2, 4,
6},..., {0, 15, 30, 45}.

As described above, in each butterfly operation, the operation unit 1
The sequence obtained by arranging the rotor indices of the four rotors to be supplied to 2 in ascending order is an arithmetic progression with 0 as a first term, and the butterfly execution order is appropriately selected. For example, focusing on the fact that a sequence obtained by arranging the tolerances of each arithmetic sequence also has a predetermined regularity, an increment value corresponding to the tolerance of each arithmetic sequence is generated every clock,
The increment value is added to the rotator index one clock before. By initializing the rotor index thus obtained to 0 every four clocks, the rotor index generation circuit 10a sequentially generates a rotor index sequence similar to that of FIG. 7 for each butterfly operation. Can be generated automatically.

The increment value generating circuit 102a can generate an increment value based on the clock value output from the clock counter 101 and the stage value output from the stage counter 501 as follows. That is, in the first stage, after removing the lower 2 bits of the 6-bit clock value output by the clock counter 101, the remaining 4 bits are replaced with 0, respectively. In the second stage, the 6 bits output by the clock counter 101 are output. After removing the lower two bits of the clock value of the bit, the lower two bits of the remaining four bits are each replaced with 0. In the third stage, the lower two bits of the 6-bit clock value output by the clock counter 101 are removed. do it.

[0075] When the sample number is 4 ^4, increment generation circuit 102a is as follows, it is possible to generate the increment value. That is, in the first stage, after removing the lower 2 bits of the 8-bit clock value output by the clock counter 101, the remaining 6 bits are replaced with 0, respectively, and in the second stage, the 8 bits output by the clock counter 101 are output. Lower 2 of clock value of bit
After removing the bits, the lower 4 bits of the remaining 6 bits are replaced with 0, respectively. In the third stage, after removing the lower 2 bits of the 8-bit clock value output by the clock counter 101, the remaining 6 bits are removed. In the fourth stage, the lower two bits of the 8-bit clock value output by the clock counter 101 may be removed.

Further, the number of sample points is 4 ^m (where m
Is an arbitrary integer of 2 or more), the increment value generation circuit 102 can generate an increment value as follows. That is, the k-th stage (where k = 1,
.., M) is 2 m output from the clock counter 101.
After removing the lower 2 bits of the bit clock value, the lower 2 (mk) bits of the remaining 2 (m-1) bits may be replaced with 0, respectively.

As described above, according to the present embodiment, FIG.
Can generate a rotator index sequence similar to that described above, and as a result, can perform a radix-4 FFT operation. Also,
By selecting the butterfly execution order such that the butterfly operations in which all of the necessary four rotators are all the same are executed consecutively, the frequency at which the increment value changes is reduced, and as a result, in particular, CMOS When a circuit is configured using transistors, power consumption is reduced as compared with the first embodiment.

In the present embodiment, the FFT operation is of the time thinning type, but may be of the frequency thinning type.

In the apparatus shown in FIG. 1, an inverse FFT operation can also be performed by inverting all the signs of the imaginary part of the rotor stored in the table 11.

Furthermore, not only the radix-4 FFT operation but also the radix-FFT operation can be performed. In this case, similarly to the above, the operation of generating an increment value corresponding to the tolerance of each arithmetic progression, adding the increment value to the held previous rotor index, and outputting the result is repeated. Then, the held value may be initialized to 0 at a predetermined cycle.

(Third Embodiment) Hereinafter, a third embodiment of the present invention will be described with reference to the drawings. FIG.
FIG. 9 is a block diagram illustrating a configuration of a fast Fourier transform operation device according to a third embodiment of the present invention. The device of FIG.
The apparatus of FIG. 5 further includes a conversion circuit 901, a specific trigonometric function value generation circuit 902, and a rotator generation circuit 903, and further includes a table 11a instead of the table 11.

FIG. 10 is a diagram showing a pair of trigonometric function values stored at each address (addresses 0 to 7) of the table 11a in FIG. As shown in FIG. 10, the table 11a includes a pair of trigonometric function values ｛cos (2πn / 64), si
n (2πn / 64)｝ (where n = 1, 2,..., 8)
Are stored at addresses (n-1).

The specific trigonometric function value generation circuit 902 generates a pair of trigonometric function values {1, 0} when the rotator index generated by the rotator index generation circuit 10a is an integral multiple of 16. . When the rotator index generated by the rotator index generation circuit 10a is not an integral multiple of 16, the conversion circuit 901 performs a predetermined bit operation on the rotator index, and performs any one of the addresses in the table 11a. To an address value indicating. The rotator generation circuit 903 converts the pair of trigonometric function values generated by the specific trigonometric function value generation circuit 902 or the address value obtained by conversion by the conversion circuit 901 from the trigonometric function values stored in the table 11a. A rotator is generated based on a pair of trigonometric function values stored at the matching address. Other components are:
Each performs the same operation as the corresponding one in FIG.

The operation of the apparatus of FIG. 9 performing the FFT operation of FIG. 6 will be described below with reference to FIGS. 6, 7, 9 and 10. The operation of generating the rotor index by the rotor index generation circuit 10a of FIG. 9 is the same as the operation of the rotor index generation circuit 10a of FIG.

When the rotator index generated by the rotator index generation circuit 10a is an integral multiple of 16,
Specific trigonometric function value generation circuit 902 generates a pair of trigonometric function values {1, 0}. Rotor index generation circuit 1
If the rotator index generated by 0a is not an integral multiple of 16, the conversion circuit 901 performs a predetermined bit operation on the rotator index to obtain an address value indicating any address in the table 11a. Convert. Then, the rotator generation circuit 903 generates the specific trigonometric function value generation circuit 902
Generates a pair of trigonometric function values or a table 11a
The rotator is generated based on a pair of trigonometric function values stored at an address corresponding to the address value obtained by conversion by the conversion circuit 901 among the trigonometric function values stored in.

FIG. 11 is a diagram for explaining the operation of the rotator generation circuit 903 of FIG. 9 for generating a rotator. Hereinafter, an operation in which the rotator generation circuit 903 generates a rotator will be described with reference to FIG. When the generated rotator index is a multiple of 16 (in decimal notation), that is, when the lower 4 bits are all 0 (in binary notation), the specific trigonometric function value generation circuit 902 generates a pair of trigonometric function values ｛1 , 0｝
Is generated and output to the rotator generation circuit 903 side.

If at least one of the lower 4 bits is not 0, the conversion circuit 901 converts the generated rotator index into an address value corresponding to the address of the table 11a, and outputs it to the table 11a. I do. In addition,
The address value obtained by the conversion can be expressed as shown in FIG. 11, where i is the lower 3 bits of the rotator index and j is the 1's complement of i. The table 11a stores trigonometric function values as shown in FIG.
Are stored as a pair at addresses 0 to 7, respectively.
The trigonometric function value stored at the address corresponding to the converted address value is read from the table 11a and provided to the rotator generation circuit 903.

The rotator generation circuit 903 assigns a given pair of trigonometric function values as a real part and an imaginary part of the rotator as shown in FIG. 11, and then inverts the signs as necessary. The rotator generated in this way is supplied to the calculation unit 12.

As described above, according to this embodiment, among the trigonometric function values for generating the rotator, a pair of trigonometric function values ｛cos (2πn / 64) and sin (2πn / 6)
4)｝ (where n = 1, 2,..., 8) is stored in the address (n−1) of the table 11a. Then, the rotor index generation circuit 10a sequentially generates the necessary rotor index of the rotor for each butterfly operation.

When the generated rotator index is an integer multiple of 16, the specific trigonometric function value generation circuit 902 generates a pair of trigonometric function values {1, 0}, while the generated rotator index is generated. If the index is not an integral multiple of 16, the conversion circuit 901 performs a predetermined bit operation on the rotator index to convert the rotator index into an address value indicating any address of the table 11a.

Next, the rotator generation circuit 903 generates a pair of trigonometric function values generated by the specific trigonometric function value generation circuit 902,
Alternatively, of the trigonometric function values stored in the table 11a, based on a pair of trigonometric function values stored at an address corresponding to the address value obtained by conversion by the conversion circuit 901,
By generating the rotator, the rotator necessary for each butterfly operation is supplied to the operation unit 12, and as a result, the operation of FIG. 6 can be performed. Further, since a pair of trigonometric function values are stored in the table 11a for １ ／ cycle, the capacity of the table 11a may be small. Further, since the specific trigonometric function value generation circuit 902 generates a pair of trigonometric function values that are frequently referred to, that is, {1, 0}, without storing them in the table 11a, the number of accesses to the table 11a can be reduced. As a result, the power consumption can be reduced and the processing speed is increased.

The effect that the capacity of the table 11a can be reduced and the effect that the number of accesses to the table 11a can be reduced, as a result, the power consumption can be reduced and the processing speed is increased are shown in FIG. This device can be obtained even if the above device is provided with another rotor index generation circuit in place of the rotor index generation circuit 10a.

Also, instead of the table 11a, 1/8
A pair of trigonometric function values ｛Acos (2πn / N) for the period,
Asin (2πn / N)｝ (A is a positive constant, N is the number of sample points, n = n ₀ +1, n ₀ +2,..., N ₀ + N / 8;
Other tables may be provided such that n ₀ = r · N / 8, where r is any integer) is stored at the address associated with n. However, in this case, the rotor index generation circuit 1
0a sequentially generates the necessary rotor indexes of the four rotors for each butterfly operation. Then, if the generated rotor index is an integral multiple of N / 4,
The specific trigonometric function value generation circuit 902 generates a pair of trigonometric function values predetermined in relation to r (for example, when r = 0, ｛A,
0}, when r = 1, {0, A},...
If not, the conversion circuit 901 converts the rotator index into an address value indicating any address in the table 11a. Further, the rotator generation circuit 90
3 is rotated based on a pair of trigonometric function values generated by the specific trigonometric function value generation circuit 902 or a pair of trigonometric function values stored at an address corresponding to an address value obtained by conversion by the conversion circuit 901. Create a child.

Also, by inverting all the signs of the imaginary part in FIG. 11, an inverse FFT operation is possible.

(Fourth Embodiment) Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings. FIG.
FIG. 2 is a block diagram illustrating a configuration of a fast Fourier transform operation device according to a fourth embodiment of the present invention. The device of FIG. 12 includes a rotator generation circuit 903a instead of the rotator generation circuit 903 and a calculation unit 12a instead of the calculation unit 12 in the device of FIG.

FIG. 13 shows the rotator generation circuit 903 of FIG.
FIG. 3 is a block diagram showing a configuration of a and a calculation unit 12a.
The rotator generation circuit 903a includes an assignment circuit 1301 and a sign bit addition circuit 1302. Arithmetic unit 1
2a is a multiplier 1303, a pair of 2's complement circuits 130
4 and an adder 1305.

The allocating circuit 1301 allocates a pair of trigonometric function values as a real part and an imaginary part of the rotator.
The sign bit adding circuit 1302 adds sign bits indicating positive and negative to the trigonometric function value. The multiplier 1303 performs complex multiplication. The two's complement circuit 1304 performs the sign inversion by complementation. The adder 1305 performs addition.

FIG. 14 is a block diagram showing the configurations of the rotator generation circuit 903 and the operation unit 12 in FIG. The rotator generation circuit 903 includes an assignment circuit 1301 and a pair of two's complement circuits 1304. The calculation unit 12
It includes a multiplier 1303, a two's complement circuit 1304, and an adder 1305. Each component in FIG.
Performs the same operation as that corresponding to.

The operation of the apparatus shown in FIG. 12 differs from that of the apparatus shown in FIG. 9 in that the sign processing of the positive and negative trigonometric function values at the time of generating the rotor and the rotator and input value at the time of butterfly operation are performed. Since only the part relating to the complex multiplication is described, the operation of the apparatus of FIG. 12 for generating a rotator and for performing the complex multiplication of the rotator and an input value will be described with reference to FIGS. 9 will be described in comparison with the operation of the ninth apparatus.

In the rotator generation circuit 903a of FIG. 13, the assignment circuit 1301 assigns a pair of trigonometric function values read from the table 11a as a real part and an imaginary part of the rotator. The sign bit adding circuit 1302 adds sign bits indicating positive or negative to the assigned trigonometric function values. The rotator generated in this way is the arithmetic unit 12
is supplied to the arithmetic unit 12a, the multiplier 1303
Multiplies the real part of the input value (for example, α) and the real part of the rotor (for example, | γ |), and the real part of the input value (for example, β) and the real part of the rotor (for example, | δ |). . Then, after a pair of two's complement circuits 1304 invert the signs of the multiplication results as necessary, an adder 1305 adds them.

On the other hand, in the rotator generation circuit 903 of FIG. 14, the allocation circuit 1301 allocates a pair of trigonometric function values read from the table 11a as a real part and an imaginary part of the rotator. A pair of two's complement circuits 1304
Respectively inverts the assigned trigonometric function values as necessary. When the rotator generated in this way is supplied to the calculation unit 12, the calculation unit 12
Multiplies the real part of the input value (for example, α) and the real part of the rotor (for example, | γ |), and the real part of the input value (for example, β) and the real part of the rotor (for example, | δ |). Then, the two's complement circuit 1304 inverts the sign of one of the multiplication results as necessary, and then adds them together.

As described above, each of the devices shown in FIGS. 9 and 12 can generate a necessary rotator and execute a butterfly operation, but the device shown in FIG.
3 and the operation unit 12, the two's complement circuit 1304
In contrast, the apparatus of FIG. 12 includes only two two's complement circuits 1304 in the rotator generation circuit 903a and the arithmetic unit 12a. instead of,
Although the device of FIG. 12 includes a sign bit adding circuit 1302, the scale of the sign bit adding circuit 1302 is relatively smaller than the scale of the two's complement circuit 1304.
The size of the device in FIG. 12 can be said to be relatively smaller than the size of the device in FIG.

As described above, according to the present embodiment, a rotator is generated by adding a sign bit indicating positive / negative to a pair of trigonometric function values. , The size of the device can be made smaller.

The above effects can be obtained even if the apparatus shown in FIG. 12 is provided with another rotor index generation circuit instead of the rotor index generation circuit 10a.

Also, instead of the table 11a, a pair of trigonometric function values ｛Acos (2πn / N), Asin (2π
n / N)｝ (A is a positive constant, N is the number of sample points, n = n
₀ , n ₀ +1, n ₀ +2,...; N ₀ is an arbitrary integer) may be provided with other tables each stored at an address associated with n.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a fast Fourier transform operation device according to a first embodiment of the present invention.

FIG. 2 is a signal flow diagram illustrating an example of a radix-4 FFT operation.

FIG. 3 is a diagram illustrating a rotor index of a rotor used in each butterfly operation of the operation of FIG. 2;

FIG. 4 is a block diagram of the apparatus shown in FIG.
It is a timing chart which shows a time change of the numerical value transmitted each point.

FIG. 5 is a block diagram illustrating a configuration of a fast Fourier transform operation device according to a second embodiment of the present invention.

FIG. 6 is a signal flow chart illustrating another example of a radix-4 FFT operation.

FIG. 7 is a diagram showing a rotor index of a rotor used in each butterfly operation of the operation of FIG. 6;

8 is a diagram showing the operation of the apparatus shown in FIG.
It is a timing chart which shows a time change of the numerical value transmitted each point.

FIG. 9 is a block diagram illustrating a configuration of a fast Fourier transform operation device according to a third embodiment of the present invention.

FIG. 10 is a diagram showing a pair of trigonometric function values stored at each address of a table 11a in FIG. 9;

FIG. 11 is a diagram for explaining an operation in which the rotator generation circuit 903 of FIG. 9 generates a rotator.

FIG. 12 is a block diagram illustrating a configuration of a fast Fourier transform operation device according to a fourth embodiment of the present invention.

13 is a block diagram illustrating a configuration of a rotator generation circuit 903a and a calculation unit 12a of FIG.

14 is a diagram illustrating a rotator generation circuit 903 and an operation unit 1 of FIG. 9;
2 is a block diagram showing a configuration of FIG.

FIG. 15 is a signal flow diagram illustrating an example of a radix-2 FFT operation.

16 is a diagram for explaining a relationship between an execution order of butterfly operations and a rotor index of a rotor required for each butterfly operation in the operation of FIG.

[Explanation of symbols]

 10, 10a Rotor index generation circuit 11, 11a Table 12, 12a Operation unit 101 Clock counter 102, 102a Increment value generation circuit 103 Clear signal generation circuit 104, 1305 Adder 105 Register 501 Stage counter 901 Conversion circuit 902 Specific trigonometric function Value generation circuit 903, 903a Rotor generation circuit 1301 Assignment circuit 1302 Sign bit addition circuit 1303 Multiplier 1304 Complementation circuit of 3042

Claims (11)

[Claims] 1. An apparatus for performing a fast Fourier transform operation, wherein a plurality of different rotators are respectively stored at addresses associated with rotator indexes assigned to the plurality of rotators. A predetermined butterfly execution order is set, and an operation means for executing a plurality of butterfly operations in accordance with the order; A rotor index generating means for sequentially generating rotor indexes of a predetermined number of rotors, wherein the rotor index generating means outputs a clock value such as to advance in relation to a clock. Clock counting means, increment value generating means for generating an increment value in relation to the clock value output by the clock counting means, and a clear signal at a predetermined cycle. Clear signal generating means, a rotor index output last time, an adding means for adding the increment value generated by the increment value generating means, and a rotor index obtained by adding the adding means. And a holding unit that temporarily holds and outputs the stored index and initializes the held rotor index in response to the clear signal generated by the clear signal generating unit. 2. The fast Fourier transform operation device according to claim 1, wherein said clear signal generating means obtains a generation timing of a clear signal based on a clock value output by said clock counting means. 3. The butterfly execution order set in the operation means is an order in which butterfly operations in which a predetermined number of rotors to be supplied to the operation means all coincide are continuously executed. 2. The fast Fourier transform operation device according to claim 1, wherein: 4. An apparatus for performing a radix-4 fast Fourier transform operation, wherein a plurality of different rotators are stored at addresses associated with rotator indexes assigned to the plurality of rotators, respectively. Storage means, a predetermined butterfly execution order is set, and operation means for executing a plurality of butterfly operations in accordance with the order; and for each of the plurality of butterfly operations, read from the storage means and supplied to the operation means Rotor index generation means for sequentially generating rotor indexes of four rotors to be performed, wherein the rotor index generation means outputs a clock value such that the clock value is incremented every clock. Clock counting means for generating, an increment value generating means for generating an increment value in relation to the clock value output by the clock counting means, a clear signal every four clocks A clear signal generating means for generating the following; an adding means for adding the rotor index output one clock before, and the increment value generated by the increment value generating means; Holding means for holding and outputting the rotor index for one clock and initializing the held rotor index in response to the clear signal generated by the clear signal generating means. Arithmetic unit. 5. The fast Fourier transform operation device according to claim 4, wherein said clear signal generation means obtains a generation timing of a clear signal based on a clock value output by said clock counting means. 6. The butterfly execution order set in said arithmetic means is such that butterfly operations such that all four rotors to be supplied to said arithmetic means coincide with each other are continuously executed. The fast Fourier transform operation device according to claim 4, characterized in that: 7. The radix-4 fast Fourier transform operation includes:
This is an operation in which the number of sample points is 4 ^m (where m is an arbitrary integer of 2 or more).
.., M), the lower 2 bits of the 2m-bit clock value output by the clock counting means are removed, and then the lower 2 (m−k) bits of the remaining 2 (m−1) bits are replaced with 0, respectively. 7. The fast Fourier transform operation device according to claim 6, wherein an incremental value is generated by performing the operation. 8. An apparatus for performing a fast Fourier transform operation, comprising a pair of trigonometric function values ｛Acos (2πn /
N), Asin (2πn / N)｝ (A is a positive constant, N is the number of sample points, n = n ₀ +1, n ₀ +2,..., N ₀ + N
/ 8; n ₀ = r · N / 8, where r is an arbitrary integer), and a predetermined butterfly execution order is set, and a plurality of butterflies are set in accordance with the order. Calculating means for performing a calculation; rotor index generating means for sequentially generating a rotor index of a predetermined number of rotors to be supplied to the calculating means for each of the plurality of butterfly calculations; Specific trigonometric function value generating means for generating a pair of trigonometric function values predetermined in relation to r, when the rotor index generated by the child index generating means is an integral multiple of N / 4; Conversion means for converting the rotor index into an address value indicating the address of the storage means, when the rotor index generated by the rotor index generation means is not an integral multiple of N / 4; Based on a pair of trigonometric function values generated by the specific trigonometric function value generating unit or a pair of trigonometric function values stored in the storage unit at an address corresponding to an address value obtained by conversion by the conversion unit. And a rotator generating means for generating a rotator. 9. The rotator index generating means includes: a clock counting means for outputting a clock value which advances in relation to a clock; and an increment value for the clock value output by the clock counting means. An increment value generating means for generating; a clear signal generating means for generating a clear signal at a predetermined cycle; an adding means for adding a previously output rotor index to the increment value generated by the increment value generating means; , The rotor index obtained by the addition means is temporarily held and output, and the held rotor index is initialized according to the clear signal generated by the clear signal generating means. 9. The fast Fourier transform operation device according to claim 8, further comprising a holding unit that performs the operation. 10. An apparatus for performing a fast Fourier transform operation, comprising: a pair of trigonometric function values ｛Acos (2πn / N);
(2πn / N)｝ (A is a positive constant, N is the number of sample points,
_{n = n 0, n 0 +} 1, n 0 + 2, ...; n 0 is a storage means for an arbitrary integer) is stored in the address associated with the n respective predetermined butterfly execution order is set, the sequence Calculating means for executing a plurality of butterfly operations in accordance with the following, and for each of the plurality of butterfly operations, a rotor index generating means for sequentially generating a rotor index of a predetermined number of rotors to be supplied to the calculating means Conversion means for converting the rotor index generated by the rotor index generation means into an address value indicating the address of the storage means; and an address value of the storage means obtained by conversion by the conversion means. Rotator generation means for generating a rotator based on a pair of trigonometric function values stored at an address corresponding to: a pair of trigonometric functions stored in the storage means. A fast Fourier transform operation device including a sign bit adding means for adding sign bits indicating positive or negative to a numerical value. 11. The rotator index generating means includes: a clock counting means for outputting a clock value which advances in relation to a clock; and an increment value for the clock value output by the clock counting means. An increment value generating means for generating; a clear signal generating means for generating a clear signal at a predetermined cycle; an adding means for adding a previously output rotor index to the increment value generated by the increment value generating means; , The rotor index obtained by the addition means is temporarily held and output, and the held rotor index is initialized according to the clear signal generated by the clear signal generating means. The fast Fourier transform operation device according to claim 10, further comprising a holding unit that performs the operation.