JPH10334056A - Multiprocessor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multiprocessor system capable of describing a program on the basis of use of a processor in a form not to specialize the description to a processor with specified hardware structure and describing the program on the basis of the use of an optional number of the processors. SOLUTION: The system is provided with a means to assign a process to a virtual processor, a means to assign processors 2a to 2d mounted on the system to the virtual processor, a means SM, 1 to store the virtual processor and the processors 2a to 2d assigned to the virtual processor by relating them and a means to enable the processors 2a to 2d stored in relation to the virtual processors to execute the virtual processors according to a fact that either of the virtual processors are called.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a unified OS (operating system) in which a plurality of processors are combined.
In particular, a multiprocessor system that is a parallel processing system that shares hardware and software resources under the stipulations described above. The present invention relates to a system that can be performed in a manner not specialized for a system and that can be performed on the assumption that an arbitrary number of processors are used.

[0002]

2. Description of the Related Art In various multiprocessor systems such as an SMP (symmetric multiprocessor) system conventionally used in personal computers and the like, all processors as hardware resources use an OS.
Was under the control of

[0003]

As described above, when the processor is under the control of the OS, at the application software level, writing a program on the assumption that the processor is used requires a specific hardware. This is not possible except in a form specific to the system of the configuration.

When a program is described in a form specialized for a system having a specific hardware configuration, the program must be rewritten every time the hardware configuration of the system is changed. Labor and cost losses increase.

Further, when a program is described in a form specialized for a specific system, it is necessary to describe the program on the assumption that a larger number of processors than the number of processors installed in the system are used. This is a constraint on creating application software.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and is intended to describe, at an application software level, a description of a program on the assumption that a processor is used without specializing a system having a specific hardware configuration. It is an object of the present invention to provide a multiprocessor system which can perform the processing on the assumption that an arbitrary number of processors are used.

[0007]

According to the present invention, there is provided a multiprocessor system for allocating a process to be executed in a system to a virtual processor (hereinafter, referred to as a virtual processor), and mounting the process to the virtual processor. Means for allocating the assigned processor (hereinafter, also referred to as a physical processor), means for storing the virtual processor and the physical processor assigned thereto in association with each other, and To the stored physical processor,
Means for executing the virtual processor.

In this multiprocessor system, a concept of a “virtual processor” different from the mounted processor is introduced, and a process to be executed in the system is assigned to the virtual processor. A physical processor is assigned to the virtual processor, and the virtual processor and the physical processor assigned to the virtual processor are stored in association with each other. Then, when one of the virtual processors is called, the physical processor stored in association with the virtual processor executes the virtual processor.

As described above, if access to the processor is made to the virtual processor, the process can be executed by the processor mounted in the system. In other words, if a program is described on the assumption that a virtual processor irrelevant to a specific hardware configuration is used, a processor mounted on the system can be accessed.

Therefore, at the level of the application software, the processor can be accessed by a program described in a form not specialized for a processor having a specific hardware configuration.

[0011] In addition, by assigning processes to a larger number of virtual processors than the number of processors installed in the system, a program is written on the assumption that the number of processors is larger than the number of processors implemented in the system. Will also be able to do it.

[0012]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. << 1. FIG. 1 conceptually shows an example of the configuration of a multiprocessor system according to the present invention. This system includes a plurality of processor elements (P) for executing an OS, application software, and the like.
E) 2 (four PEs 2a to 2d as an example in the figure)
In addition, the processor management unit (PM
U) 1 is provided. The PMU 1 is a type of coprocessor for managing a virtual processor.

Each PE 2 and PMU 1 are connected via a communication bus 3. The communication bus 3 is a bidirectional bus capable of exchanging multi-bit information between arbitrary connected elements.
The system memory SM, which is the main storage device of the system, is also shared by the PEs 2 by being connected to the PEs 2 via the communication bus 3.

<1a. PMU and PETLB> In this multiprocessor system, a unique ID (identification label) is given to each of the virtual processor and each PE2 which is a physical processor. The ID of the virtual processor is “VEID”, and the ID of the physical processor PE2 is “PEI”.
D ".

VEID is described in <3b. As described in <Virtual Processor Generation>, when a new virtual processor is generated after the system is started, the virtual processor is given to the virtual processor by the OS. The PEID is provided by hardware according to the configuration of the system and cannot be changed.

In the PMU 1 (FIG. 1), the VEID of the virtual processor and the PEID of the physical processor PE2 assigned to the virtual processor (this assignment is also described in <3b. Generation of Virtual Processor> below). A storage area (table) that can be associated and stored is prepared. This table is called a processor element TLB (PETLB).

FIG. 2 conceptually shows an example of the PETLB. The PETLB has a plurality of entries as shown in FIG. A, and each entry (except for the system entry 8 at the top of the figure) is divided into several fields as shown in FIG.

Of these fields, the Valid field 4 is a field for indicating that valid data exists in the entry, and the Lock field 5 is prohibited from changing the contents of the entry. This is a field for indicating that The VEID field 6 and the PEID field 7 of the same entry store the VEID of the virtual processor and the PEID of the physical processor PE2 assigned to the virtual processor, respectively.

The content stored in each entry is a “processor element management table” managed by the OS in the system memory SM (FIG. 1) (that is, a virtual processor that defines the correspondence between a virtual processor and a physical processor). A copy of a part of the list. PETLB
Is a kind of associative storage device, and when a VEID is given, the PEID of the physical processor PE2 assigned to the virtual processor of the VEID can be extracted.

The system entry 8 is a special entry for managing allocation information of the physical processor PE2 to a system processor described later.

Such a structure of the PETLB is similar to a table used in a general microprocessor virtual memory system.

<1b. System Processor> The “system processor” is one of the virtual processors, and is a special virtual processor for processing errors and events relating to the entire system. Interrupts from outside the system, errors related to the management of the virtual processor, and the like are handled as errors generated in the system processor.

Initialization of entries for general virtual processors other than the system processor must normally be performed by software in a processor element management table in the system memory SM, but only the system processor will be described later. <3a. As described in <System Initialization>, when the system is reset, hardware initializes the system entry 8 in PETLB.

Entries other than the PETLB system entry 8 are described in <2. Access to virtual processor >>, as described in the above, may be replaced with other entries in the processor element management table.
Only system entry 8 is in a location protected from this swap. In other words, the physical processor PE2 is always assigned only to the system processor, and the physical processor PE2 is assigned from the system entry 8.
Can be searched. However, which physical processor PE2 is assigned to the system processor can be changed at any time by rewriting the system entry 8 itself.

<< 2. Access to virtual processor >> When the application software accesses a processor in the system (for example, a process is input to a processor different from the processor currently executing the process,
In a case where communication is performed with a processor different from the processor currently executing the process, for example), the virtual processor is accessed using the VEID. In other words, in application software,
VEID is used to describe a program on the assumption that a virtual processor is used.

When an access to such another virtual processor occurs in the processor currently executing the current process (that is, the physical processor PE2 (FIG. 1) assigned to the currently executing virtual processor), the access is made to the virtual processor. It is notified on the communication bus 3 (FIG. 1) as a processor call event. At this time, the VEID of the accessed virtual processor is also put on the bus 3 at the same time.

Each physical processor PE2 stores "VEID" for storing the VEID of the virtual processor being executed.
An ID register is provided, and by referring to this register, it is possible to determine which virtual processor is currently assigned. Physical processor PE2
Responds directly to the access when the VEID put on the bus 3 matches the VEID of the currently assigned virtual processor (that is, when it is the called virtual processor).

On the other hand, PMU1 (FIG. 1)
The V sent from each entry of FIG.
Search the VEID field 6 storing the EID,
The PEID of the physical processor PE2 assigned to the virtual processor is obtained from the PEID field 7 in the same entry as the VEID field. When none of the physical processors PE2 responds directly to the access, an interrupt request for replacing the virtual processor is generated to the physical processor PE2 having the obtained PEID.

In the physical processor PE2 assigned to the called virtual processor, this interrupt causes
The rewriting of the VEID in the VEID register and the replacement of the process by an exception handler (a program describing exception processing) are performed.

When the PMU 1 searches each entry of the PETLB and finds no VEID field 6 storing the VEID sent via the bus 3, an exception is given to the above-mentioned system processor. Occur.
In this case, the OS uses PETLB by the exception handler.
Are replaced, and then the virtual processor is called again.

<< 3. Example of virtual processor management in cooperation with software><3a. System Initialization> When the system is reset, each physical processor PE2 is initialized and enters a standby state. In PETLB (FIG. 2), the system entry 8 is initialized, and all other entries are invalidated.

When all initialization processing is completed, the PMU
1 (FIG. 1) calls the system processor. This call is << 2. Access to Virtual Processor >> by the interrupt request to the physical processor PE2.

In the activated system processor, the OS
Of the kernel (nucleus) is started, and the system memory S
Initialization of the processor element management table in M (FIG. 1) is performed.

<3b. Create virtual processor>
Other parts of the OS and application software are activated, and each process is assigned to a new virtual processor. This process is performed by the process calling a “virtual processor generation task”, which is a program prepared by the OS, by a system call or the like.

The called virtual processor creation task sends a VEI to the virtual processor to which the process is assigned.
D, and assigns the physical processor PE2 to the virtual processor.
(FIG. 1). And the VEID and PEI
D and information necessary for executing the process are stored in a processor element management table in the system memory SM (FIG. 1). In this way, a virtual processor is generated.

The OS determines which physical processor PE2 is to be assigned to a newly created virtual processor based on the usage status of each physical processor PE2.
Within the range that can be represented by VEID, it is also possible to generate a larger number of virtual processors than the number of physical processors PE2 mounted on the system. In this case, the same physical processor PE2 is assigned to a plurality of virtual processors. To share.

<3c. Execution of virtual processor> The newly generated virtual processor is actually replaced with the physical processor PE2.
The processing executed above is performed independently and in parallel with the virtual processor generation processing.

To this end, an external interrupt such as a timer interrupt is periodically applied to the system. This mechanism is the same as that for making a single processor perform multitasking by time division.

Since the timer interrupt is an event relating to the entire system, when it occurs, the PMU1 automatically calls the system processor by an interrupt request to the physical processor PE2. From an interrupt handler, which is a program describing this interrupt processing, the OS
A "virtual processor management task", which is a program prepared by the above, is called.

The called virtual processor management task assigns a virtual processor that allocates and executes the physical processor PE2 for a certain period of time until the next timer interrupt from the processor element management table in the system memory SM, and sets the priority order among the processes. Decide based on The virtual processor determined in this way is << 2. Access to Virtual Processor >> As described above, execution by the virtual processor is started.

As described above, according to this multiprocessor system, the physical processor PE2 can be accessed at the application software level by a program described in a form not specialized for the hardware configuration of the physical processor PE2. Become like

Further, by assigning processes to a larger number of virtual processors than the number of physical processors PE2 installed in the system, the number of processors larger than the number of physical processors PE2 is limited within the range expressible by VEID. You can also write programs that assume the use of.

In the above embodiment, the main memory (system memory SM) is connected to a single bus (communication / memory).
Although the present invention is applied to a shared memory type (tightly-coupled type) multiprocessor of a single bus system which is shared by the processors (PE2) via the bus 3), other systems (for example, a multi-bus system, a hierarchical bus) The present invention may be applied to a shared memory type multiprocessor of a type, a multiport memory type, or the like, or a message exchange type (loosely coupled type) multiprocessor.

The present invention is not limited to the above embodiment,
It goes without saying that various other configurations can be adopted without departing from the gist of the present invention.

[0045]

As described above, according to the multiprocessor system of the present invention, the processor is accessed at the level of the application software by the program described in a form not specialized for the processor having the specific hardware configuration. be able to. This eliminates the need to rewrite the application software program even when the hardware configuration of the processor in the system is changed, thereby saving time, labor, and cost.

Further, since it is possible to describe a program on the assumption that a larger number of processors than the number of processors mounted on the system are used, it is possible to reduce restrictions on creating application software.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of a configuration of a multiprocessor system according to the present invention.

FIG. 2 is a diagram illustrating an example of a processor element table.

[Explanation of symbols]

1. Processor management unit 2a,
2b, 2c, 2d: processor element, 3: communication bus, SM: system memory, 4
... Valid field, 5 ... Lock field,
6 VEID field 7 PEID field 8 System entry

Claims (1)

[Claims] 1. means for assigning a process to be executed in a system to a virtual processor; means for assigning a processor implemented in the system to the virtual processor; and means assigned to the virtual processor and the processor. Means for associating the mounted processor with the mounted processor; and in response to any one of the virtual processors being called, the virtual processor stores the virtual processor with the mounted processor stored in association with the processor. Means for executing a processor.