JPH1032785A - Memory multiplexing system for highly precise video decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce an area on an integrated circuit used for transferring data by permitting a latch multiplexer to convert a high pass band data stream into plural low pass data streams. SOLUTION: Memories 204 and 206 integrate buffering memories used by various processing units in a decoder, in a single position. Data from the RAC input memory 204 are given to a latch multiplexers 210, 214 and 216. Data are given to the RAC output memory 206 through a RAC output memory interface 224. The latch multiplexers 210, 214 and 216 sequentially operate so that data are more frequently loaded on the latch multiplexer operating as a high pass band data channel than on the latch multiplexer operating as a low band data channel. Thus, the constitution of a whole circuit becomes economic.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates to the management of high bandwidth memory in video decoders, and in particular, significantly reduces the area on an integrated circuit used to transfer data between a decoding processor and the high bandwidth memory. And a memory data multiplexing system.

[0002]

BACKGROUND OF THE INVENTION In the United States, certain standards have been proposed for digitally encoded high definition television (HDTV) signals. This standard is the MPEG-2 standard proposed by the Moving Picture Experts Group (MPEG) of the International Standards Organization (ISO).
It is essentially the same as the standard. This standard is described in "Information Technology-Generating and Coding of Moving Pictures and Associated Audio, Recommendation H.626" (ISO / IEC 13818-2, IS,
(November 1994). This publication is available from ISO,
This specification is also incorporated by reference for its teachings regarding the MPEG-2 Digital Video Coding Standard.

[0003] Television signals encoded according to the proposed HDTV standard are transmitted using RF signals that fit within the 6 MHz bandwidth of conventional television channels. However, video images encoded according to this standard can have very high data rates, carrying as many as 94 million pixels per second. Due to the relatively narrow bandwidth of the transmission channel and the relatively high data rate of the reproduced image, the transmitted signal will undergo significant compression. Therefore, the received signal undergoes enormous processing in order to recover a video signal having a high data rate from the compressed transmission data. The format for compressed data and uncompressed data, and each processing step used for decompressing data, are all defined by the above-mentioned MPEG standard.

An earlier patent application entitled "MPEG Video Decoder with High Bandwidth Memory" (08 / 330,5)
No. 79), an input bit stream, a reference image used for motion compensation processing, and an image to be displayed in a separate memory from a processing circuit for decoding the input bit stream. , It is desirable to store. However, it is desirable for the memory to have a relatively high bandwidth in order to process all requests from each part of the decoder quickly enough to be able to generate decoded images in real time.

A system using high bandwidth memory is disclosed in the above-cited US patent application. This type of system is shown in FIG. This system has three main components. That is, a processor 110 including all the circuits necessary for decoding a video signal encoded by MPEG, initialization of the integrated circuit 110,
A control microprocessor 114 used for setting the operation mode of the decoder and the MPEG bit stream as received, a reference image used for motion compensated decoding,
And a central memory 112 for holding images to be displayed;
The three. The memory 112 used in the system shown in FIG. 1 and also used in the embodiment of the present invention is an NEC 112
And a RAMBUS memory system available from Toshiba. This memory system is described in a specification entitled "RDRAM Reference Manual", which is incorporated herein by reference. The system, taken as an example, has three 32-megabit arrays each
Each array supplies 64 bits of data words using a 96 megabit memory arrangement.

[0006] Briefly, the system shown in FIG. 1 operates as follows. The bit stream encoded by MPEG-2 is provided to the router 122,
2 divides this bitstream into two parts.
These parts are processed by variable length decoders 128 and 132, respectively. This bit stream is stored in the buffer memory 124 as received. Thus, when a sufficient number of bits have been stored, this bit stream is stored in a RAMBUS ASIC cell (R
AC) is transferred to the memory 112 via the interface 118 and the RAC 116. As shown in FIG.
The input to the C interface circuit 118 is a bus having a bit width of 192 bits.

Further, data is stored in RAC 116 and RA
The data is retrieved from the memory 112 via the C interface 118 and supplied to the VLD processors 128 and 132, the half-pixel interpolation circuit 144, and the display memory 148, respectively. In the system example shown in FIG.
Are transferred in the circuit 110 using a 192-bit bus.

Each of the sub-processors includes a buffer memory because various processors cannot process data provided by the 192 bit bus at the rate at which it was received. For example, V
One example is memories 130 and 126 connected to LD processors 132 and 128, respectively.
Each of these memories has dedicated address decoding logic. These memories are also connected so that they can receive data from the 192-bit bus and supply the data to each sub-processor when necessary.

In the example of the system shown in FIG.
Are transferred to the memories 126 and 130. The transferred data is extracted from these memories by each VLD processor 128 and 132. Each VLD processor converts variable-length coded data into fixed-length coded data. The converted data is supplied to the inverse quantization and inverse discrete cosine transform processing circuit 134. Data is transferred from VLDs 128 and 132 to processor 134 via first-in-first-out memories (FIFOs) 129 and 133, respectively.

The data provided by the processor 134 is in the form of a macroblock consisting of pixel data or difference pixel data. This data is stored in the processor 13
4 to the FIFO memories 133 and 135, and the adder 136 is controlled under the control of the half-pixel interpolation circuit 144.
And 138 respectively.

Circuit 144 controls the processing of data received from processor 134 via two paths.
This circuit allows the data representing the pixel value to pass through unaltered, and the data representing the difference pixel value to:
Combine with pixel data obtained from reference memory data. This reference memory data is provided to the circuit 144 via the plurality of memories 146. As shown in FIG. 1, each of the plurality of memories 146 receives data from the memory 112 via the RAC interface circuit 118. Next, this data is supplied from the memory 146 to the half-pixel interpolation circuit 144 via the 8-bit bus.

The circuit 144 generates reference blocks consisting of a plurality of pixels from the data provided by the memory 146, and combines these reference blocks with each block provided by the circuit 134 via FIFOs 133 and 135. . In addition and clipping circuits 136 and 138, reference data is added one pixel at a time to the data provided by processor 134. The output pixel values provided by these circuits 136 and 138 are provided to memories 140 and 142, respectively. Each of these memories receives pixel values 8 bits at a time and outputs 192 bits of data at a time by integrating these values.
The data is stored in the memory 112 via the AC interface 118.

The data provided by memories 140 and 142 represent the decoded image data. This data is stored in the memory 112 and the half-pixel interpolation circuit 144
Used as reference image data for display or provided to the memory 148 for display.

In the circuit described above, data from the high bandwidth memory 112 is transferred to each component of the processor 110 using a wide (ie, 192 bit) bus, which also provides access to the RAC interface circuit 11.
8 and each of a plurality of memories formed around the circuit. Such a configuration has a problem that if a 192-bit bus is provided as a path in a circuit, a relatively large area on a chip is required.

[0015]

SUMMARY OF THE INVENTION The present invention is a video decoder in which a high bandwidth memory is connected to a plurality of latch multiplexers, each of which converts a high bandwidth data stream into a plurality of low bandwidth data streams. It is realized in the form of a video decoder. Each of these latch multiplexers receives a relatively large amount of data from a high-bandwidth memory and orders the data held by the latch to provide a decoder through a plurality of relatively low-bandwidth data paths. And a multiplexer for supplying the data to various sub-processing units. This multiplexing operation is performed while the high-bandwidth memory supplies data to the other plurality of latch multiplexer circuits. These latch multiplexers operate sequentially so that the latch multiplexer acting as a high bandwidth data channel is loaded more frequently than the latch multiplexer acting as a low bandwidth data channel.

[0016]

DETAILED DESCRIPTION The circuit shown in FIG. 2 operates as follows. The data held in the central memory 112 is RA
MBUS ASIC Cell (RAC) 116 and RAC
RAC input memory 204 via interface 118
From the RAC output memory 206 to the memory 112
To the RAC interface 118 and RAC1
16. RAC interface 11
8, the configuration and function of the RAC 116 and the central memory 112 are described in the aforementioned patent application Ser. No. 08 / 330,579. In the following description, data transfer between the RAC interface 118 and the memory 112 operates as described in the above-referenced patent application and will not be described in detail.

[0017] Memories 204 and 206 consolidate the buffering memory used by the various processing units in the decoder into a single location. This memory makes it possible to use a less distributed memory around the integrated circuit, thus making the overall circuit configuration more economical. Also, by integrating the 192-bit bus into the input port of the latch multiplexer, the portion of the integrated circuit used by the bus is reduced.

The data from the RAC input memory 204 is
Latch multiplexers 210, 214 and 216. The data is stored in the RAC output memory 206 as RA
It is provided via a C output memory interface 224. Data is transferred between the RAMBUS memory 112 and the RAC interface 118 under the control of the DRAM control circuit 120 '. Latch multiplexer 21
Each of 0, 214 and 216 converts a 192-bit parallel data stream into a smaller data stream. For example, the latch multiplexer 210a,
210b and 210c each convert a 192-bit data stream into a 32-bit data stream for one of VLD processors 134, 132 and 130, respectively. Data transfer between the RAC input memory 204 and the latch multiplexers 210, 214 and 216 and between the RAC output memory interface 224 and the RAC output memory 206 is controlled by a latch multiplexer control circuit 212. For clarity, the connections between circuit 212, latch multiplexers 210, 214 and 216, and RAC output memory interface 224 are not shown in FIG.

In the system shown in FIG.
-2 encoded bit stream is a PES (Program Elementary Stream) packet.
It is provided to a parser 220. Decomposer 220
Extracts the bit stream data from the PES packet and provides it to the RAC output memory interface 224. The RAC output memory interface 224 is described below with reference to FIG. The PES decomposer 220 also extracts timing information from the PES packet, and extracts this information from the clock recovery and timing circuit 22.
Give to 2. This circuit may include, for example, a digital phase locked loop (not shown) that generates all of the internal clock signals used by the circuit shown in FIG.

The bit stream data is supplied to the RAC output memory 2 by the RAC output memory interface 224.
06 is written. The circuit shown in FIG.
Using a processor, the bitstream is divided into three partitions. One of these partitions contains only high-level structures such as sequence headers, group of picture headers, and picture headers. The other two partitions contain slice records. MPEG-2
The alternating slice records of the bitstream coded in are alternately placed in each of the other two partitions.

When the bit stream data is read from these three partitions, the bit stream data is read from the respective latch multiplexers 210a, 21a.
0b and 210c. Latch multiplexer 210a provides data from the first partition to high-level processing VLD processor 134, while latch multiplexers 210b and 210c provide data from the second and third partitions to respective slice and low-level VLD decoders 132 and 130 respectively. VLD processors 130, 132 and 134 convert the variable length coded bit stream to a fixed length code, which is then provided to an inverse quantization and IDCT processor 134 '. Processor 134 'has the same functions as processor 134 described above with reference to FIG.

The data provided by the processor 134 'takes the form of blocks of pixel data or differential pixel data. The difference pixel data is added to the addition circuit 13
6 and 138, where the data is
It is combined with the corresponding pixel data from the reference image provided by the half-pixel interpolation circuit 144. This circuit is
It may be the same as the circuit 144 described above with reference to FIG.

The circuit 144 converts the reference image pixel data into RA
C input memory 204 and latch multiplexer 214
Receive from Latch multiplexers 214a, 214
Each of b, 214c and 214d receives 192 bits of reference image data at a time and supplies this data to the circuit 144 only 8 bits at a time.

The adder circuits 136 and 138 output the decoded pixel data to the RAC output memory interface 22.
4, the interface 224 stores the decoded image data in the RAC output memory 206. The decoded image data is used as a reference image for decoding the motion compensated difference pixel value and a reference image for an output image to be displayed.

Data for the display image is provided to the latch multiplexer 216 from the RAC input memory. Latch multiplexers 216Y, 216U and 216V
Receives 192 bits of data at a time, and provides signals of different components of the image (ie, Y, U and V) to the display processor 218 as an 8-bit data stream. The processor 218 has Y,
The U and V signals are provided to a display device (not shown) to reproduce the decoded image.

FIG. 3 is a block diagram showing the decoder part of FIG. 2 in more detail. Although the latch multiplexers 210, 214 and 216 are shown in FIG. 2 as being distributed around the perimeter of the system, these devices are adjacent in an embodiment of the present invention as shown in FIG. doing. This implementation is advantageous because it reduces the length of the 192-bit bus and consequently the area occupied by the bus on the integrated circuit.

As shown in FIG. 3, the RAC input memory 20
4 is made up of six 32-bit, 320-word memories. RAC input address and control logic 121
Supplies 20 bits of control data to the memory 204.
The control data includes nine write address bits and nine read address bits applied to all six memories in parallel, a clock signal, and a write enable signal. The memory 204 is connected to a 192-bit system bus for receiving data from the RAC interface 118. The address and control logic 121 also uses a 29-bit bi-directional bus to communicate with the RAC interface 118. This bus allows the circuit 121 to perform a memory read operation
It is bi-directional to allow it to be performed equally with the C interface 118. RAC interface 118
Sends data to circuit 121 and memory 204 to indicate the type of data provided. Circuit 121 sends data about the status of memory 204 to RAC interface 118. Circuit 121 also keeps track of which memory locations in memory 204 are available to hold data and which memory locations have data to be provided to the latch multiplexer circuit.

Data provided by RAC input memory 204 is routed to one of seven 192-bit latches 309a-309g in latch bank 1. Latches 309a-309g are connected to receive data provided by memory 204 via a common 192-bit bus. Each latch is enabled to store data appearing on the bus in response to a respective enable signal provided by the VLD, reference and display multiplexer control and latch gate logic circuit 314. Logic circuit 314 provides seven enable signals, one of them.
Each one corresponds to one of the latches 309a-309g.

In response to one of these enable signals, a corresponding one of latches 309a-309g is
One is being transferred over the bus BI at that time.
Stores 2-bit data. As will be described later, the data is transferred from the memory 204 to the latch multiplexers 210 and 2.
14 and 216 are transferred at a rate that varies depending on how the data is used by the decoder.

The latches 309a, 3a in the latch bank 1
09b, 309c, 309e, 309f and 309g
Is stored in the corresponding latch 31 of the latch bank 2.
0a, 310b, 310c, 310h, 310i and 310j. However, the data in the latch 309d is stored in the four latches 310d and 31 in the latch bank 2.
0e, 310f and 310g. To reduce the amount of circuitry used by Latch Bank 1, Latch 309d in Bank 1 is configured to function for the four latches in Bank 2. This is possible in part because the rate at which the reference image data is provided is lower than the rate at which the bitstream data is provided to the VLD processor.

Latches 310a to 310j store 192 bits of data in latch multiplexers 312a to 312a, respectively.
312j. The multiplexer selects such that the portion of data provided by the latch is provided to a respective processing circuit in the MPEG-2 decoder circuit shown in FIG. For example, the multiplexer 312a divides the 192-bit data held by the latch 310a into a plurality of 32-bit segments. These segments are provided to the VLD level processing circuit 134 shown in FIG. Multiplexer 312a,
312b and 312c, respectively, are latches 310
a, 310b and 310c to access the 192 bits of data held by the corresponding one of them and convert the 32 bits of data to VLD processors 134, 132 and 1
Give to the corresponding one of the 30.

Each of the multiplexers 312d to 312j corresponds to one of the latches 310d to 310j.
192 bits of data held by the decoder are accessed, the data is divided into a plurality of 8-bit segments, and 8-bit data is provided to each element of the decoder shown in FIG. 2 at a time. Multiplexers 312d to 312g
Supplies the reference image data to the half-pixel interpolation circuit 144, and the multiplexers 312h to 312j supply the data to the display processor 218. The logic circuit 314 converts the control data of 44 bits into the multiplexer 3
12a to 312j to control their operation.
This control data is supplied to the multiplexers 312a to 312c.
, And five select bits for each of the multiplexers 312d-312j. The logic circuit 314 is connected to a 37-bit control bus for exchanging control signals with the RAC input address and control logic 121.

Although the number of latches in Bank 1 and Bank 2 are different, the two banks of latches use a double buffering scheme. Using this method, a particular type of data from memory 204 may be in transit from one of multiplexers 312 while a particular type of data is being transferred from a latch in bank 2 to an appropriate processing circuit. The appropriate latch in bank 1 can be made available to receive the data.

FIGS. 4A and 4B show the structures of two types of multiplexers used in the circuit shown in FIG. FIG.
(A) shows an example of a 192-bit to 32-bit multiplexer suitable for use as one of the multiplexers 312a to 312c. FIG. 4B shows an example of a 192-bit to 8-bit multiplexer suitable for use as one of the multiplexers 312d to 312j.

The multiplexer 312a shown in FIG.
Includes a 6 to 1 multiplexer 410;
The multiplexer 410 receives a 3-bit control signal from the logic circuit 314 (shown in FIG. 3) and, based on the value of the control signal, converts the 192-bit word held in a corresponding one of the registers 310a-310c. 6
Gives one of the 32 bit segments.

The multiplexer 312d shown in FIG.
Operate in substantially the same manner, but with multiplexer 42
0 is a multiplexer from 24 to 1, which is 19
The difference is that a 2-bit input value is output as one of 24 8-bit values in response to a 5-bit control signal from the logic circuit 314.

As described above, the 32-bit value output by the multiplexer 312a is output to the high-level processing VL.
This is bit stream data encoded by MPEG-2 and provided to the D processor 134. The 8-bit value output by the multiplexer 312d is a reference pixel data value provided to the half-pixel interpolation circuit 144.

FIG. 5 is a block diagram of a circuit suitable for use as the RAC output memory interface 224 shown in FIG. This circuit receives from a transport decoder (not shown) an 8-bit value representing successive bytes of the MPEG-2 transport stream. These values are decoded by the PES packet decomposer 220 into a continuous program elementary stream (PE
S) Construct a packet. The output signal provided by the decomposer 220 is a bit-serial MPEG-2 encoded bit stream. This bit stream is provided to a bit stream processor 510,
The bitstream processor 510 collects a bitstream of a plurality of segments of 32 bits each and multiplexes the segments from a 2 to 1 multiplexer 514.
And then to register 515. Here, the registers are connected to provide a 32-bit value to the RAC output memory 206. Multiplexer 514, register 515, and memory 206 are controlled by RAC output address and control logic 122.

Multiplexer 514 also receives input data from macroblock processor 512.
Processor 512 receives the two 8-bit values provided by adders 136 and 138 shown in FIG. 2 and combines successive pixel values from each adder into a 32-bit word, which is converted to a 32-bit word. And then to register 5
Give to 15.

A multiplexer 514, a register 515,
The combination of memory 206 and control logic 122 results in a data formatter that combines the 32-bit data values provided by processors 510 and 512 into 192-bit words each held in memory 206.

In the embodiment of the present invention, the processor 51
0 and 512 buffer several 32-bit words provided sequentially by multiplexer 514 and register 512, and
Includes internal registers (not shown) located in contiguous 32-bit memory locations within a 2-bit word. Thus, one 192 bit word in memory 206 contains all the bit stream data, while another 19 bit word contains another 19 bit word.
The two-bit word contains all the decoded pixel data.

Alternatively, memory 206 may be controlled to selectively provide the 32-bit data value held in register 515 to a 32-bit subword of memory 206, as described below. Using this scheme, the processor 5 used to buffer the data
The memory in 10 and 512 can be omitted. Each of processors 510 and 512 has 32
While the bit value is created, this is
At 14, control logic 122 consistently formats the 192-bit word by allocating the 32-bit value to the appropriate subword of memory 206.

The register 515 stores 3 bits from the input bit stream or from the macroblock processor 512.
Stores a 2-bit word. This value represents 32 bits of bit stream data or 32 bits of pixel data. Register 515 provides a 32-bit value to RAC output memory 206. Memory 206 includes six 32-bit, 36-word memories that are used to buffer the data provided by registers 515 until provided to RAC interface 118 shown in FIG. All six memories receive the same address value, but each memory receives a separate write enable (WE) signal.
Thus, the 32-bit value provided by register 515 provides which of the plurality of memories 206 by providing the desired address value to all of the memories and then activating the WE signal only to the selected memory. Segments (subwords) can also be written.

RAC output memory interface circuit 22
4 is a system in which 5-bit control information is transmitted to the RAC interface 11
Receive from 8. This control information specifies what type of data, ie, a bit stream or a macroblock, will be stored in register 515, and the 192 bit value is stored in memory 206 from RA.
Identify when to transfer to C interface 118. This control signal is provided to the RAC output control and logic circuit 122 which generates appropriate control signals for the other circuits shown in FIG. These signals include a 19-bit control signal for the memory 206 (6 read address bits, 6 write address bits, 1 bit clock signal and 6 WE signals). Logic circuit 122 also generates two control bits, one bit for multiplexer 514 and one bit for register 515. These control signals allow either the decoded pixel data or the bitstream data to be written to the appropriate addresses in the appropriate memory 206. Further, the circuit 122 includes 4
A bit control value is provided to the bit stream processor 510 and a 4-bit control signal is provided to the macroblock processor 512. The circuit 122 also receives two handshake signals, one each from the bitstream processor and the decoded macroblock processor. These signals indicate that each processor has data to transfer to register 515 through multiplexer 514.

The 4-bit signal provided to processor 510 allows the processor to collect four 8-bit segments of the input bitstream into a single 32-bit value. The processor 510 includes the PES decomposer 2
20 includes an internal shift register (not shown) that holds successive 8-bit segments of the input bit stream provided by 20. The 4-bit control signal for macroblock processor 512 selects three bits that specify which part of the internal shift register will provide data to multiplexer 525 and register 515, and the decoded macroblock. One bit to be included.

The above system converts a 192 bit value to RA
The data is transferred from the C input memory 204 to the various latch multiplexer circuits 210, 214 and 216 and received at the RAC output memory 206 from the RAC output memory interface 224. The data provided by the latch multiplexer is a smaller data word (ie, an 8-bit or 32-bit value)
The data provided to the various processing elements and received from the RAC output memory interface is generated as an 8-bit value representing an input bitstream or a processed image. These 8-bit values are put together and provided to the RAC output memory 206 as 32-bit values. This configuration allows for predicting and achieving the maximum rate at which data can be given to various processes,
This is an effective configuration when used for an MPEG-2 decoder.

The following table is an example of a worst-case schedule for reading data from memory 204 that enables the decoder shown in FIG. 2 to decode MPEG-2 images in the main profile high-level format. Is shown. Each number in Tables 1 and 3 is
4 to latches 309a to 309c and 309e to 30
It represents a single system clock cycle in which 192 bits of data are transferred to one of the 9g, indicated by the first column of the table. The numbers in Table 2 further represent the clock pulses at which the type of data in the first column is to be transferred to the latch 309d for transfer to the latches in Latch Bank 2, where four pulses are transferred. Indicated by column headings.

[0048]

[Table 1]

[0049]

[Table 2]

[0050]

[Table 3]

Although these tables appear to show a fixed schedule, there is no fixed time for accessing any particular type of data from memory 204. Control logic 314 and RAC input control logic 121 instead monitor the status of the latches in latch bank 1 to ensure that these latches remain full. Thus, as soon as one of these latches transfers its contents to latch bank 2, control logic 121 and 314 will attempt to fill the emptied latches with data from memory 204. Memory 20
When the data is transferred from No. 4 to the latches 309a to 309g, the display data has the highest priority, and thereafter, the reference data and the VLD data are in this order.

The order shown in the table represents the worst case timing when the decoder shown in FIG. 2 decodes the MPEG-2 image encoded according to the main profile high level format. Typically, most of the memory read operations that send data to the VLD processor send the data to the slice and low-level processors 130 and 132. V listed in the table
In the LD operation, data is transferred to three processors 1 as needed.
To one of 30, 132 and 134.

Since memory 206 is separate and independent of memory 204, data is written to RAC output memory 206 regardless of how and when data is read from RAC input memory 204. . The memories 204 and 206 and the system memory 11
2 is transferred to the RAC interface 118.
Is controlled by This interface is described in the above referenced US patent application.

When a particular bitstream is decoded, not all read and write operations are performed at the indicated timing. If a read operation is not needed because the processor does not need the data, and if a write operation is not needed because the data is not available for writing, it is simply skipped. Thus, the timing shown in the table represents a time slot available for a particular operation in the worst case timing state.

Although the invention has been described by way of example, it will be understood that it can be practiced as described above within the spirit and scope of the appended claims.

[Brief description of the drawings]

FIG. 1 (Prior Art) is a block diagram illustrating an example of a high definition video decoder using a high bandwidth memory.

FIG. 2 is a block diagram of a high bandwidth video decoder including an embodiment of the present invention.

FIG. 3 is a block diagram of a RAC input memory and a latch multiplexer of the circuit shown in FIG. 2;

FIGS. 4A and 4B are block diagrams illustrating a structure of a multiplexer among the plurality of multiplexers illustrated in FIG. 3;

FIG. 5 is a block diagram illustrating a structure of a RAC output memory interface shown in FIG. 2;

Claims (7)

[Claims] 1. A high-bandwidth memory system comprising: a memory for holding data as a data value of M bits (where M is an integer); and a plurality of latch multiplexers. A latch for receiving the M-bit data value provided by the central memory; and ordering the M-bit data value held by the latch so that at least N bits (where N
And a multiplexer that provides data at a time to an output port, the plurality of latch multiplexers comprising a plurality of first latch multiplexers acting as relatively low bandwidth channels; A plurality of secondary channels acting as relatively high-bandwidth channels
And a latch multiplexer.
A high bandwidth memory system, wherein the latch multiplexer is configured to be loaded with data from the memory more frequently than the plurality of first latch multiplexers. 2. M can be divisible by N, and the plurality of second latch multiplexers order at least P bits (where: M) by reordering the M bits of data values held by respective latches. P is an integer less than M and greater than N) at one time to each output port, wherein the memory and the plurality of first latch multiplexers and the plurality of A two-latch multiplexer, whereby the central memory stores the plurality of first latches.
And a second latch multiplexer for sequentially providing data at a predetermined rate, respectively, wherein the rate of data supplied to one of the plurality of second latch multiplexers is equal to the plurality of second latch multiplexers. 2. The high bandwidth memory system according to claim 1, further comprising an ordering means for increasing a rate of data provided to any one of the one-latch multiplexers. 3. Combining a terminal receiving a data value of R bits (where R is an integer less than M and M is divisible by R) with a sequence of the received R bit values Formatting means for converting the M-bit value generated by the formatting means into an M-bit value, and another latch for providing the stored M-bit value to another memory; and holding by the other latch Means for storing the M-bit value in the separate memory, wherein the ordering means is provided by the separate latch when provided by the combining means. 3. The high-bandwidth memory system according to claim 2, further comprising means for storing said data in said another memory. 4. The memory is a first buffer memory connected to the central memory, thereby holding a continuous M-bit value provided by the central memory, and the retained M-bit value. The plurality of first and second
A high bandwidth memory system for providing to a latch multiplexer, wherein said ordering means is connected to said first buffer memory, whereby said M bit value is consumed by each of said low bandwidth channel and said high bandwidth channel. 4. The high bandwidth of claim 3, wherein the respective rates at which the M-bit values are provided to the plurality of first and second latch multiplexers can be dynamically varied depending on the respective rates at which they are performed. Memory system. 5. Each of the data is M bits (where M
Is an integer), and is connected to receive the M-bit data value from the first memory and store the M-bit data value. An output latch connected to the output latch to provide predetermined data in the M-bit data value as a sequence of N-bit (where N is an integer less than M) data values; And output multiplexing means connected to the output latch to provide predetermined data in the M-bit data value as a sequence of P-bit (where P is an integer less than M) data values. A second output multiplexing means for receiving a data value of Q bits and a data value of R bits (where Q and R are integers less than M), respectively. Input format means connected to the control signal to selectively combine some of the Q-bit data values to generate the M-bit data value or to generate the R-bit data value. Input format means for selectively combining some of the values to generate the M-bit data value; and memory control means connected to the first memory, wherein the M-bit data value is the M-bit data value. 1 and the M generated by the input format means.
A memory control unit for storing a bit data value in the second memory; a memory control unit; a first and a second output multiplexing unit; and a control unit connected to the input format unit. Generating a control signal to cause the central memory to fetch or store the M-bit value, cause the first memory to receive the fetched data value, and store the M-bit value in the second memory. Control means for giving the data value. 6. The first memory is a buffer memory connected to the central memory, thereby receiving a continuous M-bit value provided by the central memory and holding the retained M-bit value. To the output latch, wherein the memory control means comprises a first memory and a second memory.
And the first and second memories
The M-bit value is stored in the first memory by the first memory in accordance with the respective rates at which the output multiplexing means provides the N-bit data value and the P-bit data value, respectively. 6. The memory system according to claim 5, wherein said control means generates a control signal capable of dynamically changing respective rates when applied to the cusing means. 7. A memory system connected to receive an encoded video image and suitable for use in a digital video decoder including a variable length decoder and a display device, comprising: Bit, where P is an integer, and is connected to receive the M-bit data value by combining several consecutive ones of the received P-bit data values. A formatter (where M is an integer greater than P) comprising: a memory means having M-bit data values addressed in a P-bit segment; A control means for selectively storing, in response to the signal, the received P-bit value in a segment selected from the P-bit segments. ,
And an R bit representing the encoded video image (where R
Is an integer less than P).
First output means for combining the R-bit data value into the P-bit data value provided to the formatter and providing the P-bit data value to the formatter; Receiving a data value of Q bits (where Q is an integer) that represents a different P-bit data value by combining some of the Q-bit data values and generating another P-bit data value; Second output means for providing a bit data value to the formatter; control signal generating means connected to the first and second output means and the formatter means; By generating the first
Of the P-bit data values provided by the output means of the M-bit data value into each of the consecutive P-bit segments corresponding to a data value in the M-bit data value. The control means is adapted to store, and the consecutive number of the P-bit data values provided by the second output means are stored in different ones of the M-bit data values. A control signal generating means for causing said control means to store in each of the successive P-bit segments corresponding to said value.