JPH10327202A - Input device for digital data outputted from digital broadcast receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To receive correctly a digital data output outputted from a digital broadcast receiver even when a transmission cable is long. SOLUTION: A data signal and a clock signal outputted from a tuner 10 are sent to an interface board 28 of a personal computer 12 via a cable 56. The transmitted clock signal is smoothed by a low pass filter 60. Comparators 62, 66 use an output of the low pass filter 60 for a reference voltage and compare the clock signal and the data signal in terms of voltages and shape the wave form.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input device for digital data output from a digital broadcast receiver, and to an apparatus for receiving digital data correctly.

[0002]

2. Description of the Related Art A receiver (tuner) for digital satellite broadcasting is provided with a connector for outputting data for one transponder in accordance with the specifications of the Association of Radio Industries and Businesses (ARIB standard). Broadcast and EP
Digital data output such as G (Electronic Program Guide) information can be taken into a personal computer or the like.
The output of digital data output from this connector (hereinafter referred to as “high-speed digital output”) is to reduce the power consumption of the digital satellite broadcast receiver (exactly, the holding time of the power supply voltage after the power is turned off). In order to reduce the unnecessary radiation, a normal TTL output having a weak output power is used.

[0003]

Since the high-speed digital output of the digital satellite broadcast receiver is a normal TTL output having a low output power as described above, the digital satellite broadcast receiver and the high-speed digital output If the cable connecting an input device such as a personal computer (hereinafter referred to as a "high-speed digital input device") for inputting the data is long, the following two problems occur.

(1) High-speed digital output is simply TTL
When received at the input, the input impedance of the TTL is too large compared to the characteristic impedance of the cable, signal reflection occurs, and the reflected wave propagates to the high-speed digital output terminal of the receiver. Since the output impedance of the high-speed digital output of the receiver is lower than the characteristic impedance of the cable, the signal is reflected here again. This reflected wave propagates again to the high-speed digital input terminal of the high-speed digital input device and is reflected again. Due to such a phenomenon, the waveform largely overshoots and undershoots, and the high-speed digital input device cannot correctly receive data.

(2) When a terminating resistor matching the characteristic impedance of the cable is attached to the signal line of the high-speed digital input terminal of the high-speed digital input device, the reflected wave is reduced, and the overshoot and undershoot are reduced. However, since the high-speed digital output of the receiver is TTL output,
The signal level becomes small, the offset (DC component) is not appropriate, and the amplitudes on the plus and minus sides with respect to the TTL input threshold are not always ensured uniformly. TTL malfunctions.

Due to these problems, the length of the cable connecting the high-speed digital output terminal of the receiver and the high-speed digital input terminal of the high-speed digital input device has been conventionally limited to about 50 cm.

Therefore, the following method is conceivable in order to enable correct reception even if the length of the cable is increased. That is, as in the above (2), a terminating resistor matching the characteristic impedance of the cable is connected to the high-speed digital input terminal of the high-speed digital input device to reduce reflection. Since the signal level is reduced, voltage comparison is performed using a voltage comparator IC (comparator) instead of TTL input. By properly setting the reference voltage for comparison, correct reception can be achieved.

[0008] However, the TTL output of the high-speed digital output terminal of the receiver has different characteristics depending on the manufacturer and the production lot. This is because the ARIB standard does not specify the type of TTL output, even though it is TTL output. For example, LS (Low Power Schottky), ALS
(Advanced low power Schottky), S (Schottky), F (Fast), etc. have different output characteristics. In addition, the same type may have different output current depending on the model number of the IC. For example, 74LS244 and 74LS367 used for the same purpose have the larger output current even if they are the same LS type. Therefore, T connected to the high-speed digital output terminal of the receiver
The maximum and minimum values of the signal at the high-speed digital input terminal vary depending on the type of the TL output IC. For this reason,
The reference voltage of the comparator of the high-speed digital input device cannot be fixedly set.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems in the prior art and makes it possible to increase the length of a cable connecting a digital output terminal of a digital broadcasting receiver and a digital input terminal of an input device. Is intended to provide a digital data input device capable of correctly receiving data even for different receivers.

[0010]

According to the present invention, a digital input terminal for separately inputting a data signal and a clock signal which are output in parallel from a digital output terminal of a digital broadcast receiver, and an average of the input clock signal are provided. An averaging circuit that outputs a signal of the averaged level, and a first comparator that compares the level of the input data signal with the output of the averaging circuit as a reference level, and performs waveform shaping from the first comparator. The extracted data signal is taken out.

The clock signal output from the digital broadcast receiver is output at the same level as the data signal and has a duty ratio of 50%. Therefore, the average level of the input clock signal is equal to the level of the input data signal. This is an intermediate level between the “H” level and the “L” level. Therefore, by comparing the level of the data signal with the averaged level as a reference level, even if the cable is long,
Also, data signals can be correctly received by receivers of different manufacturers and the like. Also, by comparing the level of the clock signal itself with the averaged level as a reference level, the clock signal can be correctly received. Even if the cable is long, the data signal can be transmitted to a receiver of a different manufacturer or the like. You can receive it more correctly.

Further, the present invention provides a digital input terminal for separately inputting a data signal and a clock signal output in parallel from a digital output terminal of a digital broadcast receiver, and a digital input terminal for inputting the input clock signal via an input resistor. An inverting amplifier configured to input to the inverting logic IC and feeding back the output of the inverting logic IC to the input of the inverting logic IC via a feedback resistor; and an averaging circuit for averaging the output signal of the inverting amplifier. An input terminal of the averaging circuit, a terminating resistor for connecting the output side of the averaging circuit to the input side of the input resistor, and an input threshold value which is the same as or substantially the same as that of the inverting logic IC. An inverting or non-inverting logic IC, and a terminating resistor for connecting an output side of the averaging circuit to an input side of the inverting or non-inverting logic IC. Te becomes, is made by taking out a waveform-shaped data signal from said inverting or non-inverting type logic IC.

When an input resistor is provided at the input of the inverting logic IC and a feedback resistor is provided between the input and the output, the inverting logic IC constitutes an inverting amplifier having an input threshold value at a virtual ground level (inverting amplifier). Type logic ICs do not have a hysteresis such as a Schmitt trigger.) Then, the output of the inverting logic IC is averaged by a low-pass filter or the like, and the averaged voltage is applied to the input side of the input resistance of the inverting logic IC via the terminating resistor to shift the level of the clock signal. In this manner, the intermediate value between the maximum value and the minimum value of the input clock signal is inverted regardless of the difference in the input characteristics of the inverting logic IC or the difference in the output characteristics of the digital broadcasting receiver. It can be made substantially equal to the input threshold value of the logic IC. Therefore, an inversion type or non-inversion type logic IC having the same or almost the same input threshold value as the above-mentioned inversion type logic IC is prepared, a data signal is input, and the averaged voltage is supplied through a terminating resistor. By shifting the level of the data signal by applying it to the input side of the inverting or non-inverting logic IC, the data signal becomes "H" around the threshold value or almost the threshold value of the inverting or non-inverting logic IC. "L" level. Thereby, the data signal can be correctly received.

Further, by preparing an inverted or non-inverted logic IC having the same or almost the same input threshold value as the inverted logic IC and inputting a clock signal, the clock signal is inverted or non-inverted. "H" around the threshold or almost the threshold of the inverting logic IC
The level changes to the “L” level, whereby the clock signal can be received correctly.

[0015]

Embodiments of the present invention will be described below. FIG. 2 shows an entire system of a digital satellite broadcast receiving apparatus. The system of FIG. 2 is a perfect TV! A personal computer 12 is connected as a high-speed digital input device to a commercially available tuner 10 for (trademark). The broadcasting of each program is transmitted as a digital signal from the transmitting device 16 of the broadcasting station, and is received by the antenna 20 of each user on the ground via the satellite (JCSAT-3) 18.
The received broadcast is input to the tuner 10.

A tuner 10 is a tuner for receiving digital satellite broadcasting, and is a perfect TV! It is a commercially available receiving tuner. The tuner 10 is provided with a video output terminal 44 and left and right audio output terminals 46 and 48 for decoding and outputting a video signal and an audio signal of a received program channel, and a video signal output from these output terminals 44, 46 and 48. The audio signal is transmitted to the television receiver 24 via the cable 22 and reproduced. The tuner 10 also has Perfect TV! Output terminal 3 of TTL output conforming to high-speed digital interface specifications
0 is provided. One end of a cable 26 is connected to the digital output terminal 30. The other end of the cable 26 is connected to the digital input terminal 50 of the personal computer 12. From the digital output terminal 30 of the tuner 10, raw data (M
The PEG-2 transport stream, that is, a bit stream in which video information, audio information, and data information are time-division multiplexed, is transmitted to the personal computer 12 via the cable 26 as it is.

An interface board 28 is additionally provided in the personal computer 12 as an extension board. FIG. 3 shows the configuration of the interface board 28. The interface board 28 shapes the waveform of the MPEG-2 transport stream output from the digital output terminal 30 of the tuner 10 by the receiver 32, and
4 The demultiplexer 34 extracts only necessary data packets from the data. The extracted data is output through a FIFO circuit 36 in synchronization with a read clock on the personal computer 12 side.
0 is supplied. The CPU 38 decodes the content of the data and sequentially loads the data into the hard disk 54 via the RAM 42. The data taken into the hard disk 54 is read by operating the mouse 76 or the keyboard 77, and the contents of the data are displayed on the display 14 (monitor).

The output of the tuner 10 shown in FIG.
FIG. 1 shows a detailed configuration of a portion between the input and the input of the interface board 28 of FIG. The digital output terminal 30 of the tuner 10 has an output terminal 30-1 for a clock signal (byte clock signal BCK defined by a high-speed digital interface specification for Perfect TV!), Its ground terminal 30-2, and an output terminal for a data signal. 30-3 and its ground terminal 30-4 are provided. The data signal and the clock signal are both TTL output and have the same output level. The digital input terminal 50 of the interface board 28 of the personal computer 12 is provided with a clock signal input terminal 50-1 and its ground terminal 50-2, and a data signal input terminal 50-3 and its ground terminal 50-4. . The digital output terminal 30 of the tuner 10 and the digital input terminal 50 of the interface board 28 are connected to each other by a corresponding transmission cable 56 (56-1, 56-1).
56-2, 56-3, 56-4,...).

In the interface board 28, a terminating resistor R1 is connected to the clock signal input terminal 50-1 to suppress signal reflection. Clock signal input terminal 5
The clock signal input from 0-1 is smoothed by a low-pass filter 60 (averaging circuit) composed of a resistor R2 and a capacitor C1, and a DC component is extracted. The comparator 62 outputs the output of the low-pass filter 60 to the operational amplifier 6.
The clock signal is input via the input terminal 4 and the clock signal is compared with the reference voltage as a reference voltage to output a waveform-shaped clock signal. On the other hand, the data input terminal 50-3 has a terminating resistor R3.
Is connected to suppress signal reflection. The data signal input from the data input terminal 50-3 is a comparator 66
Is input to The comparator 66 compares the voltage of the data signal with the DC component of the clock signal output from the operational amplifier 64 as a reference voltage, and outputs a waveform-shaped data signal. The subsequent circuit decodes the waveform-shaped data signal by using the waveform-shaped clock signal.

FIG. 4 shows the operation of the circuit shown in FIG. From the clock signal output terminal 30-1 and the data signal output terminal 30-3 of the tuner 10, a square wave clock signal and a data signal are output as shown in FIGS. The clock signal has a duty ratio of 50%. The signal levels of the clock signal and the data signal are equal.
These clock signals and data signals are transmitted through a cable 56
, The signal level is reduced and the waveform is rounded, and the waveform at the digital input terminal 50 of the interface board 28 is as shown in FIGS.

By smoothing the clock signal with a low-pass filter 60, a signal of an intermediate level between the "H" level and the "L" level of the input clock signal and data signal (dotted lines in FIGS. 4C and 4D). Are used as reference voltages, and the comparators 62 and 66 compare the voltages of the clock signal and the data signal, respectively, as shown in FIGS. 4 (e) and 4 (f). A clock signal and a data signal whose waveforms are equal to the clock signal and the data signal are obtained.

The configuration inside the interface board 28 shown in FIG. 1 shows the detailed configuration of the receiver 32 shown in FIG. 3, and the demultiplexer 34 shown in FIG. Extract the required data packet from the Further, the FIFO shown in FIG.
The circuit 36 synchronizes the extracted packet data with the clock of the personal computer 12 by reading the data at the falling timing of the waveform-shaped clock signal and reading it with the clock signal of the personal computer 12. FIF
The data signal read from the O circuit 36 is transmitted to the personal computer 1
Subsequent decryption processing is performed in 2.

In the above embodiment, the averaging circuit is constituted by a low-pass filter. However, the present invention is not limited to this. For example, the maximum value and the minimum value of the clock signal input are held, and the sum of the values is divided into two. It can also be composed of an output circuit or the like.
In the above-described embodiment, the invention is described as a perfect TV.
! A case where the present invention is applied to an input device for digital data output from a receiver for digital broadcasting has been described. However, the present invention is not limited to this. The present invention can also be applied to an input device for digital data output from a broadcast receiver.

[0024]

FIG. 5 shows another configuration example of a portion between the output of the tuner 10 and the input of the interface board 28 of the personal computer 12 in FIG. A clock signal and a data signal are output in parallel from the digital output terminal 30 of the tuner 10, and are input to the digital input terminal 50 of the interface board 28 via the cable 56.

The clock signal input to the digital interface board 28 is input to the inverting amplifier 70. The inverting amplifier 70 includes an inverting logic IC 72 such as 74HC04 or 74HCT04, an input resistor R1 connected to its input side, and a feedback resistor R2 connected between its output and input. By connecting the input resistor R1 and the feedback resistor to the inverting logic IC 72 in this way, the inverting logic IC 72 configures an inverting amplifier that sets its own input threshold to a virtual ground level. A capacitor C1 forming an averaging circuit is connected between the input and output of the inverting logic IC 72. The capacitor C1 functions to average the output of the inverting logic IC 72.

The output of the inverting amplifier 70 is connected to the input side of the input resistor R1 of the inverting amplifier 70 via a voltage follower and a terminating resistor R3. Inverting or non-inverting logic ICs 76 and 78 (7 in the example of FIG. 1) are connected to each input line of the data signal and the input line of the clock signal.
Inverting logic IC such as 4HC04, 74HCT04)
Are connected respectively. The voltage follower 7
4 output each logic I through a terminating resistor R4.
C76, 78 are connected to the input side.

The values of the terminating resistors R3 and R4 are set substantially equal to the characteristic impedance of each line of the cable 56.
The characteristic impedance of each line of the cable 56 is 100
In the case of Ω, the values of the resistors R3 and R4 are also set to about 100Ω. The input resistance R1 and the feedback resistance R2 of the inverting amplifier 70 are set to, for example, about 10 kΩ and 100 kΩ, respectively. The input thresholds of the logic ICs 76 and 78 and the input threshold of the inverting logic IC 72 are set equal or almost equal.

Waveform diagrams of the portions shown in FIGS. 5A to 5I are indicated by the same reference numerals in FIG. The level of the signal (e) at the virtual ground point of the inverting amplifier 70 is
2, which is 2.5V in the case of 74HC04. The data signal (a) and the clock signal (c) output from the tuner 10 are attenuated when transmitted through the cable 56, and have amplitudes as shown at (b) and (d) at the input end of the interface board 28, respectively. Becomes smaller. Now, the output clock (c) of the tuner 30
X, the line characteristic impedance of each cable 56 is R5 (= 100Ω), the average level of the input clock (d) of the interface board 28 is y, the level of the output (f) of the inverting amplifier 70 (= voltage follower). Assuming that the level of the output (g) of the signal 74 is z, the following equation holds.

Y = (x + z) / 2 z = [2.5− (y−2.5) · 10] By substituting x = (0 + 3.3) / 2 from FIG. 6A, z = 3.2 V y = 2.4 V

Therefore, the average level (1.65 V) of the output (0 V, 3.3 V) of the tuner 10 and the output (3.2 V) of the voltage follower 74 are applied to the logic IC 76 connected to the input line of each data signal. ) Is the characteristic impedance R5 (100Ω) of the cable 56.
And R5 obtained by dividing the voltage with the terminating resistor R4 (100Ω).
A data signal that rises and falls around the potential (2.4 V) at the middle point of R4 is input (FIG. 6B). Since the average level (2.4 V) of this data signal is substantially equal to the input threshold value (2.5 V) of the logic IC 76,
Can obtain a data signal having a correctly shaped waveform (FIG. 6 (h)). The average level of the clock signal input to the logic IC 78 connected to the input line of the clock signal is also 2.4 V (FIG. 6D), which is lower than the input threshold value (2.5 V) of the logic IC 78. Since they are almost equal, a clock signal whose waveform is correctly shaped is obtained from the logic IC 78 (FIG. 6 (i)). By increasing the value of the resistor R2 within a range where the output of the inverting amplifier 70 does not saturate, the potential at the intermediate point between R4 and R5 is set to the logic I
It is possible to further approach the input threshold (2.5 V) of C76, 78.

In FIG. 5, the averaging circuit is constituted by the capacitor C1 connected between the input and output of the inverting logic IC 72. However, instead of the capacitor C1, a resistor and a capacitor are connected between the inverting amplifier 72 and the voltage follower 74. Can be independently arranged.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, and is a circuit diagram showing a detailed configuration of a part of FIG. 3;

FIG. 2 is a block diagram showing the overall system configuration of a digital satellite broadcast receiving apparatus to which the present invention has been applied.

FIG. 3 is a block diagram illustrating a hardware configuration of the interface board of FIG. 2;

FIG. 4 is an operation waveform diagram of the circuit of FIG. 1;

FIG. 5 is a circuit diagram showing another embodiment of the present invention.

FIG. 6 is an operation waveform diagram of the circuit of FIG. 5;

[Explanation of symbols]

 Reference Signs List 10 tuner (digital broadcasting receiver) 12 personal computer (input device) 30 digital output terminal 50 digital input terminal 60 low-pass filter (averaging circuit) 62 second comparator 66 first comparator 70 inverting amplifier 72 inverting logic IC 76 , 78 Logic IC R1 Input resistance R2 Feedback resistance R3, R4 Termination resistance

Claims (4)

[Claims] 1. A digital input terminal for individually inputting a data signal and a clock signal output in parallel from a digital output terminal of a digital broadcast receiver, and outputting a signal of a level obtained by averaging the input clock signal. An averaging circuit, and a first comparator for comparing the level of the input data signal with the output of the averaging circuit as a reference level, and extracting a waveform-shaped data signal from the first comparator. Digital data input device. 2. The apparatus according to claim 1, further comprising a second comparator for comparing the level of the input clock signal with the output of the averaging circuit as a reference level, and extracting a waveform-shaped clock signal from the second comparator. 2. The digital data input device according to claim 1, wherein: 3. A digital input terminal for separately inputting a data signal and a clock signal output in parallel from a digital output terminal of a digital broadcast receiver; and an inversion type logic IC for inputting the input clock signal via an input resistor. And an inverting amplifier configured to feed back the output of the inverting logic IC to the input of the inverting logic IC via a feedback resistor; and an averaging circuit for averaging the output signal of the inverting amplifier. A terminating resistor connecting the output side of the averaging circuit and the input side of the input resistor; and an inverting type having the same or substantially the same input threshold value as the inverting type logic IC and inputting the data signal. A non-inverting type logic IC; and a terminating resistor for connecting an output side of the averaging circuit and an input side of the inverting type or non-inverting type logic IC. Digital data input device that is output from the type or the non-inverting type digital broadcasting receiver from the logic IC consisting retrieves the waveform-shaped data signal. 4. An inverted or non-inverted logic IC having the same or substantially the same input threshold value as the inverted logic IC and receiving the clock signal. 4. An input device for digital data output from a digital broadcast receiver according to claim 3, wherein a clock signal whose waveform has been shaped is taken out of the inversion type logic IC.