JPH10326882A - Semiconductor substrate and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing an SOI wafer of high quality with superior controllability, productivity and economy, and a wafer manufactured in the method. SOLUTION: In a wafer manufactured by bonding, after bonding, separating at a high porosity layer interface in a porous region 1 which is formed on the principal surface of a first Si substrate 2 and contains a low porosity thin layer 12 and a high porosity layer 13, a nonporous layer 14 is moved/mounted on a second substrate 3. After separating with the high porosity layer, the remaining low porosity thin layer 12 is made nonporous without utilizing selective etching by a smoothening process, such as hydrogen annealing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor substrate, and more particularly, to a method for forming an electronic device on a dielectric isolation layer or a single crystal semiconductor on an insulator or a single crystal compound semiconductor on a Si substrate. The present invention relates to a method for manufacturing a semiconductor substrate suitable for forming an integrated circuit.

[0002]

2. Description of the Related Art The formation of a single-crystal Si semiconductor layer on an insulator is performed by using a semiconductor-on-insulator (SO
I) The advantages of S, which are widely known as technologies and cannot be achieved with a bulk Si substrate for fabricating a normal Si integrated circuit,
Much research has been done on the use of devices utilizing OI technology. That is, by using the SOI technology, 1. Dielectric separation is easy and high integration is possible. 2. Excellent radiation resistance. 3. Higher speed due to reduced stray capacitance. 4. Well step can be omitted; 5. Latch-up can be prevented. Advantages such as the possibility of a fully depleted field-effect transistor by thinning can be obtained. These are described in detail in the following documents, for example. Special Issue: "Single-crystal silicon on
non-single-crystal insulators "; edited by GWCul
len, Journal of Crystal Growth, Vol. 63, No. 3, pp. 4
29-590 (1983) In recent years, SOI substrates have
Many reports have been made as substrates for realizing high-speed ET and low power consumption. (IEEE SOIConfe
Further, since the use of the SOI structure has an insulating layer below the device, the device isolation process can be simplified as compared with the case where the device is formed on a bulk Si wafer, and the device process process is shortened. . That is, the MOSF on the bulk Si
Compared with ETs and ICs, a reduction in the total cost of wafers and process costs is expected.

[0003] Above all, a fully depleted MOSFET is expected to achieve higher speed and lower power consumption by improving the driving force.
The threshold voltage (Vth) of a MOSFET is generally determined by the impurity concentration of a channel portion, but is completely depleted (FD) using SOI.
In the case of OSFET, the thickness of the depletion layer is also affected by the thickness of the SOI. Therefore, in order to produce a large-scale integrated circuit with high yield, uniformity of the SOI film thickness has been strongly desired.

[0004] Devices on compound semiconductors have high performance that cannot be obtained with Si, such as high speed and light emission. At present, most of these devices are formed by epitaxial growth on a compound semiconductor substrate such as GaAs. However, compound semiconductor substrates have problems such as being expensive, having low mechanical strength, and making it difficult to manufacture large-area wafers.

[0005] For these reasons, attempts have been made to heteroepitaxially grow compound semiconductors on Si wafers, which are inexpensive, have high mechanical strength, and can produce large-area wafers.

A study on the formation of SOI substrates was conducted in 1970.
It has been active since the age of. Initially, a method of heteroepitaxially growing single-crystal Si on a sapphire substrate, which is an insulator (SOS: Sapphire on Silicon), or a method of forming an SOI structure by dielectric isolation by oxidation of porous Si (FIPOS: Fully Isolation by PorousOxi
dized Silicon), an oxygen ion implantation method has been well studied.

In the FIPOS method, an N-type Si layer is ion-implanted with protons on the surface of a P-type Si single crystal substrate (Imai et al., J. Crystal Growth, Vol. 63, 547 (1983)), or epitaxial growth and patterning are performed. After forming only the P-type Si substrate into a porous form by anodizing in an HF solution so as to surround the Si island from the surface, the N-type Si island is dielectrically separated by accelerated oxidation. Is the way.
This method has a problem that the separated Si region is determined before the device process, which may limit the degree of freedom in device design.

The oxygen ion implantation method is described in K. This is a method called SIMOX first reported by Izumi. Oxygen ions are introduced into the Si wafer at 10 ¹⁷ to 10 ¹⁸ / cm ²
About 1320 in an argon / oxygen atmosphere.
Anneal at a high temperature of about ° C. As a result, oxygen ions implanted around the depth corresponding to the projection range (Rp) of the ion implantation are combined with Si to form an Si oxide layer. At this time, the Si layer which has been made amorphous by oxygen ion implantation on the upper part of the Si oxide layer is also recrystallized to become a single crystal Si layer. Defects contained in the surface Si layer are conventionally 10 ⁵ / cm ²
But the amount of oxygen implanted was 4 × 10 ¹⁷ / cm ²
By near, it has been successfully reduced to ~10 ² / cm ^2. However, implantation energy that can maintain the film quality of the silicon oxide layer, the crystallinity of the surface Si layer, and the like,
Since the range of the implantation amount is narrow, the film thicknesses of the surface Si layer and the buried oxide Si layer (BOX; Burried Oxide) are limited to specific values. In order to obtain a surface Si layer having a desired film thickness, sacrificial oxidation or epitaxial growth was necessary. In this case, there is a problem in that the uniformity of the film thickness is deteriorated as a result of superimposing the deterioration due to these processes on the distribution of the film thickness.

[0009] The BOX has an oxidized S called a pipe.
It has been reported that a poorly formed region i exists. One of the causes is considered to be foreign matter such as dust at the time of injection. In the portion where the pipe is present, device characteristics deteriorate due to leakage between the active layer and the supporting substrate.

As described above, SIMOX ion implantation requires a larger amount of ion implantation than the ion implantation used in a normal semiconductor process. Therefore, even if a dedicated apparatus is developed, the implantation time is long. Since the ion implantation is performed by raster-scanning or expanding the ion beam having a predetermined current amount, the implantation time is expected to increase with an increase in the area of the wafer. In addition, it has been pointed out that in the high-temperature heat treatment of a large-area wafer, problems such as generation of slip due to temperature distribution in the wafer become more severe. 1 for SIMOX
In the Si semiconductor process of 300 ° C. or higher, heat treatment at a high temperature that is not usually used is essential.
There is concern that the issues to be overcome, such as metal contamination and slippage, will become even more important.

In addition to the conventional SOI forming method as described above, in recent years, a Si single crystal substrate is bonded to another thermally oxidized Si single crystal substrate using a heat treatment or an adhesive to form an SOI structure. The method of forming has attracted attention. This method requires that the active layer for the device be uniformly thinned. That is, it is necessary to reduce the thickness of a Si single crystal substrate having a thickness of several hundred μm to the order of μm or less. There are three methods for reducing the thickness as follows.

1. 1. Thinning by polishing 2. Thinning by local plasma etching Thinning by Selective Etching It is difficult to achieve a uniform thinning by the polishing method 1.
In particular, when the thickness is reduced to sub-μm, the variation becomes several tens%, and the uniformity is a serious problem. Further, as the diameter of the wafer increases, the difficulty only increases.

In the method 2, a film is first thinned to a thickness of about 1 to 3 μm by a single polishing method, and then the film thickness distribution is measured at multiple points over the entire surface. Etching is performed while correcting the film thickness distribution by scanning a plasma using SF ₆ or the like to reduce the film thickness to a desired film thickness. It is reported that this method can make the film thickness distribution approximately ± 10 nm. However, if foreign matter (particles) is present on the substrate during plasma etching, the foreign matter serves as an etching mask, so that a projection is formed on the substrate.

Since the surface is rough immediately after the etching, touch polishing is required after the plasma etching is completed. However, since the control of the polishing amount is performed by time management, the final film thickness is controlled, and the film by the polishing is controlled. Deterioration of thickness distribution has been pointed out. Further, in the polishing, since an abrasive such as colloidal silica directly rubs the surface to be the active layer, there is a concern about formation of a crushed layer and introduction of processing distortion by polishing. Further, when the area of the wafer is increased, the plasma etching time increases in proportion to the increase of the wafer area, and there is a concern that the throughput may be significantly reduced.

Method 3 is a method in which a film structure that can be selectively etched is formed in advance on a substrate to be thinned. For example, a thin layer of P ⁺ Si containing boron at a concentration of 10 ¹⁹ / cm ³ or more and a thin layer of P-type Si are stacked on a P-type substrate by a method such as epitaxial growth to form a first substrate. After bonding this to the second substrate via an insulating layer such as an oxide film, the back surface of the first substrate is thinned in advance by grinding and polishing. Then, by selective etching of the P-type layer,
The P ⁺ layer is exposed, and the P type layer is exposed by selective etching of the P ⁺ layer to complete the SOI structure. This method is detailed in the report of Maszara (WPMaszara, JE
electrochem. Soc., Vol. 138, 341 (1991)).

Although selective etching is effective for uniform thinning, it has the following problems. - at most 10 ² about the selection ratio is not sufficient. -Touch polish is required after etching due to poor surface properties after etching. However, as a result, as the film thickness decreases, the film thickness uniformity tends to deteriorate. Particularly, in polishing, the polishing amount is controlled depending on the time. However, since the polishing rate varies widely, it is difficult to control the polishing amount. Therefore, there is a particular problem in forming an ultra-thin SOI layer having a thickness of 100 nm. The crystallinity of the SOI layer is poor because ion implantation, epitaxial growth on a high concentration B-doped Si layer or heteroepitaxial growth is used. Further, the surface properties of the surface to be bonded are inferior to those of a normal Si wafer.

The above is described in C. Harendt, et al., J. El.
ect. Mater. Vol. 20, 267 (1991), H. Baumgart, et a.
l., Proceeding of the 1st International Symposium
on Semiconductor Wafer Bonding: Science, Technolog
y and Applications, (The Electrochemical Society)
Vol.92-7, p.375, CE Hunt et al., Proceeding oft
he 1st International Symposium on Semiconductor Wa
fer Bonding: Science, Technology and Applications,
(The Electrochemical Society) Vol.92-7, p.165.

The selectivity of the selective etching largely depends on the concentration difference of impurities such as boron and the steepness of the profile in the depth direction. Therefore, when a high-temperature bonding anneal for increasing the bonding strength or a high-temperature epitaxial growth for improving the crystallinity are performed, the depth direction distribution of the impurity concentration is widened, and the etching selectivity is deteriorated. That is, it has been difficult to achieve both the improvement of the etching selectivity and the improvement of the crystallinity and the bonding strength.

Recently, Yonehara et al. Solved such a problem and reported a bonded SOI having excellent film thickness uniformity and crystallinity and capable of batch processing (T. Yonehara et al., Appl. Phy.
s. Letter Vol. 64, 2108 (1994)). In this method, the porous layer 32 on the Si substrate 31 is used as a material for selective etching. After the non-porous single-crystal Si layer 33 is epitaxially grown on the porous layer, the non-porous single-crystal Si layer 33 is bonded to the second substrate 34 via the Si oxide layer (insulating film) 35 (FIG. 5A). The first substrate is thinned from the back surface by grinding or the like to expose the porous Si over the entire surface of the substrate (FIG. 5B). The exposed porous Si is KOH, HF + H ₂
It is removed by etching with a selective etching solution such as O ₂ (FIG. 5C). At this time, the etching selectivity of the porous Si to the bulk Si (non-porous single-crystal Si) can be sufficiently increased to 100,000 times, so that the non-porous single-crystal Si layer previously grown on the porous layer has a thickness of 100 nm. Can be left on the second substrate without substantially reducing the SOI substrate. Therefore, the thickness uniformity of the SOI is substantially determined during the epitaxial growth. Since epitaxial growth can use a CVD apparatus usually used in a semiconductor process, according to a report by Sato et al. (SSDM95), the uniformity is realized within, for example, 100 nm ± 2%. In addition, the crystallinity of the epitaxial Si layer was good, and 3.5 × 10 ² / cm ² was reported.

[0020] Porous Si is manufactured by Uhlir et al.
It was discovered in the research process of electropolishing of semiconductors in 6 years (A. Uhlir, Bell Syst. Tech. J., Vol. 35 333 (195
6)). Porous Si can be formed by anodizing a Si substrate in an HF solution. Porous Si is fine pores formed by electrolytic etching in bulk Si like sponge just like sponge. Depending on the conditions of anodization and the specific resistance of Si, pores having a diameter of about several nm It is formed at a density of about 10 ¹¹ / cm ² .

Unagami et al. Studied the dissolution reaction of Si in anodization and reported that the anodic reaction of Si in an HF solution requires holes, and the reaction is as follows (T .Unagami, J. Electrochem. Soc., Vol. 127, 476
(1980)).

Si + 2HF + (2-n) e ⁺ → Si
_{^{F 2 + 2H + + ne -}} SiF 2 + 2HF → SiF 4 + H 2 SiF 4 + 2HF → H 2 SiF 6 or, Si + 4HF + (4- λ) e + → SiF 4 + 4H + +
λe ⁻ SiF ₄ + 2HF → H ₂ SiF ₆ Here, e ⁺ and e ⁻ represent a hole and an electron, respectively. Further, n and λ are the number of holes required for dissolving one atom of Si, respectively, and it is assumed that porous Si is formed when the condition of n> 2 or λ> 4 is satisfied.

From the above, it can be seen that P-type Si having holes exists.
Is made porous, but N-type Si is not made porous. The selectivity in this porous formation has been demonstrated by Nagano et al. And Imai (Nagano, Nakajima, Yasuno, Onaka, Kajiwara, IEICE Technical Report, Vol. 79, SSD79-9549 (1979)),
(K. Imai, Solid-State Electronics, Vol. 24, 159 (19
81)).

In the conventional method, the selectivity of etching depends on the difference in impurity concentration and the profile in the depth direction. Therefore, the temperature of heat treatment (bonding, epitaxial growth, oxidation, etc.) for expanding the concentration distribution is generally 800 ° C. or less. Was greatly restricted. On the other hand, in the etching in this method, since the difference in the structure between porous and bulk determines the etching speed, the restriction of the heat treatment temperature is small and
It is reported that heat treatment at about 180 ° C. is possible. For example, heat treatment after bonding increases the bonding strength between wafers, and voids generated at the bonding interface.
It is known to reduce the number and size of Also,
In the etching based on such a difference in structure, even if particles adhere to porous Si, they do not affect the uniformity of the film thickness.

In general, on a light-transmitting substrate represented by glass, the deposited thin-film Si layer is amorphous or amorphous due to the disorder of the crystal structure due to the disorder of the substrate. It is only a polycrystalline layer at best, and a high-performance device cannot be manufactured. This is due to the fact that the crystal structure of the substrate is amorphous, and even if a Si layer is simply deposited, a high-quality single crystal layer cannot be obtained.

However, a semiconductor substrate using bonding always requires two wafers, and one of them is almost completely wasted and discarded by polishing, etching or the like, which is a factor of cost increase. Not only can it be wasted, but it could waste limited Earth resources.

In order to take advantage of the characteristics of SOI using bonding, there has been a demand for a method of producing a SOI substrate of sufficient quality with good reproducibility, and at the same time, realizing resource saving and cost reduction by reusing a wafer.

Consumed in the bonding method,
A method of reusing the first substrate has recently been reported by Sakaguchi et al. (JP-A-07-302889).

In the method of bonding and etching back using the porous Si described above, they replace the step of grinding and etching the first substrate from the back surface to expose the porous Si by thinning. The following method was adopted.

After the surface layer of the first Si substrate 41 is made porous to form a porous layer 42, a single-crystal Si layer 43 is formed thereon.
Is formed, and the single crystal Si layer 43 and the first Si substrate 41 are formed.
Then, the main surface of the second Si substrate 44, which is different from the above, is bonded with the insulating layer 45 interposed therebetween (FIG. 6A). Thereafter, the bonded wafer is divided by a porous layer (FIG. 6 (b)),
The SOI substrate is formed by selectively removing the porous Si layer exposed on the surface on the side of the Si substrate by etching (FIG. 6C). Dividing the bonded wafers is performed by applying a sufficient tensile force or pressure evenly in the direction perpendicular to the surface to the bonded wafers, applying pressure, applying wave energy such as ultrasonic waves, and the wafer end surface. To expose the porous layer, etch the porous Si to some extent, insert something like a razor blade into it, expose the porous layer on the wafer end face, and apply a liquid such as water to the porous Si. After soaking, the whole bonded wafer is heated or cooled to expand the liquid, or a force is applied to the first (or second) substrate in the horizontal direction to the second (or first) substrate. The method of destroying the porous Si layer by such a method is used.

These are based on the fact that the mechanical strength of porous Si differs depending on the porosity, but is considered to be sufficiently weaker than bulk Si. For example, if the porosity is 50
%, The mechanical strength can be considered to be half that of the bulk. That is, when compressing, pulling, or applying a shearing force to the bonded wafer, the porous Si layer is first destroyed. Also, if the porosity is increased, the porous layer can be broken with a weaker force.

Here, the porosity is defined as the ratio of the volume occupied by the pores to the material of the porous layer in the volume of the porous layer.

However, in the method described in Japanese Patent Application Laid-Open No. 07-302889, the position of the peeling in the porous layer in the thickness direction cannot be specified, and the yield is lowered due to the different places where the peeling occurs in the layer on the wafer. There was something.
Furthermore, even if the residual thickness of the remaining portion of the porous Si layer after being peeled off in the wafer surface varies, even if high selective etching is used,
In order to satisfy the SOI specification aiming at high film thickness uniformity, the yield may decrease.

Japanese Patent Application Laid-Open No. Hei 8-213645 describes a method for separation by a porous layer, but does not describe the layered structure of the porous layer. Separately from this, proceedings of the 1996 Autumn Meeting of the Japan Society of Applied Physics p. In 673, Sony's Inaka Nakanaka and others changed the current in the middle,
Is described.

[0035]

Problems to be Solved by the Invention
No. 5 describes that the separation layer can be peeled from any part of the separation layer. In other words, the position at which the separation layer is peeled cannot be specified. In this case, the residual porous S in the wafer surface
If the thickness of the i-layer is variable and the etching rate of the active layer (device layer), which is a non-porous single-crystal layer, is not 0 even when the porous Si is removed by etching, the active layer is etched to some extent. This causes in-plane variation of the layer thickness, and even when used while remaining, a surface step depending on the peeling position remains as it is. Also, the above-mentioned proceedings of the 1996 Autumn Society of Applied Physics, p.
Even in the method of No. 673, it is said that the porous Si layer is peeled off at the center of the porous Si, and it is necessary to remove the remaining portion of the porous Si layer remaining on both the substrate sides.

The step of etching the porous layer has been considered to be an indispensable step for producing a high-quality bonded SOI substrate. However, the etching step requires additional steps other than the actual steps such as loading and unloading the substrate into and out of the etching apparatus, management of the etching apparatus and etchant, and cleaning after etching. If the etching step can be omitted, the manufacturing time of the SOI substrate can be greatly reduced.

Even if all of the conventional etching steps cannot be omitted, if the etching time can be greatly reduced, the manufacturing time of the SOI substrate can be shortened, and the SOI substrate can be provided at low cost.

It is an object of the present invention to provide a method for manufacturing a semiconductor substrate which can omit or shorten the step of selectively etching a porous layer.

Another object of the present invention is to provide a method for manufacturing a semiconductor substrate, which can manufacture a semiconductor substrate typified by a high-quality SOI substrate at low cost.

[0040]

According to the present invention, there is provided a first substrate having a porous region including at least two layers having different porosity, and a non-porous layer on the porous region. Adhering the surface of the non-porous layer of the first substrate and the surface of the second substrate, separating the first and second substrates, Transferring to a second substrate; and removing or rendering non-porous the remaining portion of the porous region remaining on the separation surface of the second substrate to smooth the separation surface. The step of preparing one substrate includes: a first porous layer having a thickness of 1 μm or less; a second porous layer adjacent to the first porous layer and having a high porosity; And forming the non-porous layer adjacent to the porous layer.

[0041]

FIG. 1 is a view showing a method of manufacturing a semiconductor substrate according to the present invention. As shown in FIG.
A first substrate 2 having a porous region 1 including at least two layers 12 and 13 having different porosity and a non-porous layer 14 on the porous region 1 is prepared. Reference numeral 11 denotes a substrate.

Next, as shown in FIG. 1B, the surface of the non-porous layer 14 of the first substrate 2 and the surface of the second substrate 3
Paste. Reference numeral 15 denotes a non-porous insulating layer, and reference numeral 16 denotes a substrate.

Then, as shown in FIG.
The substrate 2 and the second substrate 3 are separated from each other to form a non-porous layer 14.
Is transferred to the second substrate 3.

Thereafter, as shown in FIG.
The remaining portion 12 ′ of the porous layer 12 remaining on the separation surface of the substrate 3 is removed or made non-porous to smooth the separation surface.

In particular, when the first substrate 2 is prepared as shown in FIG. 1A, the thickness of the first porous layer 12 adjacent to the non-porous layer 14 in the porous region is determined. Is set to 1 μm or less, more preferably 0.5 μm or less. Then, the porosity (PS2) of the second porous layer 13 adjacent to the first porous layer 12 is changed to the porosity (PS1) of the first porous layer 12.
Make it higher.

The thickness of the low-porosity (PS1) first porous layer between the nonporous layer 14 and the high-porosity (PS2) second porous layer is reduced to 1 μm or less. Thereby, the two substrates are separated near the interface between the first porous layer and the second porous layer parallel to the surface of the non-porous layer 14.

The remaining portion 12 'of the first porous layer remaining on the surface of the non-porous layer transferred to the second substrate has a low porosity (P
S1), the thickness is small, and the thickness is substantially uniform over the entire separation surface. The remaining portion 12 'of the first porous layer is transformed into non-porous by heat-treating the remaining portion 12' in a non-oxidizing atmosphere, and is integrated with the underlying non-porous layer 14, and The surface is smoothed. In this manner, when removing the residual portion 12, no selective etching or selective polishing is performed at all, or only a very short etching is required.

The porosity PS1 of the first porous layer of the present invention
Is selected from a range not exceeding 40%. Specifically, it is 1% to 40%.

More preferably, the upper limit is selected from a range not exceeding 25%. Specifically, it is 1% to 25%.

The porosity PS2 of the second porous layer of the present invention
Satisfies the relationship of PS2> PS1. Preferably higher than 25%, more preferably 40%
It is better to be higher. Specifically, it is 25% to 90%, more preferably 40% to 90%.

The thickness of the second porous layer is 10 n
m and 1 μm or less. And
More preferably, it is desirable that the thickness of the second porous layer is larger than the thickness of the first porous layer.

As the first substrate used in the present invention,
After the surface of the semiconductor substrate 11 is made porous, a non-porous layer is formed on the porous region, a porous layer and a non-porous layer are formed on the substrate 11, and the surface of the substrate is made porous. After the surface treatment, the surface layer of the porous region is returned to a non-porous state.

As the non-porous layer used in the present invention,
A semiconductor formed by at least one of epitaxial growth on the porous region and nonporous treatment of the porous region is included.

Specifically, non-porous single-crystal Si, GaAs
semiconductors such as s and InP. Further, it is not essential that these thin films are formed on the entire surface, and they may be partially etched by a patterning process.

An insulating layer such as an oxide film may be formed on the surface side of the non-porous layer.

For example, the porous region can be formed by anodizing a Si substrate in an HF solution. The porous layer is 10 ^-1 to 10 n
It has a sponge-like structure in which holes having a diameter of about m are arranged at intervals of about 10 ^-1 to 10 nm. The density can be increased by changing the HF solution concentration in the range of 50 to 20%, changing the alcohol addition ratio, or changing the current density, as compared with the density of single crystal Si of 2.33 g / cm ^3. 0.1 to 0.6 g / cm ³ . If the specific resistance and the electric conductivity type of the portion to be made porous are modulated in advance, it is possible to change the porosity based on this. In the p-type, under the same anodizing conditions, the non-degenerate substrate (P ⁻ ) has a smaller pore diameter but a higher pore density by about one digit and higher porosity than the degenerate substrate (P ⁺ ). That is, the porosity can be controlled by varying these conditions. In this way, the density of porous Si can be reduced to less than half that of single-crystal Si, but the single-crystal property is maintained, and a single-crystal Si layer can be epitaxially grown on top of the porous layer. It is. However, if the temperature is higher than 1000 ° C., rearrangement of the internal holes occurs, and the characteristics of the accelerated etching are impaired. For this reason, low temperature growth such as molecular beam epitaxy, plasma CVD, low pressure CVD, photo CVD, bias sputtering, liquid phase epitaxy, etc. is suitable for the epitaxial growth of the Si layer on the porous layer. However, high-temperature growth is also possible if a protective film is previously formed on the side wall surfaces of the holes of the porous layer by a method such as oxidation.

In the porous layer, a large amount of fine voids are formed inside the porous layer, so that the surface area is dramatically increased as compared with the volume. At the same time, the semiconductor material exists only as very thin walls. Therefore, the chemical etching rate, coupled with the permeation of the etching solution by the capillary phenomenon,
The speed is significantly increased as compared with the etching rate of a normal single crystal layer.

The mechanical strength of the porous region depends on the porosity, but is considered to be weaker than that of the bulk. Also, the higher the porosity, the lower the mechanical strength. That is, when compressing, pulling or applying a shearing force to the bonded wafer,
First, the porous layer is destroyed. Further, if the porosity is increased, the porous layer can be broken with a weaker force.

The layer structure of the porous region in the present invention has at least two layers having different porosity, that is, a thin layer having a low porosity and a layer having a high porosity in order from the surface side.
By arranging a low-porosity porous layer on the surface, the crystallinity and surface roughness of the non-porous layer formed on the porous region, especially the epitaxial layer, are significantly improved. The crystallinity greatly affects the yield as well as the characteristics of the electronic device formed on the semiconductor substrate. For example, when the crystal defects of the epitaxial Si layer on the porous body having the porosity of 50% are 1 × 10 ⁵ / cm ² , the crystal defects of the epitaxial layer on the porous body having the porosity of 20% are 5 × 10 5 under the same growth conditions. ³ / cm ² and one and a half digits different. Also,
When the surface roughness is represented by the mean square roughness Rrms in the measurement with an atomic force microscope in a region of 50 μm square, the surface roughness greatly differs from 1.2 nm and 0.3 nm, respectively. In addition,
If the surface roughness is large, it is disadvantageous in the bonding step.

The first porous layer having a low porosity on the surface is approximately 1
μm or less, but more preferably a thickness of 0.5 μm or less, it is possible to make the remaining layer non-porous and smooth the surface by a surface smoothing treatment after the separation step. . Under these conditions, if the porosity of the low-porosity first porous layer is 40% or less, more preferably 25% or less, it is possible to achieve both the crystal quality and the surface roughness of the epitaxial layer. is there.

The second porous layer having a high porosity immediately below the first porous layer having a low porosity can be produced by controlling the various conditions of the anodization described above. It is sufficient that the thickness of the second highly porous layer is 10 nm or more, and 1 μm or less, more preferably 0.5 μm, in order to limit the peeling position.
It is desirable that: There is no particular problem if a third porous layer is further formed below the second porous layer, but the porosity of the third porous layer immediately below the high porosity layer is changed to the second porosity of the second porous layer. By making it lower than the porous layer, the peeling position is further stabilized, and the surface roughness after the surface smoothing treatment after the separation step is improved.

The second porous layer having a high porosity can also be formed by using both a porous treatment and ion implantation.

For example, when helium or hydrogen ions are implanted into bulk Si and heat treatment is applied, a microcavity having a diameter of several nm to several tens nm is formed in the implanted region.
is reported to form at densities as high as -10 ^16-17 / cm ³ (eg, A. Van Veen, CC Grind).
ffioen, and JH Evans, Mat, Res.Soc.Symp.Poro
c. 107 (1988, Material Res.Soc.Pittsburgh, Pennsy
lvania) p.449).

Recently, studies have been made to utilize these microcavities as gettering sites for metal impurities.

V. Raineri and SU Campisano implanted helium ions into bulk Si and heat-treated to form a group of cavities, then formed a groove in the substrate to expose the side surfaces of the cavities of the group of cavities and oxidized them. did. As a result, the cavities were selectively oxidized to form a buried Si oxide layer. That is, S
Reported that an OI structure can be formed (V. Raineri, and
SU Canpisano, Appl. Phys. Lett. 66 (1995) p.36
54). However, according to their method, the thicknesses of the surface Si layer and the buried Si oxide layer are limited to a point that both the formation of the cavity group and the relaxation of the stress introduced by the volume expansion during the oxidation are compatible. Therefore, a groove must be formed, and an SOI structure cannot be formed on the entire surface of the substrate. The formation of such cavities has been reported as a phenomenon associated with the injection of light elements into the metal, as well as the swelling or separation of these cavities, as part of a study on the first reactor wall of a fusion reactor. .

It is well known that bubbles are generated in the ion-implanted layer as described above, and the ion-implanted layer has a structure as if a porous material was formed inside. Therefore, this layer is mechanically fragile, and can be subjected to accelerated oxidation and accelerated etching as in the case of anodized porous material.

The ion-implanted element is not limited to hydrogen or a rare gas, but may be an implanted damage layer, a high-concentration layer (strained layer) of the implanted element, or a bubble layer near the interface.

If ion implantation is performed so that the projection range is included in the porous layer formed by anodization, bubbles are formed in the porous pore walls near the projection range, and the porosity is increased. The ion implantation may be performed before or after the formation of the porous layer by anodization. Further, it may be after forming the non-porous layer structure.

In the step of epitaxial growth on the porous layer, baking (heat treatment) in H ₂ to fill the surface pores of the porous Si is very effective in improving the quality of the epitaxial layer as the first step (N . Sato, et a
l., J. Electrochem.Soc., Vol. 142, No. 9, 3116 (199
Five)). In the H ₂ bake, the constituent atoms of the porous outermost layer are consumed to fill the pores. Therefore, if the outermost surface before the H ₂ bake is a thin layer having a low porosity, the sealing of pores in the hydrogen bake is promoted. If this low porosity thin layer is thinned to approximately 1 μm or less, more preferably 0.5 μm or less, it is possible to arrange a porous layer having high porosity near the lower portion of the epitaxial layer after epitaxial growth,
This allows separation in the porous region near the epitaxial layer, and the thickness of the low-porosity thin layer remaining after separation can be reduced to less than 1 μm, and sometimes to less than 0.5 μm. Is possible. Also, H
If to remove an oxide film on the side wall of porous holes in the vicinity of the surface of the porous layer by immersing a substrate to form a porous region prior to the _two-bake in HF-containing solution, an oxide film divided by the HF The non-porous part of the exposed surface layer that has not been made non-porous during the heat treatment process including during the H ₂ bake causes aggregation of the pores, lacks an oxide film on the sidewalls of the pores, reduces the mechanical strength, and causes separation. A layer that is easily formed is formed.

After the anodization, if the porous layer is passed through a high-temperature process such as epitaxial growth, surface oxidation, and heat treatment for bonding without being oxidized at a low temperature, the porous layer undergoes a structural change, and has micropores during the anodization. The objects aggregate the pores and cause the pores to expand. By utilizing this, the separation near the lower portion of the epitaxial layer can be promoted due to the expansion of the hole immediately below the epitaxy layer and the strain between the porous Si and the epitaxial Si.

In the present invention, following the separation of the bonded wafers in the second porous layer of high porosity, smoothing of the remaining portions of low porosity remaining on the surface of the transferred non-porous layer Perform processing.

As the smoothing treatment, a heat treatment in a non-oxidizing atmosphere or a heat treatment in a vacuum is preferable.
It is not limited to this. In the heat treatment, hydrogen, or He, Ne,
An inert gas such as N, Ar, kr, or Xe, or a mixed atmosphere thereof is desirable. In the heat treatment in a vacuum, the degree of vacuum is desirably 10 ⁻⁷ Torr or less. In any case, residual oxygen and moisture remaining as impurities in the atmosphere must be kept low because they oxidize the surface to form a protective film and hinder the smoothing of the surface. It is desirable that the atmosphere has a dew point of −92 ° C. or less.

In such an atmosphere, surface irregularities are smoothed by migration of surface atoms in order to minimize surface energy. In particular, when hydrogen is contained in the atmosphere, the formation of the protective film is suppressed by the reducing action, and the surface smoothing is promoted. The present inventors have studied the relationship between such a surface smoothing effect and the thickness of the residual porous layer,
If the porous layer is approximately 1 μm or less, more preferably 0.5 μm or less, the surface can be smoothed by the heat treatment, and cavities due to residual pores can be prevented from being generated in the layer after the smoothing. In other words, they have found that it can be made nonporous. When the thickness of the residual porous layer is large, the residual holes are likely to remain inside as cavities.
In the flattening by the heat treatment, the smoothing of the surface mainly proceeds by migration of surface atoms, so that the etching amount is suppressed to a very low level. In particular, when the residual oxygen and moisture in the atmosphere are suppressed to a low level, the etching amount can be reduced to almost zero.

As previously reported, since it is not necessary to use a long selective etching step, not only the effect of shortening or reducing the steps but also the excessive etching of the non-porous layer which occurs when the etching selectivity is not sufficient. The problem of deterioration of the film thickness uniformity due to the above is also unlikely to occur. Therefore,
The uniformity of the epitaxial Si film as the non-polycrystalline layer does not deteriorate at all.

According to the present invention, the non-polycrystalline epitaxial Si film formed on the single-crystal porous layer can be transferred to another substrate without separating and selectively etching. In particular, since defects peculiar to bulk Si do not propagate to the epitaxial Si film, it is possible to improve the device yield. Even now, CPU
Epitaxial wafers are used for high-performance LSIs such as. It is said that in the future, the diameter of wafers will increase, and it will be difficult to manufacture high-quality crystals by the pulling method, and it will be difficult to maintain the quality of bulk wafers. Therefore,
Increasingly, the need for epitaxial wafers is increasing. Naturally, the need for an epitaxial film also increases in an SOI substrate that replaces a bulk wafer.

The electric conductivity type and impurity concentration of the non-porous layer can be arbitrarily set by controlling the electric conduction type during epitaxial growth and the impurity concentration. Various types of SOI substrates having different concentrations can be manufactured.

Further, if an epitaxial film having a multi-layered structure of different electric conductivity type or impurity concentration is formed, the SOI substrate having a high concentration buried layer can be used as a multi-layer SOI substrate.
An I substrate can also be manufactured.

The above-mentioned various functions are described in JP-A-5-21.
It is impossible with a method such as 1128 in which the outermost surface layer of a bulk wafer is peeled off by ion implantation and transferred to another substrate.

In the case where both the porous region and the lower layer in contact with the porous region in the non-porous layer are layers epitaxially grown, the thickness of the first substrate is reduced even if it is used many times. Can be reused semi-permanently. Therefore, in addition to the above-mentioned high quality, there is a great advantage in terms of resource saving and cost particularly in the case of a large-diameter wafer.

In addition, it was difficult and expensive to obtain a large-diameter wafer with good crystallinity from a compound semiconductor single crystal. However, according to the present method, a compound semiconductor single crystal film having good crystallinity can be formed on a large-area substrate by using heteroepitaxial growth on a porous Si region.

On the other hand, in the present invention, after the substrate is made porous, the surface layer of the porous substrate can be made into a non-porous single crystal layer by a heat treatment at a temperature not higher than the melting point. In this case, a non-porous single crystal layer having good crystallinity can be formed on the surface of the porous substrate without using a semiconductor source gas such as silane. Furthermore, the surface of the formed non-polycrystalline single-crystal layer is oxidized and bonded to the other substrate, or the non-porous single-crystal layer is bonded to the other substrate whose surface is oxidized, or both. After the surface is oxidized and bonded, it is peeled off from the high porosity layer, and the remaining low porosity part is smoothed to have a good single crystal structure on the oxide layer, uniform over a large area A single crystal layer which is flat and has few defects can be formed.

Further, the method of manufacturing a semiconductor substrate according to the present invention
The first Si substrate separated by the above method can be removed by removing the remaining porous layer, or if it is not necessary to remove the remaining porous layer, or if the surface flatness is insufficient, by performing a surface flattening treatment. It can be reused again as the first substrate, the next second substrate, or as a substrate for other uses. This surface flattening treatment may be a method such as polishing and etching usually used in a semiconductor process, but may be heat treatment in a non-oxidizing atmosphere. As the non-oxidizing atmosphere, hydrogen, an inert gas, or a mixed gas atmosphere thereof is particularly preferable. Alternatively, heat treatment in a vacuum may be used. By selecting the conditions of this heat treatment, the heat treatment can be made flat so that an atomic step is locally exposed.

When the first substrate after the transfer of the non-porous material is repeatedly used as the first substrate, the first substrate is reused as many times as possible until it becomes unusable in terms of strength. It is possible to

Since the first substrate is kept intact without being made porous except for the surface layer, both surfaces of the first substrate are both main surfaces, and a supporting substrate is bonded to each surface. Thus, two bonded SOI substrates can be simultaneously manufactured from one first substrate, so that the number of steps can be reduced and productivity can be improved. Of course, the separated first substrate can be reused.

The substrate thus obtained can be used for manufacturing a large-scale integrated circuit having an SOI structure, even when an expensive SOS or SIM is used.
It can be an alternative to OX.

As the second substrate, for example, a Si substrate, S
There is an i-substrate in which an Si oxide film is formed. Alternatively, a light-transmitting insulating substrate such as quartz, fused silica, silica glass, glass, and sapphire may be used, or a metal substrate may be used, and there is no particular limitation.

An embodiment of the present invention will be described with reference to FIG.

As shown in FIG. 2A, a first Si single crystal substrate 11 was prepared, and a first porous layer 12 having a low porosity and a first porous layer 12 having a high porosity were formed on the main surface from the surface side. 2 porous layer 13
To form a porous region composed of at least two layers. Layer 13 comprises at least one layer. Porous Si is
It can be formed by anodizing a Si substrate in an HF solution. The thickness of the low porosity thin layer is as described above. On the other hand, the high porosity layer, which is the second porous layer, has a higher porosity than the low porosity thin layer, and further has a third porous layer below the high porosity layer. Preferably, the porosity of the second porous layer is higher than that of the third porous layer. In other words, the porosity of the second porous layer desirably has the highest porosity in the porous region. The thickness of the second porous layer is as described above.

As shown in FIG. 2B, the porous region 1
At least one non-porous layer 14 is formed on 2 and 13. The non-porous layer 14 is selected from the above-described materials, and specifically includes single crystal Si, polycrystalline Si, amorphous Si, a metal film, a compound semiconductor thin film, a superconducting thin film, and the like. An element structure such as a MOSFET may be formed on the non-porous layer. In the case of a multi-layer structure, SO having a buried layer
It becomes I. Further, forming the insulating film 15 such as SiO _{2 on the} outermost surface layer may mean that the interface state of the bonding interface can be separated from the active layer.

Then, as shown in FIG. 2C, the second
The surface of the substrate 16 is brought into close contact with the surface of the first substrate at room temperature.

FIG. 2C shows a state in which the second substrate and the first substrate are bonded together with the insulating layer 15 interposed therebetween. 2
When the substrate is not Si, the insulating layer 15 may not be provided.

At the time of bonding, it is also possible to sandwich three thin insulating plates and to bond them together.

Next, as shown in FIG. 2D, the substrate is separated by the thinnest layer on the outermost surface of the second porous layer 13 on the first porous layer 12 side. As a method of separating, a method of applying external pressure by pressurizing, pulling, shearing, wedge, etc., a method of applying ultrasonic waves, a method of applying heat, an internal pressure is expanded by expanding the porous region from the periphery by oxidation, , A method of heating in a pulsed manner and applying a thermal stress, a method of softening, and the like, but are not limited thereto.

Subsequently, the first substrate is brought into contact with the surface on the second substrate side.
Of the remaining portion of the porous layer 14 is subjected to a non-porous action to smooth the surface. The smoothing process is as described above.

As a result, a semiconductor substrate as shown in FIG. 2E is obtained. Non-porous layer 1 on second substrate 16
4. For example, a single-crystal Si thin film is flattened and uniformly thinned, and formed over a large area over the entire wafer. When the second substrate and the first substrate are bonded to each other with the insulating layer 15 interposed therebetween, a semiconductor substrate suitable for manufacturing an insulated and separated electronic element is obtained.

The first Si single crystal substrate 11 corresponds to FIG.
If the remaining portion of the second porous layer is unnecessary as described above, the remaining portion is removed, and if the surface smoothness is unacceptably rough, the surface is smoothed, and then the first substrate 11, Alternatively, the semiconductor device may be used as the second substrate 16 and the process shown in FIG. 2 may be repeated to form another semiconductor substrate.

By using the steps shown in FIGS. 1 and 2 using two second substrates, a process for producing a substrate can be performed on both surfaces of the first substrate, and two semiconductor substrates can be produced simultaneously. This is shown in FIG. The first substrate 11 removes the residual porous layer 13 on both surfaces if unnecessary, performs surface smoothing if the surface flatness is unacceptably rough, and then performs the first step again. It can be used as the substrate 11. Alternatively, it can be used as one of the two second substrates 16.

The size and material of the two support substrates 16 need not be the same.

The size and material of the two non-porous layers 14 need not be the same.

The insulating layer 15 need not be provided.

Since the conventional method of manufacturing a bonded substrate uses a method in which the first Si substrate is sequentially removed from one surface by grinding or etching, both surfaces of the first Si substrate are effectively used as a support substrate. It is impossible to attach. However, according to the above embodiment, since the first Si substrate is kept as it is except for the surface layer, the first S
By bonding both sides of the i-substrate as main surfaces and bonding a support substrate to each of the surfaces, two bonded substrates can be simultaneously manufactured from one first Si substrate, so that the process is shortened. , And productivity can be improved.
Of course, the separated first Si substrate can be reused.

For example, in the case of silicon, the Si substrate is made porous, and then heat-treated at a temperature equal to or lower than the melting point, so that the surface layer of the porous silicon substrate becomes a non-porous silicon single crystal layer. A silicon single crystal layer having good crystallinity can be formed on the surface of a porous silicon substrate without using a silicon-containing source gas such as silane.

FIG. 4 schematically shows the steps of forming the first porous layer and the second porous layer, the step of forming the non-porous layer, and the state of the porous region in the separation step according to the present invention. Show.

FIG. 4A shows that a low porosity layer 12a having a hole P1 and a high porosity second porous layer 13 having a hole P2 having a larger diameter than the hole P1 are formed on the surface of the substrate 11. The state in which it is formed is schematically shown.

FIG. 4B shows a state in which the nonporous layer 14 is formed as a nonporous layer forming step by making the surface portion of the low porosity layer 12a nonporous by heat treatment. This is schematically shown. That is, the second surface of the substrate 11
Porous layer 13, first porous layer 12, non-porous layer 14
Is a laminate.

FIG. 4C schematically shows the state after separation, in which the first porous layer 12 and the second porous layer 13 are separated.
This shows a state in which the interface portion of the second porous layer on the interface if side with the substrate is collapsed and separated.

FIG. 4 is a schematic view for facilitating the understanding of the present invention, but the shape of the pores of the porous layer and the shape of the separated surface are often more complicated.

After the non-porous step (b), the thickness of the non-porous layer 14 may be increased by epitaxial growth or the like.

[0109]

【Example】

Example 1 The surface layer of the first single crystal Si substrate was anodized in an HF solution.

The anodizing conditions were as follows.

Current density: 7 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: t (min) Thickness of porous Si: x (μm) Further, current density: 50 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 10 (sec) Thickness of porous Si: 0.2 (Μm) The first anodization time t was set such that the first low porosity porous layer thickness x was 0, 0.2, 0.5, 1.0, 1.5 μm.
The test was performed by changing the values to 0, 0.2, 0.5, 1.0, and 1.5 min.

By this anodization at a current density of 50 mA · cm ⁻² , the porosity of the second porous Si layer was increased, and a structurally brittle high-porosity thin layer was formed.

After placing this wafer in an epitaxial apparatus, it was placed in hydrogen and baked at 1060 ° C. In this state, a sample was taken out and observed with a scanning electron microscope, and it was confirmed that the surface pores of the porous Si were sealed.
As a result, the outermost layer of the low porosity thin layer was consumed to fill the pores and became non-porous. In particular, the low-porosity layer was formed to a predetermined thickness of 1.0 μm or less, and then the surface layer was made nonporous, and the thickness of the remaining low-porosity layer became 0.5 μm or less. . Subsequently, C on porous Si
VD (Chemical Vapor Deposit)
Single-crystal Si was epitaxially grown to 0.3 μm by the (ion) method. The growth conditions are as follows.

Source gas: SiH ₂ Cl ₂ / H ₂ gas flow rate: 0.2 / 180 l / min Gas pressure: 760 Torr Temperature: 1060 ° C. Growth rate: 0.15 μm / min Further, the surface of this epitaxial Si layer A 200 nm SiO ₂ layer was formed by thermal oxidation.

After the surface of the SiO ₂ layer was superimposed on and contacted with the surface of a separately prepared Si substrate (second substrate),
After annealing at 1180 ° C. for 5 minutes, the bonding became strong.

When the bonded wafer was separated,
Near the interface between the high and low porosity layers in the porosity layer
Cracked. It is possible to separate in any of these ways
Was. Subsequently, the substrate is placed in a hydrogen atmosphere at normal pressure,
Heat treatment was performed at 1100 ° C. for 4 hours. As a result, the second
All low-porosity thin layers remaining on the substrate are made non-porous
Was done. The cross section remains when observed with an electron microscope
No cavities or the like could be confirmed. Atomic force microscope for surface roughness
The average square roughness in a 50 μm square area
Indicates that the thickness of the low porosity layer is 0, 0.2, 0.5, 1.0, 1.5 μm.
About 0.5, 0.2, 0.2, 0.4, 1.5 nm, respectively, 1.0
The surface roughness for low porosity thin layers less than μm thick is
It was equivalent to a commercially available Si wafer. Likewise
When the crystal defect density was measured, the stacking fault density was low.
For each thickness of 0, 0.2, 0.5, 1.0, 1.5μm
About 1 × 10^Five, 6 × 10^Three, 5 × 10^Three, 5 × 10^Three, 5 × 10^Three/
cm ^TwoIntroduce crystal defects by introducing a low porosity thin layer
Density dropped dramatically.

In this manner, a single crystal Si layer having a low defect density was formed on the Si oxide film. When the film thickness of the formed single crystal Si layer was measured at 100 points on the entire surface in the plane, the uniformity of the film thickness was 211 nm ± 4 nm and 412 nm ± 4, respectively.
9 nm, 690 nm ± 14 nm, 1201 nm ± 24 n
m, 1707 nm ± 34 nm. This single crystal S
The i-layer has a different thickness because it also includes a nonporous portion of the low porosity layer.

Roughness remaining on the first Si substrate side is subjected to a surface treatment such as hydrogen annealing or surface polishing to perform a surface smoothing treatment, and then used again as the first substrate or the second substrate.
Could be used as a substrate. At this time, the porous S
If a relatively large amount of i remains, selective etching is performed in advance while stirring with a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide, followed by surface treatment such as hydrogen annealing or surface polishing. Can be used again as the first substrate or the second substrate.

Example 2 The surface layer of the first single crystal Si wafer was anodized in an HF solution.

The anodizing conditions were as follows.

Current density: 7 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 0.1 (min) First porous Si Layer thickness: 0.1 (μm) Further, current density: 50 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 5 (sec) Thickness of porous Si layer 2: 0.1 (μm) Further, a third layer may be formed. Conditions are, for example, current density: 7 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 1 (min) Thickness of third porous layer Si : 1 (μm) By this anodization, the porosity of the porous Si layer at 50 (mA · cm ⁻² ) becomes the largest in the porous region,
A structurally brittle high porosity layer formed below the low porosity lamina.

This wafer was oxidized in an oxygen atmosphere at 400 ° C. for 1 hour. Due to this oxidation, the inner wall of the porous Si hole was covered with the thermal oxide film. This wafer was placed in a 1% aqueous HF solution for 3 hours.
By immersion for about 0 seconds, the ultra-thin thermal oxide film formed on the porous surface and the inner wall of the hole near the surface was removed. After placing this wafer in an ultra-high vacuum apparatus, 1 × 10 ⁻⁹ Torr
And baked at 1000 ° C. for 5 minutes. In this state, a sample was taken out and observed with a scanning electron microscope. As a result, it was confirmed that the surface pores of the porous Si were sealed. As a result, the outermost layer of the low porosity thin layer was consumed to fill the pores and became non-porous. This substrate was set in an epitaxial growth apparatus, and single-crystal Si was epitaxially grown on porous Si by 1.0 μm by CVD. The growth conditions are as follows.

Source gas: SiH ₂ Cl ₂ / H ₂ gas flow rate: 0.4 / 180 l / min Gas pressure: 80 Torr Temperature: 900 ° C. Growth rate: 0.15 μm / min Further, the surface of this epitaxial Si layer A 200 nm SiO ₂ layer was formed by thermal oxidation.

After the surface of the SiO ₂ layer was superimposed on and contacted with the surface of a separately prepared Si substrate (second substrate),
After annealing at 1100 ° C. for 10 minutes, the bonding became strong.

When the bonded wafer was separated, 3
The formation current density of the layer is 7 mA / cm ^TwoAnd the second layer
Between the first porous layer and the second porous layer of the high porosity layer of FIG.
Split near the plane. That is, the porosity of the second layer is
When the porosity was the highest in the porous layer structure, it was easy to split. pull
Subsequently, the second substrate is placed in a hydrogen atmosphere under a pressure of 50 Torr.
The plate was placed and heat treated at 1100 ° C. for 2 hours. That
As a result, the transferred epitaxial Si layer on the second substrate
All low-porosity thin layers remaining on the surface are made non-porous
Was. When the cross section was observed with an electron microscope, the remaining cavities
Etc. could not be confirmed. Evaluate surface roughness with an atomic force microscope
As a result, the mean square roughness in the area of 50 μm square was
At about 0.3 nm, the surface roughness is usually S
It was equivalent to i wafer. Measure the crystal defect density in the same way
As a result, the stacking fault density was 5 × 10^Three/ Cm^TwoAnd low
Crystal defect density is drastically reduced by introducing a thin porosity layer.
Was.

As a result, a single crystal Si layer having a low defect density was formed on the Si oxide film of the second substrate. When the film thickness of the formed single crystal Si layer was measured at 100 points over the entire surface, the uniformity of the film thickness was 1011 nm ± 22.
nm.

The oxide film is not on the surface of the epitaxial layer,
The same result was obtained whether it was formed on the surface of the second substrate or on both.

The porous Si remaining on the surface of the second substrate
Was selectively etched while stirring with a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide solution. After that, a surface treatment such as hydrogen annealing is performed, and the surface is again used as the first substrate or the second substrate.
It can be used as a substrate.

Example 3 The surface layer of the first single crystal Si substrate was anodized in an HF solution.

The anodizing conditions were as follows.

Current density: 7 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 3 (min) Thickness of porous Si: 3 (μm) This substrate was oxidized at 400 ° C. for 1 hour in an oxygen atmosphere. Due to this oxidation, the inner wall of the porous Si hole was covered with the thermal oxide film. Ion implantation was performed so that the projection range from the wafer surface was in porous Si and near 0.3 μm from the surface. The element to be ion-implanted is not limited, and it suffices that an implantation damage layer, a high concentration layer (strain layer) of the implanted element, or a bubble layer is formed near the interface.

Single-crystal Si is formed on porous Si by CVD.
Was epitaxially grown by 0.15 μm. The growth conditions are as follows.

Source gas: SiH ₂ Cl ₂ / H ₂ gas flow rate: 0.5 / 180 l / min Gas pressure: 80 Torr Temperature: 900 ° C. Growth rate: 0.15 μm / min Further, the surface of this epitaxial Si layer Then, a 100 nm SiO ₂ layer was formed by thermal oxidation.

When the surface of the SiO ₂ layer and the surface of a separately prepared Si substrate (second substrate) were overlapped and brought into contact with each other and then annealed, the bonding became strong.
Annealing conditions are such that the implant damage layer, the high concentration layer (strain layer) of the implant element or the bubble layer does not diffuse. When the cross section in this state was observed with an electron microscope, it was confirmed that the porosity of the porous material at the ion-implanted position was increased. That is, a high porosity layer to be a separation layer later was formed by ion implantation.

When the bonded wafer was separated, it was divided by a high porosity layer formed by ion implantation.

Subsequently, the second substrate was placed in an atmosphere in which H ₂ was diluted with Ar, and heat treatment was performed at 1200 ° C. for 2 hours. As a result, the transferred single-crystal Si
Any low porosity thin layers remaining on the layer were rendered non-porous. Observation of the cross section with an electron microscope revealed no remaining cavities or the like. When the surface roughness was evaluated with an atomic force microscope, the mean square roughness in a 50 μm square region was about 0.3 nm, and the surface roughness was S which is usually commercially available.
It was equivalent to i wafer. When the crystal defect density was measured similarly, the stacking fault density was 6 × 10 ³ / cm ² , and the crystal defect density was drastically reduced by introducing a low-porosity thin layer.

As a result, a single crystal Si layer having a low defect density was formed on the Si oxide film. When the film thickness of the formed single crystal Si layer was measured at 100 points over the entire in-plane surface, the film thickness uniformity was 311 nm ± 6.2 nm.

Polycrystalline Si remaining on the surface of the first substrate
Was selectively etched while stirring with a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide solution. Thereafter, the surface treatment of hydrogen annealing was performed on the first substrate so that the substrate could be used again as the first substrate or the second substrate.

Example 4 Boron was previously diffused into the surface of the first p ^- single crystal Si substrate to make the p ⁺ layer approximately 0.2 μm
It was formed in thickness.

Subsequently, the surface layer of the substrate was anodized in an HF solution.

The anodizing conditions were as follows.

Current density: 7 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 2 (min) This substrate was observed with a scanning electron microscope. As a result, a layer having a porosity of 20% was formed on the surface to a thickness of about 0.2 μm, and a porous layer having a porosity of 50% was formed under the layer to a thickness of about 0.4 μm.

This substrate was placed in an oxygen atmosphere at 400 ° C. for one hour.
Oxidized. Due to this oxidation, the inner wall of the porous Si
Covered with oxide film. This wafer was put in the epitaxy equipment
Thereafter, the substrate is baked at 1060 ° C. for 5 minutes in hydrogen,
By baking while supplying a small amount of sauce,
The surface pores of the porous Si were filled. Porous Si filled with surface pores
A single crystal Si is formed on the p-epitaxial layer by the CVD method.
Is 0.45 μm, n ⁺1.0 μm epitaxial layer
It was epitaxially grown. The growth conditions are as follows
You.

Source gas: SiH ₂ Cl ₂ / H ₂ gas flow rate: 0.5 / 180 l / min Gas pressure: 80 Torr Temperature: 900 ° C. Growth rate: 0.15 μm / min Further, the surface of this epitaxial Si layer Then, a 100 nm SiO ₂ layer was formed by thermal oxidation.

The surface of the Si substrate (second substrate) prepared separately from the surface of the SiO ₂ layer was treated with O ₂ plasma, washed with water, superposed, brought into contact, and then heated at 400 ° C. for 60 hours.
After annealing for a minute, the bonding became strong.

When the bonded wafer was separated, the wafer was divided into high porosity layers near the interface with the low porosity layer.

Subsequently, the second substrate was placed in an ultra-high vacuum apparatus from which residual oxygen and moisture were sufficiently removed, and 1 × 10 ^-9
Heat treatment was performed at 950 ° C. for 4 hours under a pressure of Torr.
As a result, all the low porosity thin layers remaining on the second substrate were made nonporous. Observation of the cross section with an electron microscope revealed no remaining cavities or the like. When the surface roughness was evaluated with an atomic force microscope, the mean square roughness in a 50 μm square region was about 0.5 nm, and the surface roughness was equivalent to that of a commercially available Si wafer. Similarly, when the crystal defect density was measured, the stacking fault density was 6 × 10 ³
/ Cm ² , the crystal defect density was drastically reduced by introducing a low porosity thin layer.

As a result, a single crystal S having a thickness of 1.6 μm including an n ⁺ buried layer was formed on the Si oxide film of the second substrate.
An i-layer was formed. When the film thickness of the formed single crystal Si layer was measured at 100 points on the entire surface in the plane, the uniformity of the film thickness was 1.6 μm ± 0.03 μm.

The rough surface remaining on the first substrate side was subjected to a surface treatment of hydrogen annealing and a surface flattening treatment, and then used again as the first substrate or the second substrate. If porous Si remains, it is selectively etched while stirring with a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide, and then subjected to a surface treatment such as hydrogen annealing or surface polishing. For example, it can be loaded again as the first substrate or as the second substrate.

Example 5 The surface layer of the first single crystal Si substrate was anodized in an HF solution.

The anodizing conditions were as follows.

Current density: 7 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 0.1 (min) Thickness of porous Si: 0 .1 (μm) Subsequently, anodization was performed by changing the concentration of the solution as described below.

Current density: 7 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 2: 1 Time: 1 (min) Thickness of porous Si: 0.6 (Μm) Observation of this substrate with a scanning electron microscope revealed that a high porosity layer corresponding to the second chemical formation was formed at a depth of about 0.1 μm from the surface.

This substrate was oxidized in an oxygen atmosphere at 400 ° C. for 1 hour. Due to this oxidation, the inner wall of the porous Si hole was covered with the thermal oxide film. The oxide film near the surface of the porous Si was removed by HF. After placing the wafer in an epitaxy apparatus, the wafer was baked in hydrogen at 1040 ° C. for 5 minutes to obtain porous Si.
Surface pores were filled. M on the porous Si filled with surface pores
OCVD (Metal Organic Chemical Vapor Depositio
Single-crystal GaAs was epitaxially grown to 0.5 μm by the n) method. The growth conditions are as follows.

Source gas: TMG / AsH ₃ / H ₂ Gas pressure: 80 Torr Temperature: 700 ° C. After the surface of the GaAs layer and the surface of a separately prepared Si substrate (second substrate) are overlapped and contacted After annealing at 700 ° C. for 1 hour, the bonding became strong.

When the bonded wafer was separated, it was divided into high porosity layers near the interface on the low porosity layer side.

As a result, 0.5 μm was deposited on the second Si substrate.
A single-crystal GaAs layer having a thickness of m was formed. The thickness of the formed single crystal GaAs layer is set to 10
When the zero point was measured, the uniformity of the film thickness was 0.5 μm ±
It was 0.01 μm.

The surface of the GaAs layer was rough, and there was a possibility that the porous Si remained. Therefore, surface touch polishing was performed. As a result, surface smoothness equivalent to that of a commercially available GaAs wafer was obtained.

As a result of observation of a cross section by a transmission electron microscope, S
No new crystal defects were introduced into the i-layer, and it was confirmed that good crystallinity was maintained.

As the second substrate, a Si substrate having an oxidized surface can be used instead of the Si substrate. Also,
After a deposited SiO ₂ film is formed on the surface of the Si substrate or the GaAs layer, it may be bonded. In this case, the resulting substrate is used as GaAs on an insulating substrate.

If the surface remaining on the first substrate is subjected to a surface treatment such as hydrogen annealing or surface polishing and the surface is flattened, it can be used again as the first substrate or the second substrate. Can be. If porous Si remains, it may be selectively etched while stirring with a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide, and then surface treatment such as hydrogen annealing or surface polishing is performed. And can be used again as a first substrate or as a second substrate.

Example 6 The surface layer of the first single crystal Si substrate was anodized in an HF solution.

The anodizing conditions were as follows.

Current density: 7 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 0.2 (min) Thickness of porous Si: 0 0.2 (μm) Further, current density: 50 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 10 (sec) Thickness of porous Si : 0.2 (μm) By this anodization, the porosity of the porous Si layer at 50 (mA · cm ⁻² ) was increased, and a structurally fragile high-porosity thin layer was formed.

After placing this wafer in the epitaxy apparatus,
Bake in hydrogen at 1060 ° C. for 5 minutes. In this state, a sample was taken out and observed with a scanning electron microscope. As a result, it was confirmed that the surface pores of the porous Si were sealed. As a result, the outermost surface of the low porosity thin layer was consumed to fill the pores and became non-porous. Subsequently, 0.3 μm of single-crystal Si was epitaxially grown on the porous Si by CVD. The growth conditions are as follows.

Source gas: SiH ₂ Cl ₂ / H ₂ gas flow rate: 0.2 / 180 l / min Gas pressure: 760 Torr Temperature: 1060 ° C. Growth rate: 0.15 μm / min Further, the surface of this epitaxial Si layer A 200 nm SiO ₂ layer was formed by thermal oxidation.

The surface of the quartz substrate (second substrate) prepared separately from the surface of the SiO ₂ layer was treated with N ₂ plasma, washed with water, superposed and brought into contact, and then heated at 400 ° C. for 60 hours.
After annealing for a minute, the bonding became strong.

When the bonded wafer was separated, it was divided into high porosity layers near the interface with the low porosity layer. Subsequently, the second substrate was placed in a hydrogen atmosphere of 80 Torr, and heat treatment was performed at 950 ° C. for 6 hours. As a result, the second
All the low porosity thin layers remaining on the substrate were made nonporous. Observation of the cross section with an electron microscope revealed no remaining cavities or the like. When the surface roughness was evaluated with an atomic force microscope, the mean square roughness in a 50 μm square region was 0.4 nm, and the surface roughness was usually obtained from commercially available Si.
It was equivalent to a wafer. Similarly, when the crystal defect density was measured, the stacking fault density was 5 × 10 ³ / cm ² .

As a result, a single crystal Si layer having a low defect density was formed on the Si oxide film of the second substrate. When the film thickness of the formed single crystal Si layer was measured at 100 points over the entire surface, the uniformity of the film thickness was 412 nm ± 9 nm.
Met.

The roughness remaining on the first substrate side is subjected to a surface treatment such as hydrogen annealing or surface polishing to smooth the surface, and then used again as the first substrate or the second substrate. be able to. If porous Si remains, it is selectively etched while being stirred with a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide, and then subjected to a surface treatment such as hydrogen annealing or surface polishing. It could be used again as a first substrate or as a second substrate.

Example 7 The surface layer of the first single crystal Si substrate was anodized in an HF solution.

The anodizing conditions were as follows.

Current density: 1 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 2 (min) Thickness of porous Si: 0.4 (Μm) Further, current density: 50 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1: 1 Time: 5 (sec) Thickness of porous Si: 0 .1 (μm) Further, a third layer may be formed. Conditions are, for example, current density: 7 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 1 (min) Thickness of porous Si: 1 (μm) By the anodization, the porosity of the porous Si layer was increased by 50 (mA · cm ⁻² ), and a structurally fragile high porosity layer was formed.

This substrate was oxidized in an oxygen atmosphere at 400 ° C. for 1 hour. Due to this oxidation, the inner wall of the porous Si hole was covered with the thermal oxide film. After placing the wafer in a hydrogen baking apparatus, the wafer was baked in hydrogen at 1040 ° C. for 5 minutes to form a porous Si wafer.
Surface pores were filled. As a result, a low porosity thin layer (1 mA
The portion near the surface of the layer (formed at cm ⁻² ) was consumed to fill the pores and became non-porous. That is, a good quality non-porous single crystal layer was formed with a thickness of about 0.05 μm.

Further, a 20 nm SiO ₂ layer was formed on the surface of the non-porous single crystal layer by thermal oxidation.

When the surface of the SiO ₂ layer and the surface of a separately prepared Si substrate (second substrate) were overlapped and brought into contact with each other, and then annealed at 1180 ° C. for 5 minutes, the bonding became strong.

When the bonded wafer was separated, it was divided into high porosity layers near the interface on the low porosity layer side.

Subsequently, the substrate was placed in a hydrogen atmosphere of 80 Torr and subjected to a heat treatment at 1100 ° C. for 6 hours. As a result, the low porosity layer remaining on the surface of the second substrate was all made nonporous and single crystal silicon Layer. When the surface roughness was evaluated by an atomic force microscope, the mean square roughness in a 50 μm square region was 0.4 nm, and the surface roughness was equivalent to that of a commercially available Si wafer.

As a result, a single-crystal Si layer having a thickness of 400 nm was formed on the Si oxide film. When the thickness of the formed single-crystal Si layer was measured at 100 points over the entire surface, the uniformity of the film thickness was 403 nm ± 8 nm.

As a result of observation of a cross section by a transmission electron microscope, S
No new crystal defects were introduced into the i-layer, and it was confirmed that good crystallinity was maintained.

The roughness remaining on the first substrate side is subjected to a surface treatment such as hydrogen annealing or surface polishing to make the surface flat, and then used again as the first substrate or the second substrate. Can be. If porous Si remains, it is selectively etched while stirring with a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide, and then subjected to a surface treatment such as hydrogen annealing or surface polishing. First again
Or as a second substrate.

As shown in the figure, the method of each embodiment described above can be carried out on both surfaces of the first substrate.

In each embodiment, the following selective etching solution may be used to remove the porous Si layer remaining on the first substrate side after the separation of the bonded substrate.

Hydrofluoric acid, hydrofluoric acid + hydrogen peroxide water hydrofluoric acid + alcohol hydrofluoric acid + alcohol + hydrogen peroxide buffered hydrofluoric acid, buffered hydrofluoric acid + hydrogen peroxide buffered hydrofluoric acid + alcohol buffered hydrofluoric acid + Alcohol + Hydrogen peroxide solution Even if a general Si etchant is used, selective etching can be performed to some extent due to the huge surface area of porous Si.

According to each of the above embodiments, it is not necessary to use a selective etching step, so that not only the effect of the step reduction but also the film due to the excessive etching of the non-porous layer which occurs when the etching selectivity is not sufficient. Problems such as deterioration in thickness uniformity hardly occur, and uniformity of the film transferred to the second substrate does not deteriorate at all.

According to each embodiment, the wafer is separated over the entire surface of the wafer in the interface between the high porosity layer and the low porosity layer in the porous layer region over a large area or in the high porosity layer near the interface. You can do it. For this reason, after the separation, the remaining low-porosity thin layer on the second substrate side may be smoothed, and a removal step of the remaining layer of the porous layer by grinding, polishing, etching or the like is shortened or omitted. I can do it. Further, the thickness of the residual layer can be controlled by the conditions for forming the porous layer structure. In particular, if heat treatment is performed, the remaining low-porosity thin layer can be made non-porous by the heat treatment step without leaving voids therein, and the surface can be smoothed. Thus, the film thickness uniformity can be improved. This means that a wafer can be manufactured with a high yield even for a demand for ultra-high uniformity.

When the separated first substrate is used again as the first substrate in the next SOI substrate manufacturing cycle, the first substrate is reused as many times as possible until it becomes unusable in terms of strength. It is possible to

In the case where the layers in contact with the low-porosity thin layer structure in the porous layer structure and the non-porous layer structure are both epitaxial layers, the thickness of the first substrate can be increased even if it is used many times. Since it can be reused semi-permanently without reducing its quality, in addition to the above-mentioned high quality, there are great merits in resource saving and cost.

It is known that a defect is introduced into the interface or the epitaxial layer due to a difference in lattice constant due to a difference in heteroepitaxy material. Furthermore, in the case of double heteroepitaxy, if one of them is an ultra-thin film due to the relationship between the thicknesses of the two, defects are likely to be introduced on that side. Therefore, when a heterogeneous material is further epitaxially grown on the ultra-thin epitaxial layer, defects are introduced into the ultra-thin epitaxial layer. As described above, the interface becomes weak due to the difference between the lattice constants and the introduction of defects, and the interface is peeled off from the interface.

[0190]

According to the present invention, the step of selectively etching the porous layer can be omitted or shortened, and even when a large-scale integrated circuit having an SOI structure is manufactured, expensive SOS or S
An inexpensive and high-quality method for manufacturing a semiconductor substrate which can be substituted for IMOX can be provided.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view for explaining a manufacturing process of a semiconductor substrate according to the present invention.

FIG. 2 is a schematic cross-sectional view for explaining another example of a manufacturing process of a semiconductor substrate according to the present invention.

FIG. 3 is a schematic cross-sectional view for explaining another semiconductor substrate manufacturing process of the present invention.

FIG. 4 is a schematic cross-sectional view showing a nonporous process.

FIG. 5 is a schematic cross-sectional view for explaining a process of a first conventional example.

FIG. 6 is a schematic cross-sectional view for explaining a process of a second conventional example.

[Explanation of symbols]

Reference Signs List 1 Porous region 2 Substrate 3 Second substrate 11 Substrate 12 Low porosity thin layer 13 High porosity layer 14 Non-porous layer 15 Second layer structure or layer formed on surface of second substrate 16 Second Substrate 31 Substrate 32 Porous layer 33 Non-porous single crystal layer 34 Support substrate 35 Insulating layer 41 Substrate 42 Porous 43 Non-porous single crystal layer 44 Support substrate 45 Insulating layer

Claims (40)

[Claims] Providing a first substrate having a porous region including at least two layers having different porosity and a non-porous layer on the porous region; Laminating the surface of the porous layer and the surface of the second base, separating the first and second bases, and transferring the non-porous layer to the second base; Removing the remaining portion of the porous region remaining on the separation surface of the second substrate or making it non-porous to smooth the separation surface. The step of preparing the first substrate includes: A first porous layer having a thickness of 1 μm or less, a second porous layer adjacent to the first porous layer and having a high porosity, and the non-porous layer adjacent to the first porous layer. And a step of forming a semiconductor layer. 2. The method according to claim 1, wherein the step of forming the non-porous layer comprises:
2. The method of manufacturing a semiconductor substrate according to claim 1, further comprising: a step of making the surface-side portion of the porous layer nonporous; and / or a step of forming a nonporous layer on the first porous layer. . 3. The step of forming the first porous layer,
2. The method for manufacturing a semiconductor substrate according to claim 1, wherein after forming the porous layer, a portion on the surface side of the porous layer is made nonporous so that the thickness of the remaining porous layer is 1 μm or less. 4. The method according to claim 1, wherein the thickness of the second porous layer is larger than that of the first porous layer. 5. After forming a second porous layer thinner than the first porous layer, a surface portion of the first porous layer is made non-porous to form the first porous layer. The method for manufacturing a semiconductor substrate according to claim 1, wherein the thickness of the layer is reduced. 6. A third porous layer, which is thicker and less porous than the second porous layer, is formed on the second porous layer on the side opposite to the first porous layer. 2. The method for manufacturing a semiconductor substrate according to claim 1, comprising a step. 7. The method according to claim 1, wherein the step of smoothing the separation surface is performed by heat treatment in a non-oxidizing atmosphere without using any of selective etching and polishing. 8. The method according to claim 6, wherein the non-oxidizing atmosphere is hydrogen, an inert gas, or a mixed atmosphere thereof. 9. The method according to claim 1, wherein the step of smoothing the separation surface is performed by heat treatment in a vacuum without using either selective etching or polishing. 10. The method according to claim 1, wherein the porous region is made of a single crystal. 11. The method according to claim 1, wherein the porous region is a single-crystal Si layer. 12. The method according to claim 1, wherein the formation of the porous region is performed by anodizing the first substrate. 13. The first porous layer and the second porous layer are formed by anodization, and the type and concentration of impurities in the first base, current density at the time of anodization, chemical composition, and chemical solution. 13. The method for manufacturing a semiconductor substrate according to claim 12, wherein the semiconductor substrate is separately formed according to the temperature or a combination thereof. 14. The method according to claim 1, wherein after forming a porous region on one surface of the first base, the second porous layer is formed at a projected range of ions by ion implantation. A method for manufacturing a semiconductor substrate as described above. 15. Before the formation of the non-porous layer, to the extent that the porous crystal structure remains inside the side walls of the pores of the porous region,
The method for manufacturing a semiconductor substrate according to claim 1, wherein the side wall surface is oxidized. 16. The fabrication of a semiconductor substrate according to claim 15, wherein an oxide film formed on a surface of the porous region and a side wall of a hole near the surface is removed before forming the non-porous layer. Method. 17. The non-porous layer includes a portion in which the surface of the first porous layer has been made non-porous by a heat treatment in a non-oxidizing atmosphere or in a vacuum. 2. The method for manufacturing a semiconductor substrate according to item 1. 18. The non-porous layer includes a portion in which the surface of the first porous layer is made non-porous by a heat treatment in a non-oxidizing atmosphere or in a vacuum, and a surface of the non-porous layer. The method for manufacturing a semiconductor substrate according to claim 1, comprising the formed oxide film. 19. The method for manufacturing a semiconductor substrate according to claim 17, wherein the non-oxidizing atmosphere is an atmosphere of hydrogen, an inert gas, or a mixed gas thereof. 20. The method for manufacturing a semiconductor substrate according to claim 17, wherein the non-oxidizing atmosphere also contains a small amount of Si. 21. The method according to claim 1, wherein the non-porous layer is formed by epitaxy based on a crystal orientation of the first porous layer. 22. The non-porous layer according to claim 1, wherein the non-porous layer comprises a single crystal layer formed by epitaxy based on the crystal orientation of the first porous layer and an oxide film layer thereon. Of manufacturing a semiconductor substrate. 23. The method according to claim 21, wherein the non-porous layer formed by the epitaxy is a single-crystal Si layer. 24. The method according to claim 21, wherein the non-porous layer formed by the epitaxy has a single-crystal compound semiconductor layer. 25. The method according to claim 1, wherein the non-porous layer is formed of a plurality of layers having different electric conductivity types or different impurity concentrations. 26. The method for manufacturing a semiconductor substrate according to claim 1, wherein the separated first substrate is reused. 27. The method according to claim 26, wherein the preprocessing for reuse includes only a smoothing process. 28. The method of manufacturing a semiconductor substrate according to claim 26, wherein the pretreatment for reuse includes removing a remaining portion of a porous region remaining after separation and flattening. 29. The method according to claim 1, wherein the separation step is performed by any one of pressure, pulling, shearing, wedge insertion, heat treatment, oxidation, wave application, and wire cutting, or a combination thereof. A method for manufacturing a semiconductor substrate. 30. The method according to claim 1, wherein the second base is made of Si. 31. The method for manufacturing a semiconductor substrate according to claim 1, wherein the second substrate is made of a Si substrate having a Si oxide film formed on at least a surface to be bonded. 32. The method according to claim 1, wherein the second base is made of a light-transmitting base. 33. The method according to claim 1, wherein the first porous layer has a thickness of 0.5 μm or less. 34. The method according to claim 1, wherein the porosity of the second porous layer is the largest in a porous region. 35. The method according to claim 1, wherein the porous layer region comprises only two layers, a first porous layer and a second porous layer. 36. The method according to claim 1, wherein the second porous layer has a thickness of 1 μm or less. 37. The method according to claim 36, wherein the second porous layer has a thickness of 0.5 μm or less. 38. The method according to claim 1, wherein the porous region has a thickness of 2 μm or less. 39. The step of forming the first porous layer comprises, after forming a porous layer having a thickness of 1 μm or less, making the surface side portion of the porous layer non-porous and forming the remaining porous layer. 2. The method according to claim 1, wherein the thickness of the layer is 0.5 μm or less. 40. A semiconductor substrate manufactured by the method for manufacturing a semiconductor substrate according to claim 1.