JPH10326301A - Lsi test system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely verify the correctness of inter-macro connection in a short time without increasing the circuit scale by applying a simple pattern test signal to a produced net list and then monitoring the test signal. SOLUTION: A circuit to be verified consists of macros A to D and gates 1 and 2, which are connected to each other. A so-called net list showing the inter-macro connection is first produced to verify the correctness of inter-macro connection of the said circuit. The net list can be extracted by replacing each input terminal of macro A to D with the output terminal of a test signal and replacing each output terminal of macro A to D with the input terminal of the test signal respectively. A simple pattern test signal is inputted to each test signal input terminal of the net list, and the test signal is monitored at each test signal output terminal of the net list. In such a system, the correctness of inter-macro connection is verified.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a function confirmation test at the time of designing an LSI, and more particularly to a macro (also referred to as a module or a block) which is hierarchically designed using a hierarchical design technique and whose design is verified. And an LSI test method for confirming the validity of the macro connection.

[0002]

2. Description of the Related Art An LSI hierarchical design method (hierarchical de
As is well known, for example, a method of assembling a logic gate level at the lowest layer to a cell level, assembling this cell level to a macro level, and assembling a macro level to a chip level, A function confirmation test or the like is appropriately performed at the level assembly. One of these tests is a test for confirming the validity of the connection between macros.

As a test method for confirming the validity of the conventional macro indirect connection, there is the following method. A method that uses a test pattern. In this method, the function of the upper layer connected between the macros is verified using a test pattern, and if the upper layer functions normally, the connection between the macros is also correct. A method in which a conventional boundary scan circuit is incorporated in each macro, and the connection between macros is verified using this circuit. The standard specification of the boundary scan circuit is IEEE.
Although stipulated in EE1149.1, for example, as shown in FIG. 5, diagnostic cells (fi) and (fo) each composed of a flip-flop are connected to each input / output terminal unit of the chip, and a diagnostic input terminal is connected. (Cdi) and a diagnostic output terminal (cdo) are provided, diagnostic data is input from a diagnostic input terminal, and the function of the chip is determined by whether or not an output corresponding to the diagnostic data is obtained from the diagnostic output terminal (cdo). However, a method of checking the validity of the connection between the macros by incorporating this boundary scan circuit into each macro is also conceivable.

[0004]

As a conventional LSI test method for verifying the validity of the connection between macros, there is a method using a test pattern as described above, and a method using a boundary scan circuit is also conceivable. At present, as the scale of each module inside the LSI has become larger and the number of connections between macros has increased remarkably, it takes a lot of time to create test patterns. In addition, this test pattern method is complicated to verify,
Verification tests must be performed by someone who has a good understanding of their functions, but they are still time-consuming and not reliable enough.

In the case where a boundary scan circuit is incorporated in each macro, the boundary scan circuit requires cells to take in data by the number of input terminals + output terminals.
Accordingly, there is a problem that the circuit scale of each macro is increased and complicated, and as a result, the price of the provided LSI becomes expensive.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an LSI which can surely verify the validity of the connection between macros in a short period of time without increasing the circuit scale.
It is intended to provide a test method.

[0007]

An LSI test system according to the present invention is an LSI test system for verifying the validity of connection between macros of an LSI composed of a plurality of macros (also referred to as modules and blocks). A means for creating a so-called net list of only a connection between each macro, a test signal having a simple pattern sufficient to verify the validity of the connection is passed through the created net list, and each macro is monitored by monitoring this test signal. A means for verifying the validity of the inter-connection is provided.

In the netlist, each output terminal of each macro is a test signal input terminal, and each input terminal is a test signal output terminal.
Each connection line connected between each test signal input terminal and each test signal output terminal is extracted.

The test signal is a signal of a pattern in which an element is inserted and the logic of the connection line needs to be considered in each of the connection lines, and the logic of the connection signal needs to be considered. For a connection line that does not exist, a signal whose logic is inverted by one pulse interval is used.

The test signal whose logic is inverted by one pulse interval is a signal in which the logic is inverted with a time lag in order to distinguish each signal line. I do.

Further, the test signal whose logic is inverted by one pulse interval is a signal in which the pulse interval at which the logic is inverted is different in order to distinguish each signal line.

[0012] The LSI test system of the present invention employs the above-described LSI test system for verifying the validity of the connection between macros of an LSI composed of a plurality of macros.
The validity of the connection between the macros can be verified very simply, and the creation of a complicated test pattern and the boundary scan circuit are not required.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a circuit (upper macro) to which a plurality of macros to be verified are connected, and FIG. 2 is a diagram for explaining an embodiment of the present invention. As shown in FIG. 1, for example, it is assumed that a circuit to be verified is composed of macros A to D, a gate 1 and a gate 2, and each of them is connected as shown in FIG. LS of the present invention
In the I test method, a so-called netlist indicating the connection between macros is first created in order to verify the validity of the connection between macros of such a circuit.

As shown in FIG. 2, the extraction of the netlist can be easily performed by replacing the input terminals of the macros A to D with test signal output terminals and the output terminals with test signal input terminals. . That is, 1,1 ', 1''~1''''
Is an input terminal of a higher-level macro to which these macros A to D are connected.
Similarly, 2,2 ', 2 "to 2'""are the output terminals of the higher-level macros, so they are directly used as the output terminals of the test signal. Also, 2
A, 2A ', and 2A "are input terminals of the macro A, and thus are test signal output terminals. 1A, 1A' to 1A""are output terminals and are test signal input terminals.

Similarly, 2B, 2B 'to 2B'"are test signal output terminals, 1B, 1B 'to 1B""are test signal input terminals, and 2D, 2B,
2D '~ 2D''''''are test signal output terminals, 1D, 1D' ~ 1
By using D '''as a test signal input terminal, a netlist can be extracted. The macro C is a short-function macro. In such a short-function macro, it is easier to create a test pattern if a test pattern for testing the function is used as it is than to replace a terminal. Since the validity and the function verification can be performed at the same time, the terminal is not replaced.

Next, a test signal of a simple pattern is input to each test signal input terminal of the netlist created in this way, and this test signal is monitored at each test signal output terminal. FIG. 3 is a diagram showing an example of a test signal sent to a netlist. The test signal may be a signal whose logic is inverted by a predetermined pulse width, for example. However, since it is necessary to distinguish each terminal, a test signal as shown in FIG. 3 whose logic is sequentially inverted with a time lag at each terminal or a test signal whose pulse width at which the logic is inverted differs for each terminal (Not shown). The pattern of the test signal given to the gate 1 and the macro C is created in consideration of the logic of the gate and the logic of the macro C, respectively. As described above, the LSI of the present invention
The test method is to create a netlist, input a simple pattern test signal to each test signal input terminal side of the created netlist, and monitor the test signal at the test signal output terminal side. Verification of correctness can be performed very easily.

In the description of the embodiment described with reference to FIG.
The pattern of the test signal to be given to the gate 1 and the macro C is to be created in consideration of the logic of the gate and the logic of the macro C, respectively, as shown in FIG. The above-described verification test may be performed only on the portion where the netlist is created. Verification of the connections between macros not extracted in the netlist can be accurately determined from the connection relationships in the netlist. The function verification is performed as the upper macro where the function verification is not sufficient and the timing etc. needs to be verified between macros. If the path is clearly verified by the higher macro, the connection between macros This is because it may not be necessary to perform the check.

[0018]

As described above, according to the LSI test method of the present invention, a netlist of only a connection portion between macros constituting an LSI is created, so that a simple pattern signal is used as a test signal for connection. Since validity can be verified, reliable verification can be performed in a short period of time as in the case of using a boundary scan circuit. In addition, since a boundary scan circuit is not required, it is possible to prevent an increase in the unit cost of the chip without increasing the circuit scale and complexity, and to eliminate the need for special equipment such as a CAD dedicated to the test. There is.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an upper macro to which a plurality of macros to be verified are connected.

FIG. 2 is a diagram illustrating an embodiment of the present invention.

FIG. 3 is a diagram illustrating an example of a test signal used in the embodiment.

FIG. 4 is a diagram for explaining another example of a netlist extraction method.

FIG. 5 is a diagram illustrating a conventional boundary scan circuit.

[Explanation of symbols]

1,1 ', 1''~1'''', 1B, 1B' ~ 1B '''''', 1D, 1D '~ 1
D '''Test signal input terminal 2,2', 2 '' ~ 2 ''''', 2A, 2A', 2A '', 2B, 2B '~ 2B''', 2
D, 2D '~ 2D''''''Test signal output terminal

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Masahiro Saito 3-18-21 Shibaura, Minato-ku, Tokyo NEC Engineering Co., Ltd.

Claims (5)

[Claims] In an LSI test method for verifying the validity of connection between macros of an LSI composed of a plurality of macros (also referred to as modules or blocks), a so-called netlist of only a connection between macros is determined. Means for creating, a means for passing a test signal of a simple pattern enough to verify the validity of the connection to the created netlist, and means for verifying the validity of the connection between the macros by monitoring the test signal. An LSI test method, characterized in that: 2. The netlist according to claim 1, wherein each output terminal of each macro is a test signal input terminal, each input terminal is a test signal output terminal, and each test signal input terminal is connected to each test signal output terminal. 2. The LSI test method according to claim 1, wherein each connection line connected between the two is extracted. 3. The test signal is a signal of a pattern in which an element is inserted into each of the connection lines and its logic needs to be considered, and the logic of the test signal is considered. 3. The LSI test method according to claim 2, wherein a signal whose logic is inverted by one pulse interval is used for a connection line having no symbol. 4. The test signal whose logic is inverted by one pulse interval is a signal in which the logic is inverted with a time lag in order to distinguish each signal line. 4. The LSI test method according to claim 3, wherein 5. The test signal whose logic is inverted by one pulse interval is a signal in which the pulse interval at which the logic is inverted is different for each of the signal lines. The LSI test method according to claim 3.