JPH1032552A - Data transmitter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To transmit data group recorded in a CD without an error to a receiving point distant from a transmitting point by converting a data group outputted from a CD decoder to a data group added with an error-corrected code based on the PCM voice transmission system of BS broadcasting so as to transmit it. SOLUTION: A received modulation signal is demodulated by a digital demodulator 18 such as QPSK and additionally inputted to a BS decoder 19 to execute generation of a synchronizing signal, the processing of added data and an error correction processing. A packet header, independent data and a data group equivalent to data outputted from the data conversion part 3 of a data sending part 28 are separated from a transmission data group decoded by the BS decoder 19 by a data separation part 16. Data in the separated data group is divided by each bit. A data conversion part 17 converts 32-bit data to 48-bit data, namely the data are converted to a data group equivalent to a D data group outputted from the CD decoder 28 of the data sending part 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission apparatus, and more particularly, to a CD defined by a data format for CD.
When transmitting a data sequence and any independent data sequence,
The present invention relates to a novel data transmission device capable of transmitting transmission data to different places with high quality without errors.

[0002]

2. Description of the Related Art Conventionally, as a data transmission apparatus, there is an audio data transmission apparatus for satellite broadcasting, which has a sampling frequency of 32 kHz, 14 kHz for 4-channel input audio data.
Bit line quantized 1 compressed to 10 bits
4/10 bit quasi-instantaneous companding encoding method (A mode) and 2
Sampling frequency 48k for channel input audio data
The encoding is performed using Hz, 16-bit linear quantization (B mode), and PCM audio transmission and PCM audio broadcasting are performed at a code transmission speed of 2.048 Mbps.

[0003]

In the conventional data transmission apparatus, input data is limited to only voice data and independent data having a low data transmission rate, and the number of quantization bits is one.
6 kHz or 14 bit sampling frequency of 48 kHz
Alternatively, only 2-channel or 4-channel audio signals digitized at 32 kHz and independent data of several hundred Kbps can be transmitted.

An object of the present invention is to provide a data transmission unit,
For the data sequence output from the CD decoder, BS
By converting the data sequence into a data sequence with an error correction code based on the PCM audio transmission system of the broadcast and transmitting the data sequence, an error at the time of data reception is corrected, and a data sequence equivalent to the data sequence output from the original CD decoder is converted. An object of the present invention is to provide a data transmission device capable of transmitting data to a receiving point.

[0005]

In order to solve the above-mentioned problems, a general digital data sequence recorded on a CD, for example, a data length of 48 bits, a word length of 16 bits, and the like.
Word clock 44.1 kHz, bit clock 2.1
A data sequence of 168 MHz is used as an input signal, and a packet header and arbitrary independent data are added. P of signal sending part
In the LL circuit, 2.048 according to the PCM voice transmission system of BS from the bit clock signal of 2.1168 MHz
After generating a clock signal necessary for generating a data sequence of MHz and adding a synchronization signal and an error correction code by a BS encoder, the code transmission rate is 2.048 Mbp.
An s bit stream is generated, modulated by a specific digital modulator, and transmitted.

[0006] The receiving side receives the transmitted modulated signal,
After generating a bit stream having a code transmission rate of 2.048 Mbps based on the BS audio transmission system by a digital demodulator, correcting the error, adding a packet header added from a received data sequence by a transmission unit to a transmission unit by a data separation unit, independent data, and the transmission Separate from the data series.

In order to convert this data sequence into a data sequence equivalent to that output from the CD decoder of the transmission unit, the data conversion unit and a clock signal (2.
With the PLL circuit generating 1168 MHz), it is possible to generate a reception data sequence of 2.1168 Mbps, which is the same as that on the transmission side.

A data transmission apparatus according to the present invention has a data length of 48 bits output from a CD decoder, a word clock of 44.1 kHz, and a bit clock of 2.1168 MHz.
Is used as a data sequence to be input to the data transmission unit, a new transmission data sequence is generated by adding arbitrary independent data and a packet header, an error correction code is added by the PCM audio transmission method of BS broadcasting, and then digital modulation is performed. To the receiving point, the input data is not limited to audio data only,
Digital data such as a program recorded on a CD can be transmitted without error.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the embodiment shown in FIG. The data converter 3 has a general data length of 48 bits as an output interface from the CD decoder 2 and a word clock frequency of 44.1 kHz.
z, a data sequence having a bit clock frequency of 2.1168 MHz is converted into a 32-bit data sequence. In the data multiplexing unit 4, the transmission data sequence for a 10 ms period is 960 words (1 word = 16 bits), the packet header (1 word / 10 ms), independent data (77 words / 10 ms), and the data conversion unit 3. Are multiplexed from each other (882 words / 10 ms). The multiplexed transmission data is encoded by the BS encoder 5 in accordance with the PCM audio data transmission system of the BS, and generates a bit stream having a code transmission rate of 2.048 Mbps to which a frame synchronization signal, a control code, and an error correction code are added. .

[0010] The digital modulator 6 receives the bit stream, performs digital modulation, and transmits it. The digital modulator 6 generally has a four-phase DPSK (differential)
phase shift keying) modulator is used, directly or after transmission frequency conversion is performed,
Sent.

The clock signal required for the data converter 3 is
It can be generated by the PLL circuit 7. The PLL circuit 7 converts the bit synchronization clock signal (2.1168 MHz) output from the CD decoder 2 into 1 /
The frequency is divided by 1323 to generate a 1.6 kHz clock signal, which is input to one input terminal of the phase comparator 9 of the PLL circuit 7 as a reference clock signal.

On the other hand, a bit clock signal (2.048 MHz) necessary for the encoding process of the BS encoder 5 is obtained by first dividing the output signal of the VCXO 13 having a transmission frequency of 16.384 MHz into 1/8 by the frequency divider 12. Can occur. Further, the frequency is divided into 1/1280 by the frequency divider 11 and inputted to the other terminal of the phase comparator 9 at 1.6 kHz.
Is generated. The reference clock signal and the phase comparison clock signal are compared in phase by a phase comparator 9, a DC component is extracted from a phase comparison signal output from the phase comparator 9 by a loop filter 10, and the extracted DC component is input to the VCXO 13. Can be configured. The timing generator 14 of the PLL circuit 7 generates a timing clock required for the data processing.

FIG. 2 is a diagram showing the configuration of the data multiplexing unit 4 and the BS encoder 5 of the transmitting unit of FIG.
Selects data from the data conversion unit 3, packet data from the outside, and independent data based on the timing from the timing generation unit 14. The data selected by the selector 41 is alternately written to the memories 42 and 43 every 10 ms. The memories 42 and 43 have a capacity of 15360 bits, and when one is written, the other is read. 10m written to memory 42, 43
As shown in FIG. 3, the multiplexed signal format for each s is composed of a 1-word packet header, 77-word independent data, and 882-word CCD data. FIG. 4 is a diagram showing the bit synchronization clock BCK and the LR discrimination signal LRCK sent from the CD decoder 2 to the data converter 3 and the timing of writing data and CD data to the memories 42 and 43. The write timing to this memory is 2.1168M
Hz clock, one every 11.35 μs
Write 6-bit data (1 word) to the CD data area.

Referring back to FIG. 2, the BS encoder section 5 is composed of a selector 51, memories 52 and 53 that can be switched between writing and reading alternately, and a scrambler 54.
The memories 52 and 53 have a capacity of 2.048 Mbits, and switching between writing and reading is performed every 1 ms.

Next, the operation of the data receiving section will be described. FIG.
The modulated signal received in is demodulated by a digital demodulation unit 18 such as QPSK and input to a BS decoder 19, where a synchronization signal is generated, additional data is processed, and error correction is performed. For ease of explanation, the BS decoder 1 is used here.
The transmission data sequence decoded in step 9 is a data sequence with a bit synchronization clock frequency of 1.536 MHz.

The packet header (1 word / 10 m) is extracted from the data series of 1.536 Mbps by the data separation section 16.
s), independent data (77 words / 10 ms), and a data sequence (882 words / 10 ms) equivalent to the data output from the data converter 3 of the data transmitter 28. In the separated data series, data is divided every 32 bits. The data conversion unit 17 converts the 32-bit data to 48
Converted to bit data. That is, the data sending unit 28
CD data sequence (48
(Bit, word clock 44.1 kHz, bit clock 2.1168 MHz).

The PLL circuit 20 for operating the data converter 17 is 1.536 MHz output from the BS decoder 19.
The z-bit clock is frequency-divided by the frequency divider 21 into 1/320 to generate a 4.8 kHz signal. This signal is input to one terminal of the phase comparator 22 as a reference signal for phase comparison. In order to generate a bit clock of 2.1168 MHz equivalent to the output of the CD decoder 2 of the data transmission unit 28, the VCXO2 having a transmission frequency of 16.9344 MHz
6, the frequency of the clock signal output from the VCXO 26 is reduced to 1/8 by the frequency divider 25, and
To obtain a clock signal. Further, this clock signal is frequency-divided by the frequency divider 24 to 1/441, and is input to the other terminal of the phase comparator 22 as a 4.8 kHz phase comparison clock signal. By inputting the phase comparison signal output from the phase comparator 22 to the VCXO 26 through a loop filter 23 for extracting a DC component, the PLL circuit 2
0 can be configured. Further, the timing generator 27 of the PLL circuit 20 generates a timing clock necessary for the data processing.

[0018]

The first effect of the present invention is that the transmission data sequence to be processed is not limited to PCM audio data, but JPEG,
CDs for MPEG, MIDI, character information, programs, etc.
The data sequence can be transmitted to a receiving point distant from the transmitting point without data error.

The second effect is PCM defined by BS broadcasting.
Since data transmission is performed according to the audio transmission method, the BS decoder can use a low-cost device for demodulating an audio signal.

The third effect is that when the reading speed of the CD becomes N times (N is an arbitrary integer), the transmission frame configuration conforming to the PCM audio transmission system of the BS broadcast is maintained, and the PL is maintained.
That is, it can be dealt with only by partially changing the L circuit and the digital modulation / demodulation unit.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a data multiplexing unit and a BS encoder in the transmission unit of FIG. 1;

FIG. 3 is an example of multiplexing of transmission data according to the embodiment;

FIG. 4 is a diagram showing a bit synchronization clock, L, in the transmission unit of FIG.
9 is a timing chart showing a relationship between an R determination signal, data, and write timing of a memory of a data multiplexing unit.

[Explanation of symbols]

 Reference Signs List 1 transmission data processing unit 2 CD decoder 3 data conversion unit 4 data multiplexing unit 5 BS encoder 6 digital modulation unit 7 PLL circuit 8 frequency divider (1/1323 frequency divider) 9 phase comparator 10 loop filter 11 frequency divider ( 1/128 frequency divider) 12 frequency divider (1/8 frequency divider) 13 VCXO (16.384 MHz) 14 timing generator 15 received data processor 16 data separator 17 data converter 18 digital demodulator 19 BS decoder Reference Signs List 20 PLL circuit 21 Divider (1/320 divider) 22 Phase comparator 23 Loop filter 24 Divider (1/441 divider) 25 Divider (1/8 divider) 26 VCXO (16 .9344 MHz) 27 Timing generator 28 Data transmitter 29 Data receiver 41,51 Selector 42,43,52,53 Memo Re 54 Scrambler

Claims (3)

[Claims] 1. A data transmission unit, comprising: a CD decoder for decoding a signal read from a compact disk (hereinafter abbreviated as CD); and a transmission data sequence extracted from a data sequence output from the CD decoder. A data multiplexing unit for adding independent data having a specific code length and a packet header to a transmission data sequence output from the data conversion unit to generate a new transmission data sequence; The transmission data series is transmitted by satellite broadcasting (hereinafter referred to as BS
BS encoder section that performs encoding in accordance with a code format conforming to the PCM audio data transmission method, a PLL circuit that generates a system clock required for processing these data, and A data modulating unit that modulates and transmits the data according to the modulation method described above, wherein a data receiving unit receives a modulated signal transmitted from the data transmitting unit and demodulates data, and a demodulation obtained from the data demodulating unit. A BS decoder that decodes a data sequence based on a BS audio signal transmission system, a data separation unit that separates a packet header multiplexed by the data multiplexing unit from independent data and a transmission data sequence, A data conversion unit that converts the data sequence into a data sequence composed of a specific bit length, and a bit synchronization clock and PLL for generating clock and system clock
A data transmission device comprising: a circuit for transmitting and receiving a data sequence recorded on a CD and an independent data sequence. 2. Compact disk (hereinafter abbreviated as CD)
A CD decoder unit for decoding the signal read from the data decoder, a data conversion unit for extracting a transmission data sequence from the data sequence output from the CD decoder unit, and a transmission data sequence output from the data conversion unit. A data multiplexing unit that generates a new transmission data sequence by adding independent data composed of a code length and a packet header, and a PCM audio data transmission system for satellite broadcasting (hereinafter abbreviated as BS) of the multiplexed transmission data sequence. A BS encoder for encoding with a code format conforming to the above, a PLL circuit for generating a system clock required for processing these data, and data for modulating the multiplexed data by a predetermined modulation method and transmitting the data. A data transmission device comprising a modulation unit. 3. A data demodulator for receiving a modulated signal and demodulating data, and a BS decoder for decoding a demodulated data sequence obtained from the data demodulator based on a satellite broadcast (hereinafter abbreviated as BS) audio signal transmission system. A data separating unit for separating the packet header multiplexed by the data multiplexing unit from the independent data and the data sequence for transmission, and data for converting the data sequence for transmission into a data sequence having a specific bit length A data transmission device comprising: a conversion unit; and a PLL circuit that generates a bit synchronization clock and a system clock necessary for processing received data.