JPH1032314A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device, on which minuscule contacts for connecting conductive layers are formed through a diffusion layer and an insulating layer on the surface of a silicon substrate. SOLUTION: Gate electrodes 4 are formed on the surface of a p-type silicon substrate 1 through a gate oxide film 3. A first SiO2 film 5 and side walls 7 are formed on the top and sides of the gate electrodes 4. A Si3 N4 film 14 and a BPSG film 8 are formed on the surface of the first SiO2 film 5 and the side walls 7. The BPSG film 8 is polished by a CMP method until the Si3 N4 film 14 on the gate electrodes 4 is exposed. Then, the BPSG film 8 is eliminated by wet etching with a mask of resist 9 to open an upper contact 10a. The Si3 N4 film 14 is dry-etched with a mask of the resist 9 to open a lower contact 10b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device having a contact hole formed in a self-aligned manner.

[0002]

2. Description of the Related Art It is essential for a memory cell of a dynamic random access memory (DRAM) to have a smaller cell area in order to improve the degree of integration. Regarding photolithography technology, sub-quarter micron resist patterning has become possible in recent years by lithography technology using an excimer laser as a light source or lithography technology using an electron beam.

However, one of the factors that hinder the reduction of the cell area is that the alignment margin of the photolithography technique cannot be easily reduced. Current D
The photolithography technique is used a plurality of times in the RAM manufacturing process. For example, a D having a stacked capacitor having a structure in which the capacitor is located above the bit line
To form a memory cell of a RAM, at least photolithography for forming a gate electrode, forming a bit contact hole, forming a bit line, forming a capacitor contact hole, forming a storage electrode, and forming a counter electrode is performed. is required. When designing a memory cell array, it is necessary to sufficiently consider the alignment margin of photolithography, and it is not possible to simply reduce the memory cell area without increasing the alignment margin. In view of the above circumstances, several techniques for reducing the alignment margin between photolithography have been proposed so far.
Here, attention is paid particularly to a technique for reducing the alignment margin between the gate electrode and the contact hole. Several techniques for reducing the alignment margin between the gate electrode and the contact hole have been proposed. For example, Japanese Patent Application Laid-Open No. 4-106929 discloses a method for manufacturing such a semiconductor device.

FIG. 5 is a cross-sectional view for sequentially explaining main manufacturing steps of a stacked DRAM obtained by the method of manufacturing a semiconductor device described in Japanese Patent Laid-Open No. 4-106929.

[0005] As shown in FIG. 5 (a), a P-type silicon substrate 101 having a thickness of 500
A field oxide film 102 having a thickness of 30 nm is formed.
A gate oxide film 103 having a thickness of 3
00 nm polysilicon film and 300 nm thick SiO ₂
By forming a film, by lithography and etching,
An SiO ₂ film 105 and a gate electrode 104 are formed.

Next, phosphorus ions are implanted into the N-type diffusion layer 11.
3,113a is formed and has a thickness of 300 nm by the CVD method.
The SiO ₂ film is grown and etched back to form a sidewall 1 made of the SiO ₂ film on the gate electrode 104.
07 is formed, and arsenic is ion-implanted to form an N-type diffusion layer 1.
06,106a to obtain LDD fabrication.

Next, as shown in FIG. 5B, a SiO ₂ film 114 having a thickness of 100 nm is grown on the entire surface, contact holes 117 are formed on the N-type diffusion layers 106 and 113, and a thickness of 200 nm is formed. Is grown and selectively etched to obtain a polysilicon film 115.

Next, as shown in FIG. 5C, a 40 nm Si ₃ N ₄ film 112 is grown as a capacitor insulating film on the entire surface, a 200 nm thick polysilicon is grown, and selective etching is performed. To form a polysilicon film 116, and use the PSG film 10 having a thickness of 1.0 μm as an interlayer insulating film.
Grow 8.

Next, as shown in FIG. 5D, the PSG film 108 is etched using the resist 109 as a mask and the Si ₃ N ₄ film 112 as an etching stopper to form a contact hole 110.

Next, as shown in FIGS. 6 (e) and 6 (f),
Si ₃ N ₄ film 112 in contact hole 110 and Si
The O ₂ film 114 is etched, the resist 109 is removed, and the aluminum wiring 111 is formed to complete the memory cell portion.

[0011]

SUMMARY OF THE INVENTION The above-mentioned Japanese Patent Application Laid-Open No. 4-106 is disclosed.
In Japanese Unexamined Patent Publication No. 929 (hereinafter, referred to as a first conventional technique), a Si ₃ N ₄ film 1 used as a 40-nm-thick capacitive insulating film was used.
12 is used as a stopper for contact etching for etching the PSG film 108. However, when the element is miniaturized and applied to, for example, a 256 Mbit DRAM,
A problem as shown in the sectional view of FIG. 6 occurs.

In FIG. 6, the width and interval of the gate electrode 204 are 250 nm and 300 nm,
4, the thickness of the SiO ₂ film 205 deposited on the gate electrode 204 was 150 nm, and the thickness of the SiO ₂ film of the sidewall 206 was 50 nm. In a 256 Mbit DRAM, the capacitance insulating film is 10 nm.
And the film thickness is insufficient to use the capacitive insulating film as an etching stopper. Therefore, the SiO ₂ film 114 having a thickness of 100 nm used in the first conventional example is used.
Instead, a Si ₃ N ₄ film 214 having a thickness of 40 nm was used as an etching stopper.

In the contact etching for etching the PSG film 208, the PSG film 208 is etched and Si ₃ N ₄ deposited on the gate electrode 204 is formed.
The film 214 is exposed, and the PSG film 208 deposited between the gate electrodes 204 is further etched to remove at least the surface of the Si ₃ N ₄ film 214 deposited on the P-type silicon substrate 201 between the gate electrodes 204. It must be etched until it is exposed. PSG between the gate electrodes 204
While the film 208 is being etched, the Si ₃ N ₄ film 214 deposited on the top and side surfaces of the gate electrode 204 in the area of the contact 210 that has been opened is over-etched.

When the etching selectivity of the SiO ₂ film with respect to the Si ₃ N ₄ film is sufficiently large, the Si ₃ N ₄ film 118 works as an etching stopper. When the Si ₃ N ₄ film deposited in the portion cannot be used as an etching stopper and is etched, and the SiO ₂ film on the side wall is etched in over-etching, the conductor layer is buried in the contact 210 in such a situation. , Conductor layer and gate electrode 10
4 is short-circuited.

The reason that the Si ₃ N ₄ film did not function as an etching stopper at the end of the gate electrode is that the reactive ion etching has an oblique (FIG. 7B) flat etching rate (FIG. 7A). This is because the etching speed is about twice as high as the etching speed of the portion.

If the thickness of the Si ₃ N ₄ film 314 is made twice as large as 80 nm, for example, so as to serve as an etching stopper even in the above-mentioned oblique portion, as shown in FIG. There is a problem that the contact is not able to be opened by the method as in the first conventional example because it is buried with the ₃ N ₄ film 314. That is, when the element is miniaturized, a manufacturing method is required in which the thickness of the nitride film serving as an etching stopper is sufficiently smaller than the distance between the gate electrodes, and a contact opening is provided so as to serve as an etching stopper. is there.

As a method for avoiding the problem that the above-mentioned Si ₃ N ₄ film does not work as an etching stopper at the slanted end portion of the gate electrode when the thickness of the Si ₃ N ₄ film is small, for example, Japanese Patent Laid-Open No. 6-124944. Discloses a semiconductor device.

FIG. 9 shows a circuit diagram similar to the example shown in FIG. 6 using the method shown by the semiconductor device of the above-mentioned Japanese Patent Application Laid-Open No. 6-124944 (hereinafter referred to as a second prior art).
It is sectional drawing which shows the manufacturing method of opening a contact on the assumption that it applies to a 56M bit DRAM.

[0019] As shown in FIG. 9 (a), the width of the gate electrode 404, spacing and thickness, the thickness of the SiO ₂ film 405 is deposited on the gate electrode 404, SiO ₂ film thickness of the side wall 407 Had the same dimensions and film thickness as FIG. Next, a Si ₃ N ₄ film 414 having a thickness of 40 nm is formed, and a PSG film 408 having a thickness of 300 nm is further formed.

Next, as shown in FIG.
9 for 400 seconds using diluted hydrofluoric acid (HF: H ₂ O =
1:10), the PSG film 408 is wet etched to open the upper contact 410a, and then the Si ₃ N ₄ film 138 is anisotropically etched by dry etching using CF ₄ to open the lower contact 410b.

Thereafter, when bit lines 411 are formed, FIG.
The structure shown in (c) is obtained.

In the second conventional example, since the PSG film 408 is etched and wet etching is used to open the upper contact 410a, the Si ₃ N ₄ film 41 is used.
Even when the film thickness of 4 is as thin as 40 nm, the Si ₃ N ₄ film 414 is not etched at the end of the gate electrode as in the first conventional example, and serves as an etching stopper.

However, since the wet etching is an isotropic etching, the size of the opening above the upper contact 132 is wider than the size of the opening defined by the resist 409. For example, if the opening size of the resist 409 is 150
In the case of μm, the opening size above the upper contact 410a is about 500 nm, which is larger than the width 350 nm of the bit line 411 on the upper contact 410a. As a result, the bit line 411 must be formed so as to cross the step of the upper contact 410a. Such a step may cause a difference in the depth of focus or a difference in the resist film when the resist pattern of the bit line 411 is formed by photolithography. The change in thickness causes a problem that pattern formation is difficult.

A problem common to the first conventional example and the second conventional example is that an interlayer insulating film formed between a word line and a bit line is a composite of an Si3 N4 film and a thick PSG film. Since the film becomes a film, the thickness of the interlayer insulating film increases. As a result, there is also a problem that the contact resistance of the peripheral contact is increased by increasing the depth of the peripheral contact formed in the peripheral region.

According to the present invention, even when the element is miniaturized, the contact connecting the conductive layer and the diffusion layer formed on the gate electrode with the interlayer insulating film interposed therebetween does not short-circuit with the gate electrode. It is an object of the present invention to provide a method of manufacturing a semiconductor device in which the thickness of an interlayer insulating film formed is reduced and the depth of a contact formed in a peripheral region is not increased.

[0026]

According to a method of manufacturing a semiconductor device of the present invention, a step of forming a field oxide film for element isolation on a semiconductor substrate of one conductivity type, a step of forming a gate insulating film, a first conductive film, and a first conductive film. Sequentially forming the insulating film, forming the gate electrode by sequentially etching the first insulating film and the first conductive film, and forming the sidewall on the gate electrode using the second insulating film. Forming a diffusion layer of a transistor by ion-implanting impurities of a conductivity type different from that of the substrate into the surface of the semiconductor substrate using the field oxide film and the gate insulating film as a mask; A step of sequentially forming a film and a fourth insulating film, and a step of forming a fourth insulating film on the entire surface using a chemical mechanical polishing method (CMP) until the third insulating film or the first insulating film on the gate electrode is exposed. Polishing the film Forming a resist pattern for opening a contact hole by using a photolithography technique; and selectively opening an unnecessary portion of a fourth insulating film using the resist pattern as a mask to open an upper contact hole. Selectively removing the third insulating film using an anisotropic dry etching technique using the resist pattern as a mask to open a lower contact hole; and forming a contact comprising the upper contact hole and the lower contact hole. The method is characterized by including at least a step of filling the hole with a second conductive film and a step of forming a conductor layer made of a third conductive film so as to cover the contact hole.

Further, the conductive layer is a bit line or a storage node electrode of a dynamic random access memory (DRAM).

Preferably, the third insulating film is a silicon nitride film, the fourth insulating film is a silicon oxide film,
The etching used in the step of selectively removing unnecessary portions of the fourth insulating film using the resist pattern as a mask is wet etching using a hydrofluoric acid-based chemical.

Alternatively, the first insulating film is a silicon nitride film, the third insulating film is a silicon oxide film containing no impurities, and the fourth insulating film is a PSG film or a BPS film.
G film, wherein the etching used in the step of selectively removing unnecessary portions of the fourth insulating film by etching using the resist pattern as a mask is gas phase etching using HF gas.

According to the above manufacturing method, the fourth insulating film having a large thickness is polished by CMP until the first insulating film on the gate electrode is exposed, and is thinned. Then, the contact pattern defined by the resist is formed. In order to remove the fourth insulating film as a mask by isotropic wet etching or vapor phase etching having a high selectivity, the third insulating film became an etching stopper in these etchings and was embedded in the gate electrode and the contact. There is no short circuit between the conductor layer and the gate electrode. In addition, the fourth in isotropic etching
The width of the contact hole extending in the lateral direction is narrower than the width of the conductor layer formed above the contact because the thickness of etching the insulating film is thinner than that of the conventional example, and photolithography for forming the conductor layer is performed. , The formation of a resist pattern is facilitated. Also, the fourth insulating film is formed by CMP
As a result, the thickness of the interlayer insulating film in the peripheral region becomes thin, and as a result, the depth of the peripheral contact becomes shallow.

[0031]

Next, a first embodiment of the present invention will be described with reference to the drawings.

FIGS. 1 and 2 are sectional views showing the main manufacturing steps of the first embodiment of the method of manufacturing a semiconductor device according to the present invention in order. In the first embodiment,
This is applied to the manufacture of a stacked DRAM in which a capacitor is formed on a bit line having a 0.25 μm design rule, and is as follows.

As shown in FIG. 1A, the specific resistance is 10Ω.
After forming an N-well and a P-well (not shown) in a desired region on the surface of a P-type silicon substrate 1 cm, a 300 nm-thick field oxide film 2 is formed by LOCOS.
Gate oxide film 3 having a thickness of 10 nm in an oxygen atmosphere at 850 ° C.
Is formed, a first polysilicon film doped with phosphorus having a thickness of 50 nm is deposited by the CVD method, a first tungsten silicide film having a thickness of 100 nm is deposited by the sputtering method, and the thickness is further deposited by the CVD method. 70nm first
Of SiO ₂ film is formed, by lithography and etching to form a gate electrode 4 and the first SiO ₂ film 5 made of composite film of the first polysilicon film and the first tungsten silicide layer. The width and interval of the gate electrode 4 are 250 nm and 300 nm, respectively.

Next, phosphorus is ion-implanted into the memory cell portion to form an N-type diffusion layer 6a.
A second SiO ₂ film having a thickness of nm is grown and etched back to form a sidewall 7 made of the SiO ₂ film on the side surface of the gate electrode 4. Next, arsenic is ion-implanted into a desired region in the peripheral portion to form an N-type diffusion layer 6b.

Next, as shown in FIG. 1B, a 20-nm thick Si ₃ N ₄ film 14 and a 400 nm-thick first BPSG film 8 are grown on the entire surface by CVD. Heat treatment is performed at 850 ° C. for 10 minutes in an atmosphere.

Next, as shown in FIG. 1C, the first BPSG film 8 is polished by CMP until the surface of the Si ₃ N ₄ film 14 on the gate electrode 4 is exposed, and then the halftone phase shift is performed. The PSG film 8 remaining between the gate electrodes 4 is etched by wet etching using buffered hydrofluoric acid, using the resist 9 having a pattern having an opening diameter of 200 nm as a mask by KrF excimer laser lithography using a mask to form an upper contact 10a. To form Here, in wet etching using buffered hydrofluoric acid, the Si ₃ N ₄ film 14 sufficiently serves as an etching stopper. Also, the first BPSG to be etched
Since the film 8 is not above the Si ₃ N ₄ film 14 deposited on the gate electrode 4, the opening diameter of the upper contact 10a does not greatly increase.

Next, as shown in FIG. 1D, CH ₂ F ₂ and C _2, which have a large selectivity of the Si ₃ N ₄ film with respect to the SiO ₂ film, are used.
The lower contact 10b is etched by etching the Si ₃ N ₄ film 14 by anisotropic dry etching using a mixed gas of O _2.
Open.

Next, as shown in FIG.
Is removed, a second polysilicon film containing phosphorus having a thickness of 50 nm is deposited by a CVD method, and a second tungsten silicide film having a thickness of 100 nm is deposited by a sputtering method. Further, a bit line 11 made of a second tungsten silicide film and a second polysilicon film is formed by using a photolithography technique and a dry etching technique.

Next, as shown in FIG. 2B, a second BPSG film 12 having a thickness of 300 nm is deposited by the CVD method.
Heat treatment is performed at 850 ° C. for 10 minutes in a nitrogen atmosphere. Subsequently, after opening the capacity contact 13 by using the photolithography technique and the dry etching technique,
A third polysilicon film containing 0 nm of phosphorus is deposited. Subsequently, a storage node electrode 15 made of a third polysilicon film is formed by using a photolithography technique and a dry etching technique, and then has a thickness of 10 nm by a CVD method.
A Ta ₂ O ₅ film is deposited, and is deposited at 800 ° C. in an oxygen atmosphere.
The capacitor insulating film 16 is formed by oxidizing for about a minute. Further, after a titanium nitride film having a thickness of 100 nm is deposited on the entire surface by sputtering, a plate electrode 17 is formed by photolithography and dry etching, and a third BPS having a thickness of 300 nm is formed by CVD.
A memory cell is completed by depositing a G film 18 and performing a heat treatment at 800 ° C. for 10 minutes in a nitrogen atmosphere.

Next, as shown in FIG. 2C, a peripheral contact 19 is opened in the peripheral region by using a photolithography technique and a dry etching technique. In the present embodiment, since the first BPSG film is removed by using the CMP, the peripheral contact has a depth of 300 nm compared to the conventional example.
It became shallow. Subsequently, a titanium film having a thickness of 60 nm and a titanium nitride film having a thickness of 100 nm are deposited by a sputtering method.
Further, a tungsten film having a thickness of 400 nm is deposited by the CVD method, and the tungsten film is etched back to leave the tungsten film only on the peripheral contact. Then, a 400 nm-thick aluminum alloy film is deposited by the sputtering method. Finally, a metal wiring 20 made of an aluminum alloy film, a titanium nitride film and a titanium film is formed by using a photolithography technique and a dry etching technique.

Next, a second embodiment of the present invention will be described with reference to the drawings.

FIGS. 3 and 4 are cross-sectional views showing, in order, main manufacturing steps of a second embodiment of the method of manufacturing a semiconductor device according to the present invention. In the second embodiment, 0.
This is applied to the manufacture of a stacked DRAM in which a bit line is formed on a capacitor having a design rule of 25 μm, and is as follows.

As shown in FIG. 3A, the specific resistance is 10Ω.
After forming an N-well and a P-well (not shown) in a desired region on the surface of a P-type silicon substrate 51 cm, the LOCOS
A field oxide film 52 having a thickness of 300 nm is formed by a method, a gate oxide film 53 having a thickness of 10 nm is formed in an oxygen atmosphere at 850 ° C., and a first polysilicon film doped with phosphorus having a thickness of 50 nm by a CVD method. Is deposited, and then a first tungsten silicide film having a thickness of 100 nm is deposited by a sputtering method.
The the Si ₃ N ₄ film 55 is formed of, by lithography and etching, to form a Si ₃ N ₄ film 55 and the first polysilicon film and the gate electrode 54 made of a composite film of the first tungsten silicide layer. The width and interval of the gate electrode 54 are 250 nm and 300 nm, respectively.

Then, phosphorus is ion-implanted into the memory cell portion to form an N-type diffusion layer 56a.
A second SiO ₂ film having a thickness of 00 nm is grown and etched back to form a sidewall 57 made of the SiO ₂ film on the side surface of the gate electrode. Next, arsenic is ion-implanted into a desired region in the peripheral portion to form an N-type diffusion layer 56b.

Next, as shown in FIG. 3 (b), a second S layer not containing an impurity having a thickness of 20 nm is entirely formed by the CVD method.
iO ₂ film 64 followed by first BPSG of 400 nm thickness
After growing the film 58, heat treatment is performed at 800 ° C. for 10 minutes in a nitrogen atmosphere.

Next, as shown in FIG. 3C, the first BPSG until the surface of the second SiO ₂ film 64 or the Si ₃ N ₄ film 55 on the gate electrode 54 is exposed by the CMP method.
After polishing the film 58, a PSG film remaining between the gate electrodes by vapor phase etching using HF gas using a resist 59 having an opening diameter of 200 nm as a mask by KrF excimer laser lithography using a halftone phase shift mask 58 is etched to form upper contacts 60a. Here, in gas phase etching using HF gas, B containing impurities such as phosphorus and boron is used.
The PSG film is etched but contains no impurities
Since the O ₂ film is not etched, the second SiO ₂ film 64
Fully serves as an etching stopper. Also, since the first BPSG film 58 to be etched is not above the Si ₃ N ₄ film 55 deposited on the gate electrode 54, the opening diameter of the upper contact does not greatly increase.

Next, as shown in FIG. 3D, a second SiO 2 film is formed by anisotropic dry etching using CF 4 gas.
_{The second} film 64 is etched to open the lower contact 60b. As compared with the film thickness of the sidewall 57 of 100 nm, the second
Since the thickness of the SiO ₂ film 64 of 20 nm is sufficiently thin,
The gate electrode 54 is not exposed in anisotropic dry etching using F ₄ gas.

Next, as shown in FIG. 4A, after depositing an amorphous silicon film containing phosphorus with a thickness of 500 nm by the CVD method, a storage node electrode made of the amorphous silicon film is formed by photolithography and dry etching. After forming a pattern and performing processing to make the surface uneven, the storage node electrode 65 is formed,
A 10-nm-thick silicon nitride film is deposited and oxidized to form a capacitor insulating film 66. After depositing a second polysilicon film containing phosphor with a thickness of 100 nm on the entire surface by the CVD method, a plate electrode 67 is formed by a photolithography technique and a dry etching technique.

Next, as shown in FIG. 4B, a second BPSG film 62 having a thickness of 300 nm is deposited by the CVD method.
Heat treatment is performed at 850 ° C. for 30 minutes in a nitrogen atmosphere. Subsequently, after opening a bit contact 63 by using a photolithography technique and a dry etching technique,
A third polysilicon film containing phosphorus having a thickness of 200 nm is deposited by a method, and is etched back to leave the third polysilicon film on the bit contact. Subsequently, after a second tungsten silicide film having a thickness of 100 nm is deposited by a sputtering method, a bit line 16 made of the second tungsten silicide film is formed by using a photolithography technique and a dry etching technique.

Next, a third BPSG film 68 having a thickness of 300 nm is deposited by the CVD method, and is deposited at 850 ° C. in a nitrogen atmosphere.
The heat treatment for 30 minutes completes the memory cell.

The manufacturing process shown in FIG. 4C is the same as the manufacturing process of the first embodiment, and the description is omitted.

[0052]

As described above, if the method of manufacturing a semiconductor memory device according to the present invention is used, the third insulating film becomes an etching stopper in the etching of the fourth insulating film even if the element is miniaturized. Therefore, there is no short circuit between the gate electrode and the conductor layer embedded in the contact, and the reliability is improved even when the semiconductor device is formed at a high density. Further, the contact resistance was reduced due to the shallow depth of the peripheral contact.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a first embodiment of a semiconductor device manufacturing method of the present invention.

FIG. 2 is a continuation of FIG. 1;

FIG. 3 is a sectional view showing a second embodiment of the method of manufacturing a semiconductor device according to the present invention;

FIG. 4 is a continuation of FIG. 3;

FIG. 5 is a sectional view sequentially showing a method of manufacturing a semiconductor device according to a first prior art;

FIG. 6 is a cross-sectional view for explaining a problem of the first conventional example.

FIG. 7 is a view for explaining the reason why the problem shown in FIG. 6 occurs.

FIG. 8 is a sectional view for explaining another problem of the first conventional example.

FIG. 9 is a cross-sectional view for explaining a problem of the second conventional example.

[Explanation of symbols]

1, 51, 101, 201, 301, 401 P-type silicon substrate 2, 52, 102, 202, 402 Field oxide film 3, 53, 103, 203, 303, 403 Gate oxide film 4, 54, 104, 204, 304 , 404 Gate electrode 5, 6a, 6b, 56a, 56b, 106a, 106
b, 206a, 206b, 306a, 406a, 406
b N-type diffusion layer 7, 57, 107, 207, 307, 407 Side wall

Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical indication location H01L 21/336 H01L 27/10 681F 29/78 301Y

Claims (5)

[Claims] A step of forming a field oxide film for element isolation on a semiconductor substrate of a first conductivity type; and a step of forming a gate insulating film, a first conductive film and a first conductive film on the semiconductor substrate on which the field oxide film is not formed. Forming a gate electrode by sequentially etching the first insulating film and the first conductive film; and forming a sidewall on the gate electrode with the second insulating film. Forming a transistor diffusion layer by ion-implanting a second conductivity type impurity into the surface of the first conductivity type semiconductor substrate using the field oxide film and the gate insulating film as a mask; A step of sequentially forming an insulating film and a fourth insulating film; and a step of forming the fourth insulating film on the entire surface of the gate electrode by chemical mechanical polishing until the third insulating film or the first insulating film is exposed. Polishing process and Forming a resist pattern for opening a contact hole using a photolithography technique; and selectively etching an unnecessary portion of the fourth insulating film with respect to the third insulating film using the resist pattern as a mask. Opening the upper contact hole by using the resist pattern as a mask, selectively removing the third insulating film using an anisotropic dry etching technique to open the lower contact hole; A semiconductor comprising at least a step of filling a contact hole formed of a contact hole and a lower contact hole with a second conductive film, and a step of forming a conductor layer made of a third conductive film so as to cover the contact hole. Device manufacturing method. 2. The method according to claim 1, wherein said conductor layer is a bit line of a dynamic random access memory (DRAM). 3. The method according to claim 1, wherein said conductive layer is a storage node electrode of a dynamic random access memory (DRAM). 4. The third insulating film is a silicon nitride film,
The fourth insulating film is a silicon oxide film, and the step of selectively etching unnecessary portions of the fourth insulating film using the resist pattern as a mask is wet etching using a hydrofluoric acid-based chemical. A method for manufacturing a semiconductor device according to any one of claims 1, 2, and 3, wherein: 5. The method according to claim 1, wherein the first insulating film is a silicon nitride film,
The third insulating film is a silicon oxide film containing no impurities, the fourth insulating film is a PSG film or a BPSG film, and an unnecessary portion of the fourth insulating film is selectively etched using the resist pattern as a mask. The step of performing is a vapor phase etching using HF gas.
4. The method for manufacturing a semiconductor device according to any one of 2 and 3.