JPH10322663A - Computer system and video decoder used in the system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To exclude a repeat field from a field composite processing object only by adding simple hardware logic and to display a smooth image without fadering on a display monitor of a computer. SOLUTION: A mask circuit 503 of a DVD decoder 112 inputs a repeat first field flag register (Rep-Reg) 112b in every Vsync that is outputted from a video port control circuit 502 and when a repeat first field flag = '1', it masks Vsync and Hsync which correspond to the next field. It automatically frees the mask when the next Vsync comes. A VGA controller 113 does not capture video data while the Vsync and Hsync are masked. Then, a repeat field is easily excluded from a field composite processing object.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system and a video decoder, and more particularly to a computer system having a function of decoding moving image data which has been digitally compressed and encoded and displaying the data on a non-interlaced display monitor and the system. Related video decoder.

[0002]

2. Description of the Related Art In recent years, with the development of computers and multimedia technologies, various computer systems compatible with so-called multimedia have been developed. This type of computer system is provided with a function for reproducing moving images and audio data in addition to text data and graphics data.

[0003] With the development of multimedia in such computers, DVDs have recently attracted attention as new storage media that can replace CD-ROMs. One DVD
-ROM media can record about 4.7 Gbytes of data, which is about seven times the size of current CD-ROMs on one side, and about 9.4 Gbytes of data can be recorded on double-sided recording. By using the DVD-ROM media, it becomes possible to reproduce a title such as a movie including a large amount of video information on a computer with high quality.

[0004] Video information recorded on DVD-ROM media is composed of two types of data, presentation data and navigation data. Presentation data is a set of video objects to be reproduced, and is composed of video, sub-picture, and audio. Video data is compression-coded by the MPEG2 system. In addition, run-length encoding and AC
-3 are supported. The sub-picture is bitmap data, and is used for displaying subtitles of a movie or displaying options on a menu screen. One video object can include one channel of video data, up to eight channels of audio data, and up to 32 channels of sub-picture data.

[0005] Navigation data is playback control data for controlling the playback procedure of presentation data, and navigation commands can be embedded therein. The navigation command is for changing the reproduction contents and the reproduction order of the video data. By using this navigation command, the title creator can define various branch structures in the title, and can create an interactive title.

[0006] These titles are usually created for the purpose of being reproduced on a home TV using a consumer player, and there are the following two types of contents. (1) One is frame data (progressive data) encoded at a frame rate of 24 Hz like a movie film.

(2) The other is field data encoded at 60 Hz, that is, 60 fields per second. Some titles are composed of a combination of the data of (1) and (2). For example, for a program, frame data (progressive data) of (1)
The CM information and the like are titles having a structure such as using the field data of (2).

Both the frame data (progressive data) of (1) and the field data of (2) are D
The data is decoded by the VD decoder and output as 60 Hz field data for interlace display corresponding to the NTSC output. When displaying this on a computer display monitor, it is necessary to convert interlace display data output from the DVD decoder into non-interlace display data. This conversion is performed using a simple field combining process. That is, one frame is generated by superimposing even and odd fields on the frame memory, and this is displayed on the display monitor of the computer in a non-interlaced manner.

However, in the interlaced / non-interlaced conversion by the simple field combining, since a field having a time difference is combined into one frame, a so-called feathering in which the contour looks striped occurs. . This phenomenon is
This is particularly noticeable in fast-moving scenes.

There are the following two causes for this fading. (I) Field image problem: This is due to the fact that the above-mentioned field data (2) is synthesized. The field images have a time difference one by one (1/60 second), and when the field images having such a time difference are combined, the fading occurs.

(Ii) Repeat field problem: DVD
When decoding the frame data (progressive data) of 24 frames / second, the decoder converts the frame data of 24 frames / second into the field data of 60 fields / second by a 3: 2 pull-down method. This 3: 2 pull-down method is shown in FIG.

In FIG. 11, Frame No. Indicates the frame number of the frame data (24 frames / sec) before decoding, and Field No. Indicates the field number of field data (60 fields / second) corresponding to NTSC after decoding. The subscript (E) of the field number indicates an even field, and (O) indicates an odd field.

In the 3: 2 pulldown, a difference in frame rate is absorbed by creating three fields from one frame at a rate of two frames per three frames. When three fields are created, the third field has the same data as the first fee (R:
Repeat field). In FIG. 11, the third field of the first frame is the first field (1
E), and the third field of the third frame is also a repetition of the first field (3E).

In the simple field synthesizing process, two continuous field images (1E, 10 and 1E) are connected as shown in FIG.
, 2E, 2O and 3E,...) Are synthesized. The problem is 1E
And 2E, and 3E and 4E. 1E and 2E are generated from data having different frame numbers, and have a time difference of 1/24 seconds. Similarly, 3E and 4E also have a time difference of 1/24 seconds. Therefore, a frame obtained by a combination of fields including a repeat field causes a fader.

[0015]

As described above, conventionally, when a title created for a TV is displayed on a display monitor of a non-interlaced display, the above-described problem of the fader caused by the field picture problem and the repeat field problem occurs. There was a problem that occurs. Especially,
When a title is composed of frame data that requires 3: 2 pulldown, a combination of fields having a time difference occurs at a probability of 1/2, and the display quality of a moving image with a fast motion is lower than that of a TV. There was a problem of deterioration.

The present invention has been made in view of such a point, and enables a repeat field to be excluded from an object of a field combining process with a simple hardware configuration, so that a smooth image without fading is displayed on a display monitor of a computer. It is an object of the present invention to provide a computer system and a video decoder capable of playing back video.

[0017]

According to the present invention, there is provided a video decoder for decoding a video data string which has been digitally compressed and encoded, and a video port for inputting video data for interlaced display output from the decoder. A display for converting video data fetched from the video port into video data for non-interlaced display and displaying the video data on a display monitor by a field composing mode for composing an odd field and an even field to generate a frame for non-interlaced display. When the video data output from the video decoder is a repeat field generated by 3: 2 pull-down conversion, a video signal input to a video port of the display controller is provided. Characterized in that it comprises means for masking the synchronizing signal and the horizontal synchronizing signal.

In this computer system,
When the frame data requiring the 3: 2 pull-down conversion is input to the video decoder, the video decoder performs a decoding process involving the 3: 2 pull-down conversion, and the video decoder periodically outputs a repeat field. This repeat field is sent to the video input port of the display controller. At this time, the vertical synchronization signal and the horizontal synchronization signal output to the video input port are masked. Since the vertical sync signal and the horizontal sync signal are basically used as sync signals for capturing video data, masking the vertical sync signal and the horizontal sync signal to prevent the repeat field from being captured by the display controller. Can be. As a result, the repeat field is excluded from the target of the field synthesis, and the simple field synthesis processing is performed only by the combination of two fields in the same frame number. Therefore, a smooth image without fader can be reproduced on a display monitor of a computer only by adding simple hardware for masking the vertical synchronization signal and the horizontal synchronization signal.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a basic configuration of hardware and software of a personal computer according to an embodiment of the present invention.

The personal computer includes a DVD
As main hardware necessary for reproducing video information, a DVD-ROM drive 111 capable of accessing both a CD-ROM medium and a DVD-ROM medium, and DVD video information read from the DVD-ROM drive 111 DVD decoder 112 for decoding (video, sub-picture, audio), VGA controller 11 for controlling a non-interlaced computer display monitor (LCD, CRT)
3 and the like are provided.

The DVD-ROM medium stores video information constituting a DVD video title.
The title reproduction on the DVD-ROM medium is performed by the DVD driver group 114, the DVD application program 1
15. Controlled by the video port driver 116. The video port driver 116 is a software driver for controlling a digital video input port of the VGA controller 113.

The DVD driver group 114 is a software driver for controlling the MPEG2 video.
It controls the ROM drive 111 and the DVD decoder 112 to transfer video information from the DVD-ROM drive 111 to the DVD decoder 112.

From the DVD-ROM drive 111 to the DVD
The video information transferred to the decoder 112 is composed of an MPEG2 program stream, which includes coded video, sub-picture, and audio, respectively.

The video data transferred to the DVD decoder 112 by the MPEG2 program stream includes
As described above, there are a type composed of frame data (progressive data) encoded at a frame rate of 24 Hz, such as a movie film, and a type composed of field data encoded at 60 Hz.

Further, these two types of video data are converted to a DV format.
As control information for enabling the D decoder 112 to correctly decode, a progressive flag (Progressive Se) is included in the MPEG2 program stream.
qu.) and a repeat first field flag (Repeat First Field).

The progressive flag = 1 indicates that the video data to be decoded is frame data of progressive scanning, that is, frame data (progressive data) encoded at the above-described 24 Hz frame rate.
The progressive flag = 0 indicates that the video data to be decoded is the above-described field data.

The repeat first field flag is
This is used for controlling 3: 2 pull-down conversion, and a repeat first field flag = 1 indicates that a repeat field should be output next.

The DVD decoder 112 has a progressive flag register (Prog-Reg) 112a and a repeat first field flag register (Rep-Reg).
-Reg) 112b, where MPEG
The contents of the progressive flag and the repeat first field flag included in the two program streams are respectively set. The progressive flag register (Prog-Reg) 112a and the repeat first field flag register (Rep-Reg) 112a
Reference numeral 112b is used to control the decoding operation by the DVD decoder 112 and to notify external hardware or software of what kind of decoding is being performed by the DVD decoder 112.

The video data decoded by the DVD decoder 112 is data for interlaced display, and is directly input to the digital video input port of the VGA controller 113 via a dedicated video bus. The digital video input port of the VGA controller 113 has a vertical synchronization signal Vsync and a horizontal synchronization signal Hs.
A progressive flag signal and a repeat first field flag signal are also input in addition to the SYNC and the digital YUV data. These flag signals are VGA
It is used to control the operation of the interlace / non-interlace conversion executed by the controller 113.

The VGA controller 113 has a simple field combining mode and a complementary mode as modes for interlace / non-interlace conversion. In the simple field combining mode, two pieces of field data (even and odd fields) that are continuously input are combined to generate one piece of frame data. In the complement mode, the missing lines (odd lines for even fields and even lines for odd fields) from each input field are complemented by interpolation (interpolation processing), etc. One frame image is generated. In this case, for example, by averaging two consecutive lines of the input field for each pixel, a missing line to be present between the two lines is obtained.

Switching between the simple field synthesis mode and the complement mode is controlled by the value of the progressive flag output from the DVD decoder 112. In this case, when the progressive flag = 0, that is, when the field data is being decoded, the complementary mode is used. When the progressive flag = 1, that is, when the frame data is being decoded, the simple field combining mode is used.

In the simple field synthesizing mode, the value of the repeat first field flag is DVD
It is used to switch whether or not to exclude the field data from the decoder 112 from the field synthesis processing. That is, the repeat first field flag =
In the case of 1, the VGA controller 113 does not take in the field data output next from the DVD decoder 112. As a result, the repeat field is skipped and excluded from the field synthesis processing. On the other hand, when the repeat first field flag = 0, the combining process is performed in the order of input in units of two fields as usual.

Further, such skip control of the repeat field is performed by controlling the V output from the DVD decoder 112.
This can be performed more easily by masking sync and Hsync.

Further, the operation control of the interlace / non-interlace conversion executed by the VGA controller 113 can be executed by software.

In this case, the DVD decoder 112 periodically generates the interrupt signal I for each Vsync of the field data.
Issues an NTA and causes the CPU to execute interrupt processing.
During this interrupt processing, the progressive flag register (Prog-Reg) 112 of the DVD decoder 112
a and the repeat first field flag register (Rep-Reg) 112b are referred to. Then, a mode set command (ModeS
et), and a drop field command (Drop Field) for instructing skipping of field data
By issuing to the video port driver 116,
The conversion mode setting and the repeat field skip control of the VGA controller 113 are executed via the video port driver 116.

Next, a specific system configuration of the personal computer of this embodiment will be described with reference to FIG. This system corresponds to a notebook type personal computer, and includes a PCI bus 10, a CPU 11, a main memory (MEM) 12, an HDD
13, a DVD interface 16 composed of an ATAPI or SCSI interface, and an audio controller 17, and the aforementioned DVD-ROM drive 111, DVD decoder 112, and VGA controller 113 are provided.

The DVD-ROM drive 111 has a storage capacity of about 10 GB on both sides of the disk.
Up to 1 data stream stored in media
Read at a transfer rate of 0.8 Mbps. This DVD-
The ROM drive 21 includes, as shown in FIG.
2, pickup 213, pickup drive 2
14, a servo controller 215, and a drive controller 216 including an ECC circuit for error detection and correction. Motor 212, pickup 213, pickup drive 214, servo controller 215, and drive controller 216
Functions as a drive device for driving the DVD medium 211 and reading data recorded on the DVD medium 211.

On the DVD-ROM medium 211, for example, a movie of about 135 minutes on one side can be recorded. The movie information can include main video (video), sub-video (sub-field) up to 16 channels, and audio (audio) up to 32 channels.

In this case, these videos, sub-pictures,
The audio and the audio are recorded after being digitally compressed and encoded according to the MPEG2 standard. According to the MPEG2 standard, other encoded data can be included in data encoded by MPEG2, and the encoded data is treated as one MPEG2 program stream.

The video is encoded using MPEG2,
Run-length coding and DOLBY AC3 are used for sub-picture and audio coding, respectively. Even in this case, the encoded video, sub-picture, and audio are treated as one MPEG2 program stream.

The encoding processing of the MPEG2 standard is variable rate encoding, and the amount of information recorded / reproduced per unit time can be made different. Therefore, the higher the moving rate of the scene, the higher the transfer rate of the MPEG stream constituting the frame group corresponding to the scene, the higher the quality of the moving image can be reproduced.

In order to utilize such features of MPEG2, in this embodiment, a title such as a movie is recorded on the DVD medium 211 using a data format as shown in FIG.

As shown in FIG. 4, one title is composed of a file management information section and a data section, and the data section has a large number of data blocks (block # 0).
~ # N). D at the beginning of each data block
There is an SI (Disk SerhInformation) pack, and one data block is from the DSI pack to the next DSI pack. The storage location of each DSI pack is managed by the disc search map information in the file management information section.

One data block constitutes information for 15 frames required for reproducing a moving image for a certain period of time, for example, 0.5 seconds, and includes a GOP (Group of).
picture). Each data block contains
Video pack (VIDEO pack), sub-picture pack (SP pack), and audio pack (AUD pack)
IO packs) are multiplexed and recorded. These video packs (VIDEO packs), sub-picture packs (SP packs), and audio packs (AUDI packs)
O-pack) is a coded video, sub-picture, and audio data unit. The data size of these packs is equivalent to the above-mentioned sector size and is fixed, but the number of packs that can be included in one data block is variable. Therefore, a data block corresponding to a scene with a sharp motion includes a larger number of video packs.

Each of the video pack, the sub-picture pack, and the audio pack includes a header section and a packet section (video packet, sub-picture packet, and audio packet). The packet part is the encoded data itself. The header section includes a pack header, a system header, and a packet header. In the packet header, a stream ID indicating whether the corresponding packet is a video packet, a sub-picture packet, or an audio packet is registered. .

The encoded data recorded on the DVD is scrambled by using a predetermined encryption algorithm, for example, for the encoded data of an arbitrary sector. This is to prevent unauthorized copying of the title.

In the DVD, a multi-story function for selecting and playing back a scene group corresponding to a scenario designated by the user among a plurality of scenarios, and a user designated in a plurality of videos having different shooting angles. It also has a multi-angle function for selecting and playing back images at different angles.

These functions are such that a plurality of videos corresponding to a multi-story and a multi-angle are multiplexed in units of, for example, data blocks, and the position and the position of the data block for each story or angle are determined by disc search map information or the like. This is achieved by managing connections.

Next, each unit of the system shown in FIG. 2 will be described. The CPU 11 controls the operation of the entire system, and executes an operating system and an application program to be executed stored in a system memory (MEM) 12. DVD-RO
The transfer and reproduction of the data recorded on the M media is performed by CP
This is executed by causing U11 to execute the above-described DVD driver group 114, DVD application program 115, and video port driver 116.

The DVD interface 16 is an HDD or C
This is a disk interface for connecting a disk device such as a D-ROM to the PCI bus 10. In this embodiment, a DVD-RO
Data transfer with the M drive 111 is performed. The DVD interface 16 includes a DVD-ROM drive 111
For temporarily holding data read from
FO buffer 162 and I / O port 1 for reading data from FIFO buffer 162 onto PCI bus 10
61 are provided. The I / O port 161 includes an I / O register that can be read by a bus master device that issues an I / O read transaction on the PCI bus 10.

The audio controller 17 includes a CPU 1
1 controls the input / output of sound data under the control of the PCM sound sources 171 and F for sound output.
An M sound source 172, a multiplexer 173, and a D / A converter 174 are provided. The output from the PCM sound source 171 and the FM sound source 172 and the digital audio data transferred from the DVD decoder 18 are input to the multiplexer 173, and one of them is selected.

The digital audio data is a DVD-R
The audio data read from the OM drive 111 is decoded. Audio data is transferred from the DVD decoder 112 to the audio controller 17 via the audio bus 18a.
The CI bus 10 is not used. Therefore, digital audio data can be transferred at a high speed without affecting the performance of the computer system.

Under the control of the CPU 11, the DVD decoder 112 transmits the MPEG2
After reading out the program stream and separating it into video, sub-picture, and audio packets, they are decoded, synchronized, and output. The DVD decoder 112 is realized by a chip set mounted on a system board of the computer system. As shown in the figure, the master transaction control unit 201, the descramble control unit 202, and the MP
An EG2 decoder 203 and an I / O address register 204 are provided.

The master transaction control unit 201
This is for operating the DVD decoder 112 as a bus master (initiator) for issuing a transaction on the PCI bus 10.
6 to execute an I / O read transaction for reading moving image data. In this case, the I / O read transaction includes an address phase for designating the I / O port 161 of the DVD interface 16 and one or more data transfer phases subsequent thereto, and moving image data can be read by burst transfer. . The I / O address value designating the I / O port 161 is stored in the I / O address register 204 by the CPU 11.
Is set to

The MPEG2 program stream read by the master transaction control unit 201 is:
The data is sent to the MPEG2 decoder 203 via the descramble control unit 202. Descramble control unit 20
In step 2, a disk scramble process is performed in which the scrambled data included in the MPEG2 program stream is decrypted and restored. The MPEG2 decoder 203 performs a process of separating the MPEG2 program stream into video, sub-picture, and audio packets, and a process of decoding them.

The decoded audio data is transferred to the audio controller 18a via the audio bus 18a as digital audio data as described above. The decoded video and sub-picture are combined and sent to the VGA controller 113 as digital YUV data. In this case, the DVD decoder 1
Digital YUV from 12 to VGA controller 113
As described above, the dedicated video bus 1 is used for data transfer.
8b is used, and the PCI bus 10 is not used. Therefore, similarly to digital audio data, transfer of digital YUV data can be performed at high speed without affecting the performance of the computer system. As the audio bus 18a and the video bus 18b,
A ZV port or the like can be used.

The DVD decoder 112 has a built-in NTSC encoder 205 and also has a function of converting digital YUV data and audio data into an NTSC TV signal and outputting the signal to an external TV receiver.

The VGA controller 113 is a CPU
Under the control of this system, an LCD or an external CRT display used as a display monitor of this system is controlled, and supports not only a VGA specification text and graphics display but also a moving image display.

The VGA controller 113 includes a graphics display control circuit (Graphics) 1 as shown in the figure.
91, video display control circuit 192, multiplexer 19
3, a D / A converter 194, and the like.

The graphics display control circuit 191 controls the V
This is a GA compatible graphics controller, which converts VGA graphics data drawn in a video memory (VRAM) 20 into RGB video data and outputs it.
The video display control circuit 192 is an interface with the above-described digital video input port, and has a function of performing interlace / non-interlace conversion using a video memory (VRAM) 20 or a video buffer in the video display control circuit 192; A YUB-RGB conversion circuit for converting YUV data converted to frame data for display into RGB video data is provided.

The multiplexer 193 selects one of the output data of the graphics display control circuit 191 and the video display control circuit 192, or converts the video output from the video display control circuit 192 onto the VGA graphics from the graphics display control circuit 191. Combine and output to LCD. Further, the D / A converter 194 converts the video data from the multiplexer 194 into analog RGB signals and outputs the analog RGB signals to a CRT display.

FIG. 5 shows a specific connection relationship between units constituting the DVD decoder 112. FIG.
The PCI interface unit 501 comprises the above-described master transaction control unit 201, descramble control unit 202, and I / O address register 204. The MPEG2 program stream descrambled by the PCI interface unit is input to the MPEG2 decoder 203, where it is decoded. In this case, the MPEG2 decoder 203
Interprets the progressive flag and the repeat first field flag included in the MPEG2 program stream, and proceeds with the decoding operation according to the result. -Reg) 112a and a repeat first field flag register (Rep-Reg) 112
b.

The video data decoded by the MPEG2 decoder 203 is input to the NTSC encoder 205 and the video port control circuit 502 of the PCI interface unit 501. The video port control circuit 502 converts video data output from the MPEG2 decoder 203 into a data format for output to the video port of the VGA controller 113,
The vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the digital YUV data, the progressive flag signal, and the repeat first field flag signal described with reference to FIG. 1 are output to the video port of the VGA controller 113. The progressive flag signal and the repeat first field flag signal sent to the VGA controller 113 are stored in a progressive flag register (Prog).
-Reg) 112a and the contents of a repeat first field flag register (Rep-Reg) 112b.

Next, a specific operation for interlace / non-interlace conversion control will be described. First, an interlace / non-interlace conversion control operation for solving the above-described field image problem will be described with reference to FIG.

When displaying the field data, the conversion mode of the VGA controller 113 is set to the complement mode as described above, and the missing lines from each field picture (odd lines for even fields, even lines for odd fields) ) To generate and display one frame image from one field image, it is possible to avoid combining fields with a time difference. However, some titles have a mixture of frame data (progressive data) and field data.
In this case, it is necessary to dynamically switch the conversion mode from the simple field synthesis mode to the complement mode during the playback of the title. By performing this switching, field data can be displayed without fading. Hereinafter, this switching method will be described. [Case of Using Progressive Flag Signal] FIG. 6 shows the relationship between switching between frame data (progressive data) and field data and switching between conversion modes.

In FIG. 6, Frame No. Indicates the frame numbers of the frame data (24 frames / sec) and the field data (60 fields / sec) before decoding. Field No. Indicates the field number of field data (60 fields / second) corresponding to NTSC after decoding. The subscript (E) of the field number indicates an even field, and (O) indicates an odd field.

During the decoding period of the frame data (24 frames / sec), the progressive flag register (Prog-Reg) 112a is set to "1",
When switching to decoding of field data (60 fields / second), the progressive flag register (P
(log-Reg) 112a is reset to “0”.

The DVD decoder 112 decodes video data while determining whether video data to be decoded is frame data or field data based on a progressive flag included in the MPEG2 program stream. In decoding frame data,
The frame rate is also adjusted by 3: 2 pull-down conversion. The video port control circuit 502 of the DVD decoder 112 outputs digital YUV data and a progressive flag signal, which are decoding results, to the video port of the VGA controller 113, together with Vsync and Hsync.

The VGA controller 113 samples the progressive flag signal output from the video port control circuit 502 of the DVD decoder 112 every Vsync. When detecting that the progressive flag signal is asserted to “1”, the VGA controller 113
Starts interlace / non-interlace conversion using the simple field synthesis mode. Then, upon detecting that the progressive flag signal has been deasserted to “0”, the VGA controller 113 changes the conversion mode to the complement mode. [When not using progressive flag signal] DVD
The decoder 112 decodes the video data while determining whether the video data to be decoded is frame data or field data based on the progressive flag included in the MPEG2 program stream. In the decoding processing of the frame data, the frame rate is also adjusted by 3: 2 pull-down conversion. The DVD decoder 112 outputs an interrupt signal INTA for each Vsync.
Issue This interrupt signal INTA is transmitted to the CP via hardware such as a router or an interrupt controller.
It is input to U11. Thereby, the DVD driver group 1
Fourteen interrupt routines are activated.

The interrupt routine is performed by the DVD decoder 11
2 progressive flag register (Prog-Re
g) Referring to 112a, if the progressive flag is "1"
Mode set command (Mo
deSet) to the video port driver 116 to instruct the VGA controller 113 to set the conversion mode to the simple field synthesis mode. The video port driver 116 writes the conversion mode setting information to the VGA controller 113, and sets the conversion mode to the simple field synthesis mode. Then, when the progressive flag is reset to “0”, the interrupt processing routine issues a mode set command (ModeSet) to the video port driver 116 to instruct the VGA controller 113 to switch the conversion mode to the complement mode. . The video port driver 116 is a VGA
Write the conversion mode setting information to the controller 113,
Switch the conversion mode from simple field synthesis mode to complement mode.

Next, an interlace / non-interlace conversion control operation for solving the above-described repeat field problem will be described with reference to FIG. When decoding frame data of 24 frames / sec (progressive data), the frame data of 24 frames / sec is converted into field data of 60 fields / sec by a 3: 2 pull-down method. In this 3: 2 pull-down conversion, as shown in FIG.
The third field of the first frame is a repeat field, and the first field (1E) is repeated. The third field of the third frame is also a repeat field. 3
E) is repeated.

The problem in performing the simple field synthesizing process is a combination of field data generated from frame data having different frame numbers.
By skipping the repeat field from the target of the simple field synthesis processing, the repeat field problem can be solved. Hereinafter, a skip field skip control method will be described. [When a Repeat First Field Flag Signal is Used] When video data to be decoded is frame data, the DVD decoder 112 determines the timing of generating a repeat field based on the repeat first field flag included in the MPEG2 program stream, and : Decoding the video data while adjusting the frame rate by pull-down conversion. In FIG. 7, for the sake of simplicity, the repeat first field flag and the generation timing of the repeat field are matched, but in practice, the repeat first field flag is set in the latter half of the first field as the repeat source. Reset in the first half of the second field.

The video port control circuit 502 of the DVD decoder 112 supplies the digital YUV data and the fast repeat field flag signal as the decoding result together with Vsync and Hsync to the VGA controller 1.
13 video ports. The first repeat field flag signal is the content of the repeat first field flag register (Rep-Reg) 112b, and indicates that the next output field is a repeat field.

The VGA controller 113 outputs the repeat first field flag signal output from the video port control circuit 502 of the DVD decoder 112 to Vsyn.
Sample every c. When detecting that the repeat first field flag signal is asserted to “1”, the VGA controller 113 does not capture the next field, that is, the repeat field. As a result, the repeat field is excluded from the target of the field synthesis, and the simple field synthesis processing is performed only by the combination of two fields in the same frame number.

That is, the VGA controller 113
As shown in the figure, first, one frame is generated by the first field (1E) and the second field (1O) of the first frame. Next, the repeat field 1
For the third field (1E) of the frame, the data is not taken in, and the first field (2E) of the second frame is not captured.
A second frame is generated by E) and the second field (2O). In this way, by skipping the repeat field, it is possible to obtain a screen without fader. [When the repeat first field flag signal is not used] When the video data to be decoded is frame data, the DVD decoder 112 determines the timing of generating a repeat field based on the repeat first field flag included in the MPEG2 program stream, and : Decoding the video data while adjusting the frame rate by pull-down conversion. The DVD decoder 112 issues an interrupt signal INTA for each Vsync. This interrupt signal INT
A is input to the CPU 11 via hardware such as a router and an interrupt controller. This gives D
An interrupt routine of the VD driver group 114 is started.

The interrupt routine is performed by the DVD decoder 11
2 is referred to, and if the repeat first field flag is set to “1”, a drop field command (Drop Field) is sent to the video port driver 11.
6 Video port driver 116
The video data capture prohibition information is written to the VGA controller 113 to instruct not to capture the next field data.

Next, referring to the flowchart of FIG.
The operation of the interrupt processing routine started by the interrupt signal from the DVD decoder 112 will be described.
The interrupt processing routine first includes a progressive flag register (Prog-Reg) 112a and a repeat first field flag register (Rep-Reg).
g) Read 112b and check whether the repeat first field flag is set to "1" (step S101). If the repeat first field flag is "1", the interrupt processing routine issues a drop field command and instructs not to capture the next field data (step S10).
3). Next, the values of the progressive flags “1” and “0”
If "1", the simple set mode is indicated by the mode set command, and if "0", the complementary mode is indicated by the mode set command (step S).
104, S105, S106).

FIG. 9 shows a second example of the structure of the DVD decoder 112 necessary for solving the repeat field problem. This configuration is the most characteristic part of the present invention.

As shown, a mask circuit 503 is provided at the output stage of the video port control circuit 502 of the PCI interface unit 501. This mask circuit 503 is for masking Vsync and hsync output from the video port control circuit 502, and is used to mask a repeat first field flag register (R
ep-Reg) 112b.

That is, in the mask circuit 503,
Vsync output from video port control circuit 502
Repeat first field flag register (R
If the value of (ep-Reg) 112b is input and the repeat first field flag = "1", Vsync and Hsync corresponding to the next field are masked. Then, when the next Vsync comes, the mask is automatically released.

Basically, since Vsync and Hsync are used as a start signal for the VGA controller 113 to capture video data from the video port, if Vsync and Hsync are masked, the data at that time is not captured. Therefore, by masking Vsync and Hsync corresponding to the repeat field by the mask circuit 503, the repeat field can be removed and the occurrence of a combination of fields having a time difference can be prevented. This is shown in FIG.

In FIG. 10, the third field (1E) of the first frame is a repeat field, and the corresponding Vsync and all the subsequent Hsyncs are set.
nc is masked by the mask circuit 503. As a result, the third field (1E) of the first frame, which is a repeat field, is skipped without being captured by the VGA controller 113. Next Vs
Since the mask is automatically released from the SYNC, the first field (2E) of the second frame is captured by the VGA controller 113 as usual, and used for the field synthesis processing.

As described above, in the configuration of FIG. 9, instead of using the repeat first field flag signal or the interrupt signal, a configuration is adopted in which the repeat field is excluded from the field synthesizing process by masking Vsync and Hsync. The repeat field problem can be solved without providing a signal line or the like.

Here, in addition to Vsync,
All Hsyn corresponding to the repeat field generation period
c is masked to prevent video data from being erroneously written to the off-screen area on the frame buffer and other display screen areas other than video.

As described above, in this embodiment,
Since the DVD decoder 112 itself has a function of notifying the video data structure (frame / field) to be decoded and instructing skipping of the repeat field, even if the video stream is scrambled, the flag in the stream is set. The above-described function can be realized by using such a function, and it is possible to efficiently prevent the synthesis of fields having a time difference without affecting the copy protection function. In particular, by solving the repeat field problem using the mask of Vsync and Hsync, the display quality of video on the display monitor can be improved only by adding simple hardware.

[0086]

As described above, according to the present invention, by repeating a repeat field by mask control of Vsync and Hsync, it is possible to prevent synthesis of fields having a time difference, thereby simplifying hardware. It is possible to reproduce a smooth image without fading on the display monitor of the computer only by adding the configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of a computer system according to an embodiment of the present invention.

FIG. 2 is an exemplary block diagram showing a specific hardware configuration of the system according to the embodiment;

FIG. 3 is a DVD-R used in the system of the embodiment.
FIG. 2 is a diagram illustrating a configuration of an OM drive.

FIG. 4 is an exemplary view showing an example of a recording format of moving image data used in the system of the embodiment.

FIG. 5 is an exemplary view showing a connection relationship between units in a DVD decoder used in the system of the embodiment;

FIG. 6 is a timing chart showing an interlace / non-interlace conversion mode switching operation in the system of the embodiment.

FIG. 7 is a timing chart showing a repeat field skip control operation in the system of the embodiment.

FIG. 8 is an exemplary flowchart showing a procedure of interlace / non-interlace conversion mode switching and repeat field skip control processing executed by software used in the system of the embodiment.

FIG. 9 is an exemplary block diagram showing a second configuration example of the DVD decoder used in the system of the embodiment;

FIG. 10 is a timing chart showing a repeat field skip control operation using the DVD decoder of FIG. 9;

FIG. 11 is a timing chart for explaining a conventional interlace / non-interlace conversion operation.

[Explanation of symbols]

111 DVD-ROM drive 112 DVD decoder 112a Progressive flag register (Prog-
Reg) 112b Repeat first field flag register (Rep-Reg) 113 VGA controller 114 DVD driver group 115 DVD application program 116 Video port driver 502 Video port control circuit 503 Mask circuit

Claims (4)

[Claims] 1. A video decoder for decoding a video data string which has been digitally compressed and encoded, and a video port for inputting video data for interlaced display output from the decoder, wherein an odd field and an even field are synthesized. A display controller that converts video data captured from the video port into video data for non-interlaced display and displays the video data on a display monitor by a field composition mode that generates a frame for non-interlaced display. The video data output from the video decoder is 3:
A computer system comprising: means for masking a vertical synchronizing signal and a horizontal synchronizing signal input to a video port of the display controller when a repeat field is generated by two-pull-down conversion. 2. The video data string includes repeat field information for instructing generation of a repeat field as information for controlling 3: 2 pull-down conversion of the video decoder. Means for outputting a repeat field according to the repeat field information; and means for controlling a mask of a vertical synchronization signal and a horizontal synchronization signal input to a video port of the display controller according to the repeat field information. The computer system according to claim 1. 3. An interlace display video input from the video input port using a field synthesis mode having a video input port and synthesizing an odd field and an even field to generate a frame for non-interlace display. It is configured to be usable in a computer system having a display controller that converts data into video data for non-interlaced display and displays the video data on a display monitor, and is digitally encoded and read from a recording medium used in the computer system. A video decoder that decodes the video data stream, wherein the video data output to the video input port of the display controller is a repeat field generated by 3: 2 pull-down conversion. Video decoder, characterized in that it comprises means for masking the vertical synchronizing signal and a horizontal synchronizing signal is input to the video port of the controller. 4. The video data string includes repeat field information indicating generation of a repeat field as information for controlling 3: 2 pull-down conversion of the video decoder. The means for masking the synchronization signal controls the masking of the vertical synchronization signal and the horizontal synchronization signal input to the video port of the display controller in accordance with the repeat field information, and controls the vertical synchronization signal and all the synchronization signals corresponding to the repeat field generation period. 4. The video decoder according to claim 3, wherein the horizontal synchronization signal is masked.