JPH10322211A - A/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption almost without sacrificing the performance, to simplify the configuration and to reduce the chip area by selecting rough resolution for a compressed part at a different signal position for each of pluralities of systems. SOLUTION: Parallel A/D converters 12R, 12G, 12B have pluralities of different reference voltages and digitize an analog input voltage by comparing the analog input voltage with pluralities of the reference voltages respectively. Gamma correction circuits 14R, 14G, 14B apply inverse gamma correction to digital R, G, B signals that are gamma-corrected on the premises of being displayed on a CRT. Number of comparators at a signal compression side is selected smaller than the number of comparators at a signal expansion side in the gamma correction circuits 14R, 14G, 14B. That is, the resolution at the signal compression side is made rough by thinning out the comparators act the signal compression side. Concretely the comparators are thinned depending on a gradient of the input at a smaller signal level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter having a non-linear conversion characteristic, and more particularly to a parallel type A / D converter suitable for use in a signal processing system for performing non-linear compression / decompression by combining a plurality of signals. .

[0002]

2. Description of the Related Art In a color TV system, the input / output characteristics of a picture tube such as a CRT are also called light-to-light conversion characteristics (light emission characteristics).
If a video signal output from an imaging device such as a CD (Charge Coupled Device) type solid-state imaging device is directly input to a picture tube, faithful color reproduction cannot be performed.
Therefore, on the signal source side (image transmission side), γ (gamma) correction is applied to the video signal in accordance with the light emission characteristics of the picture tube.

On the other hand, for digital signal processing, an analog video signal is converted into a parallel type A signal having a uniform resolution (resolution).
When digitization is performed by the D converter, the characteristics of the entire system are determined based on the resolution on the side expanded by the γ correction, so that the resolution on the side compressed by the γ correction is wasted. That is, in the parallel type AD converter having a uniform resolution, since the conversion operation is performed with a higher resolution than necessary in a portion where the signal is compressed, the power is additionally consumed correspondingly.

[0004] By utilizing the fact that the resolution on the side compressed by γ correction is wasted and making the resolution on the side compressed by γ correction coarse, power consumption can be substantially reduced without sacrificing performance. The applicant of the present invention has proposed a parallel A / D converter capable of reducing the noise (Japanese Patent Application No. Hei 7 (1994) -207).
-244172).

[0005] This technique can also be applied to an interface with a liquid crystal display. That is, video signals output from a VTR or a personal computer are subjected to γ correction on the assumption that they are displayed on a picture tube such as a CRT. Therefore, when a liquid crystal having a light emission characteristic that is substantially linear with respect to the input voltage is used as a display, it is necessary to perform inverse γ correction. In many designs, this inverse γ correction is performed as digital signal processing after AD conversion, so that a parallel AD converter having a uniform resolution wastes the resolution, as in the case described above.

[0006]

By the way, considering a color liquid crystal display, a parallel type A / D converter is used for video signals of R (red), G (green) and B (blue) which are three primary colors of additive color mixture. Are required. On the other hand, in consideration of the application of the above-described conventional technique, three similar AD converters can be used for R, G, and B video signals.
In this case, there is a slight, but similar, performance drop as in the case of a single unit.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to reduce power consumption while minimizing performance degradation when digitizing R, G, and B video signals. To provide an A / D converter.

[0008]

An A / D converter according to the present invention is used in a signal processing system for performing non-linear compression / expansion by combining a plurality of systems of signals. It is configured to be roughly set at different positions for each system signal.

In the A / D converter having the above configuration, since the characteristics of the entire system are determined based on the resolution on the expansion side, even if the resolution on the compression side is wasted, the performance is hardly sacrificed. Power consumption can be reduced.
In addition, by changing the position where the resolution is made coarse for each of the signals of a plurality of systems, it is possible to suppress the performance degradation when combining the signals of the plurality of systems as much as possible, as compared to the case where the same position is used.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows an LCD, for example.
FIG. 2 is a block diagram illustrating an example of a configuration of a signal processing system including γ correction in a display system using a (Liquid Crystal Display; liquid crystal display).

In FIG. 1, analog R, G, and B signals of three channels sent from a microcomputer or the like are converted into digital R, G, and B signals by an AD converter 11 according to the present invention.
It is converted to a B signal. The AD converter 11 includes, for example, parallel AD converters 12R and 12R for R, G, and B primary colors.
G and 12B are mounted on one chip.
Digital R, G and B signals are converted to DSP (Digital Signal).
Processor; digital signal processing).

The DSP circuit 13 is composed of gamma correction circuits 14R, 14G, and 14B provided corresponding to R, G, and B, and a signal processing unit 15 that performs various kinds of signal processing. The digital R, G, and B signals are subjected to inverse γ correction by the γ correction circuits 14R, 14G, and 14B, and various signal processing is performed by the signal processing unit 13. The digital R, G, B signals passed through the DSP circuit 13 are supplied to the LCD 17 via the driver 16 as drive signals.

[0013] Parallel AD converters 12R, 12G, 12B
Has a plurality of reference voltages having different voltage values from each other, and digitizes by collectively comparing an analog input voltage with each of the plurality of reference voltages. Will be described later. In the gamma correction circuits 14R, 14G, and 14B, the digital R,
Inverse γ correction is performed on the G and B signals. FIG. 2 shows the input / output characteristics of the inverse γ correction.

Here, a basic circuit configuration of the parallel type AD converter will be considered. FIG. 3 is a circuit diagram of an example of a 4-bit parallel AD converter. In FIG. 3, a reference voltage generating circuit 21 is constituted by 16 resistors R1 to R16 connected in cascade with each other. Lowest resistance R
The first open end is applied a reference voltage Vref _B of the bottom side, the reference voltage Vref _T top side to the open end of the resistor R16 of the uppermost is applied.

In the reference voltage generating circuit 21, the resistances of the resistors R1 to R16 are formed so as to have the same resistance as much as possible due to diffusion resistance, aluminum wiring resistance and the like. As a result, reference voltages at equal intervals are obtained at the connection points of the resistors R1 to R16. Each of these reference voltages is applied to 15 comparators C of the comparison circuit 22.
1 to C15 are applied as inversion (-) input terminals as comparison reference voltages. 15 comparators C1 to C15
Collectively compares the analog input voltage Vin applied to each non-inverting (+) input terminal with each comparison reference voltage.

In this comparison circuit 22, the fifteen comparators C1 to C15 compare the analog input voltage Vin with the respective comparison reference voltages, so that the comparison outputs of the comparators higher than a certain comparator are all logic "0". ,
The lower comparators are all in the state of logic "1". Each comparison output of the comparators C1 to C15 is supplied to the logic circuit 23. The logic circuit 23 takes two adjacent comparison outputs as two inputs, and generates an output of logic "1" when the lower comparison output is logic "1" and the upper comparison output is logic "0". 14 gates A1 to A14
And a gate 15 having only the uppermost comparison output as two inputs.

Each logic output of the logic circuit 23 is
4 is supplied. This encoder 24 has a logic circuit 23
Is encoded and output as 4-bit digital signals D0 to D3. As described above, in the parallel type AD converter, the resistors R connected in cascade are connected.
By setting the resistance values of 1 to R16 to be the same, a uniform linear conversion characteristic can be obtained.

However, since the parallel type A / D converter having the above-described basic circuit configuration has a uniform resolution, it is more than necessary in the portion where the signals are compressed by the subsequent gamma correction circuits 14R, 14G and 14B. The conversion operation is performed at the resolution of. Therefore, in the parallel type AD converter, the number of comparators on the signal compression side in the subsequent gamma correction circuits 14R, 14G and 14B is made smaller than the number of comparators on the signal expansion side, that is, the signal compression side. By reducing the number of comparators, the resolution on the signal compression side is reduced. To be more specific, in correspondence with the input / output characteristics of the inverse γ correction shown in FIG. 2, the comparator may be thinned in accordance with the input gradient at the lower signal level (darker).

FIG. 4 is a circuit diagram in the case where the present invention is applied to, for example, a 4-bit parallel type AD converter. In the figure, the same parts as those in FIG. 3 are denoted by the same reference numerals. In this example, the circuit configuration is such that every other comparator is thinned out in the smaller (darker) signal level. When compared with the basic circuit of FIG. 3, the comparison circuit (comparator array) 22
, For example, the comparators C2, C4, C6 are deleted, and the gates A2, A4, A
6 has also been deleted. Note that this circuit example is only for explaining the concept of thinning out, and is not limited to this.

As described above, in the parallel type AD converter,
By thinning out the comparator on the signal compression side according to the input gradient, the differential non-linearity (DNL) differs at the input level, but the magnitude of 1 LSB of the output code is constant. Conversely, there is integral linearity. In this way, the resolution of the signal compression side is coarsened by thinning out the comparator on the signal compression side, so that the circuit configuration of the comparison circuit and the encoder can be simplified by the amount of the thinning out of the comparator. , Power consumption can be reduced.

In this embodiment, when the parallel type AD converter having the above configuration is used as the AD converters 12R, 12G, and 12B in FIG. 1, the resolution (resolution) on the side compressed by γ correction is R, G, Roughening is performed at a different position for each B, that is, by changing the position where the comparator on the side compressed by the γ correction is thinned out for each of R, G, and B, the performance degradation in the brightness direction is suppressed. As a result, the power consumption of the AD converter can be reduced without any perceived performance degradation by human eyes. Or conversely, if the same performance degradation is allowed, the power consumption can be further reduced.

FIGS. 5 and 6 show the input / output characteristics of the 8-bit AD converter suitable for the present invention. The input / output characteristics are designed so that performance is more important than reduction in power consumption. The input is actually an analog voltage, which is interpreted and shown as a code of an ideal 8-bit AD converter. If the input code is 128 or less and the final code is 255, all R,
The G and B outputs match the code numbers. That is, the comparator is decimated by the input code 127, and the decimated position is different for each of R, G, and B.

FIG. 7 shows the step size of the signal processing system based on the input / output characteristics when γ = 2.0. This figure shows that when the input signal x is a continuous signal from 0 to 1, the output code y is

(Equation 1) Represents the jump amount of the output code y. As is clear from FIG. 7, the jump amount of each color of R, G, B is
At worst, it does not exceed 2. In addition, it can be seen that the combination of R, G, and B is suppressed to 1.3 or less halfway.

According to this characteristic, when the luminance is increased from black in white, the color becomes brighter while slightly changing the color. In the case of such characteristics, the colors are mixed and appear to the human eyes as white and bright, and the deterioration of the characteristics is not felt at all as compared with a full three-channel AD converter. Therefore, it is particularly useful for an AD converter in which the three primary colors of R, G, and B are mounted on one chip.

In the present invention, even if the value of γ is changed to some extent, the AD converter itself does not require any correction.
Further, in the present embodiment, the case where γ = 2.0 has been described, but γ = 2.2 is usually used,
This is an advantageous direction according to the present invention.

Also, in the present embodiment, an example has been described in which the present invention is applied to a signal processing system for performing gamma correction by combining R, G, and B video signals, but the present invention is not limited to this. The present invention can be applied to a general signal processing system that performs nonlinear compression / expansion by combining a plurality of systems of signals.

[0027]

As described above, according to the present invention,
In AD converters used in signal processing systems that perform nonlinear compression / expansion by combining multiple systems of signals, performance is almost sacrificed by coarsening the resolution of the compressed part at different positions for each of the multiple systems. Power consumption can be reduced without reducing the circuit area, and the chip area can be reduced by the amount that the circuit configuration can be simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a signal processing system including gamma correction.

FIG. 2 is an input / output characteristic diagram of inverse γ correction.

FIG. 3 is a circuit diagram showing a basic configuration of a parallel AD converter.

FIG. 4 is a circuit diagram illustrating the concept of a parallel AD converter according to the present invention.

FIG. 5 is an input / output characteristic diagram of an 8-bit AD converter (part 1)
It is.

FIG. 6 is an input / output characteristic diagram of an 8-bit AD converter (part 2)
It is.

FIG. 7 is a characteristic diagram showing a step size after inverse γ correction.

[Explanation of symbols]

Reference Signs List 11 AD converter 12R, 12G, 12B Parallel AD converter 13 DSP circuit 14R, 14G, 14B γ correction circuit 17 LCD (liquid crystal display)

Claims (2)

[Claims] An A / D converter used in a signal processing system for performing non-linear compression / expansion by combining a plurality of systems of signals, wherein a resolution of a part to be compressed is different at a position different for each of the plurality of systems of signals. An AD converter characterized by being roughly set. 2. A comparator array comprising a plurality of comparators each having a reference voltage having a different voltage value, and a comparator on a side to be compressed in the comparator array is provided by thinning out at a different position for each of the plurality of signals. 2. The AD converter according to claim 1, wherein: