JPH10321550A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the manufacture of a semiconductor device capable of forming the impurity layer of a width smaller than the line-to-line dimension of a masking pattern. SOLUTION: An ion source is installed tilt by a prescribed angle θ with respect to the vertical plane of the surface of an N-type semiconductor substrate 120. Impurity ions 141 are made incident inside the N-type semiconductor substrate 120 via the opening 123 of a resist film 124 from a direction tilted by the prescribed angle θ with respect to the vertical plane of the surface of the N-type semiconductor substrate 120. On the surface of the N-type semiconductor substrate 120 inside the opening 123, a projection surface 126 is formed corresponding to the wall surface of the opening 123. The impurity ions 141 are not injected to an area corresponding to the projection surface 126 inside the opening 123 but are injected only to areas other than that. Thus, a channel stop region 125 as the impurity layer is formed in the region of a width narrower than the width of the opening 123 of the resist film 124.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device for forming an impurity layer by implanting impurity ions through a mask having an opening corresponding to a pattern of the impurity layer formed in a semiconductor substrate. It relates to a manufacturing method.

[0002]

2. Description of the Related Art In recent years, with the spread of imaging devices such as video cameras equipped with semiconductor devices such as solid-state imaging devices, CCs have been developed.
Development of solid-state imaging devices such as D (charge-coupled device) has been actively conducted. The CCD has, for example, a charge storage portion (for example, N ⁺⁾ formed by injecting impurity ions into an N-type semiconductor substrate.
Layers), a virtual gate (for example, a P ⁺ layer), an impurity layer such as a transfer channel region (for example, an N ⁺ layer) and a channel stop region (for example, a P ⁻ layer), a charge transfer electrode formed in a film forming process, and a light shielding Al. (Aluminum) layer and the like. The formation of the above-described impurity layer is generally performed by
It is often performed using the ion implantation apparatus 300 shown in FIG.

In the ion implantation apparatus 300, a substrate support 330 for supporting an N-type semiconductor substrate 320 is provided at, for example, the bottom of a vacuum chamber 310 decompressed by a vacuum evacuation system (not shown). An ion source 340 is provided at a position facing the substrate support 330, and an impurity ion 341 (for example, boron ion (B ⁺ )) is generated by the ion source 340. The impurity ions 341 generated by the ion source 340 are accelerated and extracted in a beam form by an extraction electrode 342 provided at the outlet of the ion source 340. The extracted impurity ions 341 are vertically incident on the N-type semiconductor substrate 320, thereby forming an impurity layer.

Here, the formation of the channel stop region, which is the finest region of the above-described formation of the impurity layer, will be described in detail with reference to FIG. FIG.
^This is an enlarged view of a part of the cross section of the N-type semiconductor substrate 320 when the channel stop region of the ⁺ layer is formed.
It is assumed that an overflow barrier layer (P ⁻ layer) 322 has already been formed on the N-type semiconductor substrate 320 in the previous ion implantation step. Further, a resist film 324 as a mask is formed on the overflow barrier layer 322 of the N-type semiconductor substrate 320. The resist film 324 has, for example, a line dimension a
The opening 323 corresponding to the fine pattern to be formed is formed.

[0005] In the ion implantation apparatus 300, the impurity ions 341 are perpendicularly incident on the surface of the N-type semiconductor substrate 320 through the openings 323 of the resist film 324 and are implanted into the overflow barrier layer 322. As a result, a channel stop region 325 is formed. After that, the resist film 324 is removed in the ashing process.

In the above-described method, the line spacing a of the pattern of the resist film 324 and the impurity ions 3
The relationship a = c... (1) is established between the width 41 of the region into which 41 is implanted (hereinafter referred to as implantation width c). Therefore, in order to implant the impurity ions 341 into the desired implantation width dimension c, it is necessary to design the pattern line dimension a so as to satisfy the expression (1). For example, the injection width dimension c of the channel stop region of currently mass-produced CCDs is about 0.55 μm. Therefore, the line dimension a of the pattern of the resist film 341 is also 0.5
It is necessary to be about 5 μm. Particularly in recent years, further increase in the number of pixels and downsizing of CCDs have been demanded, and the injection width c
Is increasing to 0.4 μm or less. To meet this demand, an exposure apparatus having a processing accuracy of 0.4 μm or less is required.

[0007]

However, among light exposure apparatuses which are currently widely used, the exposure limit value (minimum line width of resist) is about 0.4 μm. Therefore, in the above-described method, it is difficult to make the injection width dimension smaller than the exposure limit value of the light exposure device, and there is a problem that it is impossible to increase the number of pixels and reduce the size.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of forming an impurity layer having a width smaller than a line dimension of a mask pattern. .

[0009]

According to a method of manufacturing a semiconductor device of the present invention, an impurity ion is made to enter a semiconductor substrate from a direction inclined with respect to a vertical plane of a semiconductor substrate surface, thereby forming an opening in a mask. The impurity layer is formed in a region having a width smaller than the width.

In this method of manufacturing a semiconductor device, the impurity ions enter the semiconductor substrate from a direction inclined with respect to the vertical plane of the surface of the semiconductor substrate, thereby forming a region having a width smaller than the width of the opening of the mask. , An impurity layer is formed.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to FIGS. FIG. 1 shows a cross section of an ion implantation apparatus 100 according to one embodiment of the present invention. FIGS. 2 and 3 show N in FIG.
It shows a part of the cross section of the mold semiconductor substrate 120 in an enlarged manner. 2 shows a state before forming a channel stop region (portion indicated by a broken line in the figure) of the CCD, and FIG. 3 shows a state when forming the channel stop region.

The ion implantation apparatus 100 includes a metal (for example, stainless steel) vacuum chamber 110 that is depressurized by a vacuum evacuation system (not shown), and a substrate support section that supports an N-type semiconductor substrate 120 at, for example, the bottom of the vacuum chamber 110. 130,
An ion source 140 attached to the vacuum chamber 110. The ion source 140 includes an N-type semiconductor substrate 120.
It is installed at a predetermined angle θ with respect to the vertical surface of the surface.

The ion source 140 generates impurity ions 1 by, for example, ECR (Electron Cyclotron Resonance) discharge.
41 (for example, B ⁺ ). In addition, a metal (for example, tantalum (T
The extraction electrode 142 in which a plurality of ion passage holes are formed in each of a plurality of (for example, two) plates a)) is provided. The ion implantation apparatus 100 generates an electric field between a plurality of plates constituting the extraction electrode 142,
The impurity ions 141 are accelerated and extracted in a beam form, and N
The light is incident on the mold semiconductor substrate 120 at a predetermined angle θ. A cooling means (not shown) is provided in the substrate support section 130, and the impurity ions 141 are provided.
Prevents the temperature of the N-type semiconductor substrate 120 from rising when the light enters the N-type semiconductor substrate 120.

Next, as a specific example of a method of manufacturing a semiconductor device according to one embodiment of the present invention,
A method for forming the channel stop region 125 using the “00” will be described.

As shown in FIG. 2, it is assumed that an overflow barrier layer (P ⁻ layer) 122 has already been formed on the N-type semiconductor substrate 120 in the previous ion implantation step. Further, a resist film 1 as a mask is formed on the overflow barrier layer 122 of the N-type semiconductor substrate 120.
24 are formed. In the resist film 124, an opening 123 corresponding to a fine pattern having, for example, an interline dimension a and a film thickness dimension b in an exposure step is formed.

In the ion implantation apparatus 100, the vacuum chamber 110 is depressurized by a vacuum exhaust system (not shown), and impurity ions 141 (for example, B ⁺ ) are generated by the ion source 140. The impurity ions 141 generated by the ion source 140 are accelerated and extracted in the form of a beam by the extraction electrode 142.

Here, in this ion implantation apparatus 100,
The ion source 140 is installed at a predetermined angle θ with respect to a vertical plane of the surface of the N-type semiconductor substrate 120. Therefore, the impurity ions 141 extracted from the ion source 140 pass through the opening 123 of the resist film 124 from the direction inclined at a predetermined angle θ with respect to the vertical surface of the surface of the N-type semiconductor substrate 120. Incident inside. The above-described predetermined angle θ is referred to as an ion incident angle θ in the following description.

As described above, since the impurity ions 141 are incident on the surface of the N-type semiconductor substrate 120 in an oblique direction, the surface of the N-type semiconductor substrate 120 in the opening 123 is, as shown in FIG. The projection surface 126 of the wall surface is formed. The impurity ions 141 are not implanted into the region corresponding to the projection surface 126 in the opening 123 but are implanted only into the other region. The implanted impurity ions 141 form the overflow barrier layer 32.
2 in the depth direction. Thus, a channel stop region 125 as an impurity layer is formed in a region of the resist film 124 having a width smaller than the width of the opening 123.

The conditions for ion implantation at the time of forming the channel stop region 125 are, for example, that the acceleration energy is 70 KeV and the density (dose) of the implanted ions is 1.
It is 8 × 10 ¹² cm ⁻² .

The implantation width dimension c of the region formed as the channel stop region indicated by the broken line in FIG. 2 is expressed by the following equation. c = a− (b · tan θ) (2) That is, as represented by the equation (2), the implantation width dimension c is controlled by the ion incident angle θ.

For example, in the case where a channel stop region having an injection width dimension c of 0.2 μm is formed in an opening 123 corresponding to a pattern having a line dimension a of 0.55 μm and a thickness dimension b of 0.35 μm. Is obtained by substituting the line dimension a, the film thickness dimension b, and the desired implantation width dimension c into the equation (2) to obtain 0.2 = 0.55− (0.35 · tan θ). Calculate θ. Based on the calculation result (θ = 45 °), the mounting angle of the ion source 140 with respect to the vertical surface of the surface of the N-type semiconductor substrate 120, that is, the ion incident angle θ is set to 45 °.

Thus, the channel stop region 1
The resist film 124 is removed from the N-type semiconductor substrate 120 on which the resist film 124 is formed by the ashing process, and finally, the CCD 150 as shown in FIG. 4 is formed. FIG.
It is sectional drawing which shows an example of the structure near the light receiving part of one pixel in D150. In the CCD 150, a charge accumulation portion 127 made of an N ⁺ layer is formed on the left side of the channel stop region 125 on the overflow barrier layer 122 in the drawing,
A virtual gate 128 made of a P ⁺ layer is formed on the charge storage section 127. On the right side of the channel stop region 125 on the overflow barrier layer 122 in the figure, a transfer channel region (charge transfer portion) 129 formed of an N ⁺ layer is formed. The read gate 130 is formed next to the gate.

Further, an insulating film 131 is formed on the channel stop region 125, on the virtual gate 128, on the transfer channel region 129, and on the readout gate 130. Through the insulating film 131, an insulating film 131 is formed on the channel stop region 125. The charge transfer electrode 132 is formed on the channel region 129 and the read gate 130. Further, on the charge transfer electrode 132 and the virtual gate 12
On the insulating protection film 133, a light-shielding Al (aluminum) having a light receiving portion 134 of a predetermined size on the virtual gate 128 is formed.
Layer 135 is formed. In this way, a finer CCD than before is formed.

As described above, in the method of manufacturing the semiconductor device according to the present embodiment, the impurity ions 141 are made to enter the N-type semiconductor substrate 120 from a direction inclined with respect to the vertical plane of the surface of the N-type semiconductor substrate 120. Therefore, the channel stop region 125 can be formed in a region having a width smaller than the width of the opening 123 of the resist film 124. Therefore, a finer impurity layer such as the channel stop region 125 can be formed with a simple configuration, and it is possible to increase the number of pixels and reduce the size of the CCD.

The method of forming the channel stop region 125 and its effects have been described using the ion implantation apparatus 100 according to one embodiment of the present invention.
The discharge is not limited to the CR discharge, and may be performed by, for example, discharge using a hot filament. In the ion implantation apparatus 100, the ion source 140 is fixedly installed in the vacuum chamber 110.
A bendable vacuum bellows may be provided between 0 and 0 so that the ion incident angle θ can be arbitrarily adjusted. Further, in the ion implantation apparatus 100, N
The impurity layer is formed on the type semiconductor substrate.
An impurity layer may be formed on another substrate such as As (gallium arsenide).

The method of manufacturing a semiconductor device according to the present invention comprises:
The present invention is not limited to the above embodiment, and the ion implanter to be used may have another structure. For example, even if the ion implantation apparatus 200 having the structure as shown in FIG. 5 is used, the same effect as the above embodiment can be obtained.

In this ion implantation apparatus 200, the vacuum chamber 2
The electrodes 250a and 250b divided into two poles are disposed to face each other between the ion source 240 inside the substrate 10 and the substrate support 230, and the vacuum chamber 210 is disposed between the electrodes 250a and 250b.
Is applied by a DC power supply 250c from outside. That is, the DC power supply 250c
By generating an electric field between the electrodes 250a and 250b, the trajectory of the impurity ions 241 extracted in a beam form from the extraction electrode 242 of the ion source 240 is deflected. As a result, the impurity ions 241 obliquely enter the N-type semiconductor substrate 220, and as a result, an impurity layer may be formed in a region narrower than the opening of the mask (resist film) as in the above embodiment. it can.

The ion implantation apparatus 200 shown in FIG.
In addition to the method of setting the ion incident angle θ by generating an electric field as described above, a method of generating a magnetic field using an electromagnet or a permanent magnet and thereby deflecting the ion trajectory may be adopted.

[0029]

As described above, according to the method of manufacturing a semiconductor device of the present invention, impurity ions are made to enter the semiconductor substrate from a direction inclined with respect to the vertical plane of the semiconductor substrate surface. The impurity layer can be formed in a region having a width smaller than the width of the opening of the mask, and a fine semiconductor device can be manufactured with a simple structure. Therefore, there is an effect that the performance of the imaging device and other electronic devices can be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a configuration of an ion implantation apparatus according to an embodiment of the present invention.

2 is a cross-sectional view of an N-type semiconductor substrate showing a state before a channel stop region in a CCD is formed by the ion implantation apparatus of FIG. 1;

3 is a cross-sectional view of an N-type semiconductor substrate showing a state when a channel stop region in a CCD is formed by the ion implantation apparatus of FIG.

FIG. 4 is a cross-sectional view illustrating an example of a structure near a light receiving portion of one pixel in a CCD.

FIG. 5 is a sectional view of an ion implantation apparatus according to another embodiment of the present invention.

FIG. 6 is a cross-sectional view of an ion implantation apparatus employing a conventional semiconductor device manufacturing method.

7 is a cross-sectional view of an N-type semiconductor substrate showing a state when a channel stop region in a CCD is formed by the ion implantation apparatus of FIG.

[Explanation of symbols]

100: ion implantation device, 110: vacuum chamber, 120: N
Type semiconductor substrate, 122 ... overflow barrier layer, 12
3 ... opening, 124 ... resist film, 125 ... channel stop region, 130 ... substrate support, 140 ... ion source,
141: impurity ion, 142: extraction electrode, 200
... Ion implantation apparatus, 210 ... Vacuum chamber, 220 ... N-type semiconductor substrate, 230 ... Substrate support, 240 ... Ion source, 24
1 ... impurity ions, 242 ... extraction electrodes, 250a ...
Electrode, 250b ... Electrode, 250c ... DC power supply

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor device, wherein an impurity layer is formed by implanting impurity ions through a mask having an opening corresponding to a pattern of an impurity layer formed in a semiconductor substrate, the method comprising: An impurity layer is formed in a region having a width smaller than the width of an opening of the mask by causing the impurity ions to enter the semiconductor substrate from a direction inclined with respect to a vertical surface of the semiconductor substrate surface. Semiconductor device manufacturing method.