JPH10320998A - Manufacture of memory circuit and integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To replace more troubled cells with a few spare rows in a memory integrated circuit. SOLUTION: A memory circuit 200 comprises a main data memory array 220, an error memory array 240 and a spare memory array 230 which has spare rows for the replacement of troubled memory cells. Address information for the identification of the troubled memory cells is stored in the error memory array 240. The data memory array 220, the spare memory array 230 and the error memory array 240 are accessed simultaneously. The output of the error memory array 240 cuts off the rows of the troubled cells selectively and the spare rows in the spare memory array 230 are used for the connection to a data bus connected to an output data bus 261. The data memory array 220, the error memory array 240 and the spare memory array 230 operate synchronously with each other.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates to the field of semiconductor memory devices and, more particularly, to improving the manufacturing yield of usable embedded and stand-alone memory integrated circuits.

[0002]

BACKGROUND OF THE INVENTION Today's data systems are becoming increasingly digital. As a result, such systems utilize the high speed at which electronic components, such as semiconductor devices, process information. While semiconductor devices in modern systems require high speed and reliability, such highly required features are calculated processes that require high accuracy and the goal of ensuring high quality products. Labor. Despite performing rigorous quality measurements, a significant number of defective semiconductor devices are manufactured, discovered, and discarded during the manufacturing process.
Since discarded devices waste a great deal of resources, various efforts have been made to recover (reuse) usable devices even if some memory cells are defective.

[0003] Semiconductor devices having embedded memories are particularly prone to defects. The memory circuit consists of a plurality of columns and rows, the intersections of which form thousands of storage cells,
Each storage cell stores binary (binary) "bit" data. In a factory test of a memory circuit, some defective cells are generally found. A failed cell cannot store any binary state data. According to conventional practice, only one cell is a binary "1" or "0"
Cannot be stored correctly, the entire column (or row) corresponding to the failed cell is permanently invalidated and replaced with another ("spare") column (or row). Alternatively, the entire semiconductor device is rejected.

[0004]

Generally, several spare rows are manufactured in a semiconductor device during manufacturing. In the prior art, each spare column can only replace a faulty cell along only one memory circuit column. Unfortunately, adding extra columns in a memory circuit increases the size of the circuit, and thus the size of the semiconductor device. As it is well known that minimizing the size of semiconductor devices is a goal in the art, those involved in the development and manufacture of such devices must use memory technology while reusing reusable memory circuits using redundant techniques. An attempt is being made to increase the cell failure coverage (the number of replaceable defective cells).

[0005]

SUMMARY OF THE INVENTION The above-mentioned problems are solved and a technical advance in semiconductor manufacturing technology is achieved by replacing a failed cell on a memory circuit. Specifically, each spare column is used to replace a plurality of failed cells in a plurality of memory circuit columns. In another embodiment, the spare row is used to replace a plurality of failed cells in a plurality of memory circuit rows. In the prior art, each spare column can only replace a failed cell on a single memory circuit column, so in an integrated circuit memory according to the present invention the same memory cell failure coverage is obtained with fewer spare columns, or , More defective memory cells can be replaced with the same number of spare columns.

In one embodiment, a memory circuit, such as a flash electronically erasable programmable read only memory (EEPROM), has at least one spare for replacing a main data memory array, an error memory array, and a failed memory cell. It consists of a spare memory array with columns. Address information identifying all failed main data array cells is stored in the error memory array. If the number of spare columns is greater than or equal to the maximum number of failed cells having a common row address, the spare columns can replace failed cells on any main data array column. If the number of spare columns is less than the maximum number of failed cells having a common row address, the memory cannot be reused using this method.

In operation, the data memory array, the spare memory array, and the error memory array are accessed simultaneously. The output of the error memory array is used to selectively disconnect a column of failed cells and connect a spare column in the spare memory array to a data path leading to an output data bus. Since the data memory array, the error memory array and the spare memory array operate synchronously, the read time of the main data memory array increases only slightly or not at all. Thus, according to the present embodiment, a memory circuit maker can effectively replace a failed cell while keeping the required number of spare columns to a minimum.

[0008]

FIG. 1 is a schematic diagram showing a memory array portion of an integrated circuit. By definition, a memory "array"
Has multiple cells, the size of the array can vary, and has several rows and columns. The parameters of each cell are defined by column and row intersections. In the illustrated embodiment, memory array 100 includes column 1
01, 102, and 103, and rows 104, 10
5, and 106. Columns 101-103 and row 10
Intersections 4 to 106 form 9 cells. Specifically, the intersections of row 104 and columns 101, 102 and 103 create memory cells 110, 120 and 130, respectively. The intersections of row 105 and columns 101, 102 and 103 are at memory cells 140, 150 and 160, respectively.
Generate Similarly, the intersections of row 106 and columns 101, 102 and 103 are at memory cells 170, 180, respectively.
And 190 are generated.

All memory cells in data memory array 100 have transistors for manipulating the binary value of each cell. The transistors in the memory cell 110 include a control gate 111, a drain 112, a source 11
3, and the floating gate 114. Since the transistor is well known to those skilled in the art, the function of the transistor will not be described in detail here. For purposes of the present invention, all other memory cells (ie, cells 110, 120, 13) in data memory array 100 of this embodiment
0, 140, 150, 160, 170, 180 and 1
It is sufficient to state that 90) also includes a transistor having a control gate element, a drain element, a source element, and a floating gate element. Failure of a memory cell is usually the result of destruction of all, some, or one of the transistor elements.

FIG. 2 shows a block diagram of an embodiment of a memory portion of an integrated circuit in which the present invention is implemented. In this example, memory circuit 200 is a flash EEPROM consisting of rows and columns forming a specific number of cells. As will be appreciated by those skilled in the art, the present invention may be applied to other types of memory (eg, static random access memory or dynamic random access memory) and memory circuits of various sizes, whether embedded or standalone. Can also be used.

The memory circuit 200 includes a memory array 21
0, an error memory array 240, and a multiplexer 260. The memory array 210 has a main data array 220 and a spare array 230. In the present embodiment, the main data array 220 has 512 columns and 256 columns.
Rows, whereby 131,072 memory cells are formed. Spare array 230 has eight "spare" columns and 256 rows, thereby forming 2,048 "replacement cells" available in spare array 230. The error memory array 240 is composed of 56 columns and 256 rows, and includes information regarding the location of the failed cell in the main data array 20, identification of the sense amplifier of the failed cell, and replacement of the failed cell from the spare array 230. And instructions for replacement with a replacement cell in the spare column.

In memory circuit 200, data from the eight columns is multiplexed into a single sense amplifier for sending to an internal data bus. 5 in the main data array 220
For 12 columns, 64 sense amplifiers (ie, PSA1, PSA2, PSA3,..., PSA6)
4). Main data array sense amplifiers PSA1-P
SA64 is connected to each of the input multiplexers IM1 to IM
It is interconnected via 64 with the main data array columns. Each sense amplifier used in main data array 220 receives data from eight columns via an input multiplexer. During a given memory read cycle, each input multiplexer interconnects one of the eight columns with the input of the sense amplifier via an input link. In this embodiment, the input links IL1 to IL64 connect the input multiplexers IM1 to IM64 to the sense amplifiers PSA1 to PSA.
Interconnect with A64. Main data array sense amplifier P
SA1 to PSA64 are output data links OL1 to OL.
Multiplexed data via the data bus 221
Send to The "one of eight"("1/8") column selection is always the same for all 64 main data array sense amplifiers and multiplexers. The externally supplied 3-bit column address determines which of the eight columns to select, as is well known to those skilled in the art. Of the 64 sense amplifiers used in the main data array 220, only 16 send information to the 16-bit internal data bus 221 during a given memory read cycle.

For the write cycle, 8
64 write circuits (PWR1 to PWR64) corresponding to 64 groups of
There is an eight column multiplexer. As is well known to those skilled in the art, a write circuit outputs a predetermined column voltage to write to a selected memory cell. The main data array memory cells are written by outputting desired data to the data bus. Specifically, the data is sent to the data bus 221 via the multiplexer 260 and input to the 16 selected write circuits. As is well known to those skilled in the art, the 16 write circuits are divided into 64 write circuits (PWR1 to PWR1) by two bits of the column address.
PWR64). The writing circuit is
A predetermined voltage is output to perform writing to 16 memory cells selected according to the １ ／ column selection in the 16 column multiplexers and the selected row. If the data to be written is "1", the "1" state is written to the cell. If the data to be written is "0", no data is written to the cell and the cell is erased, that is, maintained in the "0" state.

Spare data array 230 comprises a column of spare cells for replacing failed cells in a corresponding row of main data array 220. In the illustrated embodiment, the spare data array 230 comprises eight columns, a spare input multiplexer SIMI, a spare sense amplifier SSA1, and a spare write circuit SWR1. Spare array 230 includes a single spare sense amplifier S via input data link SI1.
It consists of SA1 and eight spare columns multiplexed into a single write circuit SWR1. SSA1 output and SW
The input of R1 is connected to the multiplexer 260 via the data bus 231. The selection of columns to access from the spare data array is controlled by the same externally supplied 3-bit column address as described above for the main data array. The column selection of “one out of eight” is the same for both the main data array and the spare data array, so that each spare column corresponds to 64 columns in the main data array in this embodiment. Can be replaced. As is well known to those skilled in the art, each of the eight spare columns
Replace faulty cells on 64 data array columns with the same "1 out of 8" column selection. However, unlike the prior art, the spare columns of this embodiment are not limited to replacement of failed cells along a single main data array column, and 64 spare columns if the failed cells have different row addresses. Can be replaced with a faulty cell in any of the columns. In the illustrated embodiment, the maximum number of failed cells that can be replaced by eight spare columns in spare data array 230 is 4,096 (ie, eight cells per row for 256 rows). It is. In the prior art, the same eight spare columns can only replace 2,048 failed cells. However, there are more severe restrictions on the spatial location of the replaced cells. Specifically, conventionally, each spare column replaces only the failed cells along a single main data array column. Thus, all replaceable failed cells are limited to eight main data array columns. If the failed cells are randomly distributed across the main data array 220,
In the prior art, only eight failed cells, ie, one per spare column, can be replaced.

In this embodiment, each fault cell has a separate row address, and for each of eight groups of 64 cells along each row, there is only one fault cell per group. In each case, the spatial distribution of replacement cells allows each spare column to replace up to 256 failed cells. The group of 64 cells consists of cells along rows that have the same "one out of eight" column selection during a given memory cycle. In another embodiment, the replacement cell is independent of the row or column address of the failed cell.
Perform a replacement for a given memory cycle in the main array. The address of each failed cell and the total number of failed cells are determined (mapped) during factory testing of the array after chip fabrication or by user testing before (or during) use. Specifically, the test is “launched”
It can be performed during or at initialization by the user. If a chip becomes unusable due to the number of failed cells and their spatial distribution, the chip is discarded.

The error memory array 240 has 56 columns and 256 rows. Therefore, there is one available in the error memory array 240 for storing information.
There are 4,336 cells. When data is input to the data bus and transferred through multiplexer 260, error memory array 240
The information on the location of each failed cell in is written. As with the main data array 220, the eight error memory array columns are multiplexed into a single sense amplifier and a single write circuit. During a read cycle, error memory sense amplifiers EMSA1, EMSA2,.
MSA7 receives data from the 56 error memory array columns via multiplexers EMM1 through EMM7 via input links EIL1 through EIL7. The outputs of the error memory sense amplifiers are output data links EO1-EO7.
Via the data bus 241. When writing to the error memory, the data to be written is
61 to the error bus 2 through the multiplexer.
41 and sent to the write circuits EWR1 to EWR7. As already described for the main memory array,
"One out of eight" column multiplexers EMM1-EMM
A predetermined voltage propagates to the selected column through MM7,
Write predetermined data to the selected cell. In operation, the main data array 220, the spare data array 230, and the error memory array 240 are accessed simultaneously.

When reading or writing the data memory array 210, immediately before or simultaneously with the read / write function, the error memory array 240
Are accessed and read. The output of the error memory 240 is received by the multiplexer 260 via the error data bus 241 and the multiplexer 260
Used to determine if a spare column is needed. If a spare column is needed, the address of the affected main data array sense amplifier and write circuit, which is replaced by the spare sense amplifier and spare write circuit, is output. The data stored in error memory array 240 includes the row and column addresses of each failed cell in the main data array, and information indicating whether a replacement cell should be used. The same row of the 256 rows is activated in the main data array, the spare data array and the error memory array. The "one out of eight" column selection in the error memory array is performed for each of the eight groups of 64 cells along each row in the main data array. Same as what is done in Therefore, during the replacement of the failed cell, one replacement cell is activated in the spare data array, and seven information cells are activated in the error memory array. One of the seven information cells is an error flag that indicates whether there is a failed cell in the corresponding group of 64 cells of the main data array. The other six information cells are error address cells that determine which column of the group of 64 cells contains the failed cell, if any. If the error flag indicates that there is a failed cell in the group of the main data array of 64 cells, multiplexer 260 accesses the column indicated by the error address cell to cause the corresponding spare column to be accessed. , Sense amplifier SSA1, and spare write circuit SWR1 are coupled to data bus 261. In this case, the main data array data bus 221 is disconnected from the data bus 261 by the multiplexer 260.
At all other times, the main data array sense amplifier is interconnected with data bus 261.

When reading the data memory array 210, the multiplexer 260 receives information from the main data memory array 220, the spare array 230, and the error memory array 240 via the data buses 221, 231 and 241 respectively. . The data is processed,
The data is sent to the external system via the output data bus 261. When writing to the data memory array 210, the multiplexer 260 transfers data to be written from the data bus 261 to the main data memory array 220 or the spare memory array 230, respectively.
1 or 231. According to the present embodiment,
Multiplexer 260 selectively disconnects external data bus 261 from main data array data bus 221 using control information received from error memory array 230. When disconnected from the main data array data bus 221, the external data bus 261 is interconnected with the spare data bus 231 so that data exchanged with the spare column is transferred. In this way, the bits normally stored in the failed cell of the main data array are stored in the replacement cell of the spare data array and multiplexed with other data. Thus, the integrity of the data stored in the memory circuit 200 is guaranteed.

[0019]

According to the present embodiment, according to the spare replacement method described above, when each failed memory cell has a different row address, a single spare memory cell can be used regardless of the column address of the failed memory cell. A column can replace a plurality of failed memory cells. In other words, one faulty cell in the first column is replaced for one row address, and another faulty cell, whether it is in the same column or another column, , Can be replaced for another row address. It is also possible to use spare rows instead of spare columns or to use any combination of spare rows and columns to achieve the results expected by embodiments of the present invention. In another embodiment, a failed cell at any location in the main data array can be replaced by a replacement cell. This is in stark contrast to the prior art where even if there is only one failed cell in the data memory array column, it is necessary to replace the existing data array memory column with the entire spare column. In this case, in the prior art, all the cells in the spare column are required to operate in order to be replaced with the entire column in the main data memory array. According to the present invention, not all cells in the spare column need to operate (unless, of course, all cells in the spare column are used to replace cells in the main data array). Thus, the number of spare rows required is reduced. In other words, for a given number of spare cell columns, the number of replaceable faulty cells increases.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a part of a memory array including a plurality of memory cells.

FIG. 2 is a system schematic diagram of an embodiment of a memory circuit in which the present invention is implemented.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 memory array 101 column 102 column 103 column 104 row 105 row 106 row 110 memory cell 111 control gate 112 drain 113 source 114 floating gate 120 memory cell 130 memory cell 140 memory cell 150 memory cell 160 memory cell 170 memory cell 180 memory cell 190 Memory cell 200 Memory circuit 210 Memory array 220 Main data array 221 Data bus 230 Spare array 231 Data bus 240 Error memory array 241 Data bus 260 Multiplexer 261 Data bus

 ──────────────────────────────────────────────────続 き Continuation of the front page (71) Applicant 596077259 600 Mountain Avenue, Murray Hill, New Jersey 07974-0636 U.S.A. S. A.

Claims (10)

[Claims] 1. A method of manufacturing a memory circuit, comprising the steps of: testing a main data array of a memory circuit to identify a failed cell; determining a failed cell position in the main data array; A replacement cell determination step of determining a replacement cell to be replaced, and a data path connection step of disconnecting a data path connecting the failed cell to the output data bus and connecting a data path connecting the replacement cell to the output data bus. A method for manufacturing a memory circuit, comprising: 2. The method of claim 1 wherein said step of connecting a data path comprises the step of disconnecting a data path coupling a failed cell to an output data bus during a read cycle. 3. The method of claim 1 wherein said step of connecting a data path comprises the step of disconnecting a data path coupling a failed cell to an output data bus during a write cycle. 4. The method of claim 1, wherein said step of determining a failed cell location comprises determining a column address and a row address of the failed cell. 5. The replacement cell determination step includes a step of confirming that a replacement cell in a spare column can be replaced with a defective cell at an arbitrary position in the main data array. Method 1. 6. The replacement cell determination step is such that, if each failed cell has a different row address, the replacement cell in the spare column can be replaced with a plurality of failed cells in a column of the main data array. 2. The method of claim 1, further comprising the step of verifying that the information is valid. 7. A method for improving the manufacturing yield of an integrated circuit including a memory circuit, comprising: testing whether a data memory array of the memory circuit has a defective cell; and identifying a column address of each defective cell. Identifying a row address of each failed cell; and defining a minimum number of replacement cells required to replace each failed cell in the data memory array. A method for improving the manufacturing yield of integrated circuits. 8. The method of claim 4, further comprising the step of using a replacement cell to replace a faulty cell at any location in the data memory array. 9. A main data memory array having a plurality of memory cells formed by intersections of rows and columns.
A spare data memory array (2) having a plurality of replacement cells for replacing a failed cell in the main data memory array.
30) a plurality of memory cells for storing information on the position of the row and column of the failed cell in the main data memory array and the position of the row and column of the corresponding replacement cell in the spare data memory array; An error memory array (240), comprising:
Means for disconnecting the data path from the failed cell to the output data bus and connecting the data path from the replacement cell in the spare data memory array to the output data bus (26)
0). An integrated circuit comprising: 10. The main data memory array is an EEPR
The integrated circuit of claim 9, comprising OM memory cells.