JPH10320997A - Programming circuit provided in semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a programming circuit by which malfunctioning such as reading/writing data from/in a defective memory cell, etc., can be avoided regardless of the rising speed of a power supply voltage when a power supply is closed and which is provided in a semiconductor memory device. SOLUTION: A PMOS transistor 7 is connected between a power supply 9 and one of the electrodes of a capacitor 1. When a redundancy circuit is used, a fuse 3 is cut off. When the voltage of the power supply rises gradually, if the voltage reaches the threshold voltage |Vpth| of the PMOS transistor 7, the PMOS transistor 7 is turned on and the voltage of the power supply 9 is applied to the one terminal of the connector of the capacitor 1 which produces a capacitance coupling. Therefore, the voltage level of the other electrode of the capacitor 1 is lifted to a voltage level equal to the voltage level of the one electrode and the level of a node N1 is fixed to an H level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a program circuit provided in a semiconductor memory device, and more particularly to a program circuit provided in a semiconductor memory device capable of replacing a defective memory cell with a redundant memory cell.

[0002]

2. Description of the Related Art Semiconductor memory devices such as SRAMs and DRAMs are generally provided with redundant memory cells arranged in a plurality of columns and a plurality of rows to replace defective memory cells for the purpose of improving yield. I have. First, the operation of such a conventional semiconductor memory device in which redundant memory cells arranged in the row direction (hereinafter, referred to as redundant memory cell rows) are used will be described.

In this case, a redundant memory cell is set in advance for a row address of a defective memory cell, and if a row address signal input from the outside is a row address signal corresponding to the defective memory cell, the program circuit is activated. A signal of a predetermined level is output to the redundant row address decode circuit. The redundant row address decode circuit activates a predetermined redundant word line in response to the row address signal. As a result, a redundant memory cell row connected to the redundant word line can be selected. When the bit line pair is activated by the column address signal, one redundant memory cell connected to the activated bit line pair is selected from the redundant memory cell rows. Therefore, data reading / writing is performed in this redundant memory cell instead of the defective memory cell.

Next, the operation in the case where a redundant memory cell arranged in the column direction (hereinafter, referred to as a redundant memory cell column) is used will be described.

Just as in the case of using a redundant memory cell row, a signal of a predetermined level is output from a program circuit to a redundant column address decode circuit in response to an externally input column address signal. A corresponding redundant bit line pair is activated based on the output signal, and a redundant memory cell column is selected. Then, data is read / written in one redundant memory connected to the word line activated by the row address signal in the selected redundant memory cell column.

That is, in a semiconductor memory device such as an SRAM or a DRAM, selection of a redundant memory cell is controlled via a redundant row address decode circuit and a redundant column address decode circuit based on the level of an output signal from a program circuit. I have.

FIG. 10 is a circuit diagram showing a program circuit 1000 in a conventional SRAM.

FIG. 11 is a diagram showing a change in the voltage level of the node N1 with respect to the voltage of the power supply 9 in the program circuit 1000 shown in FIG. 10, and FIG. 11 (a) shows a case where the voltage of the power supply 9 rises sharply. FIG. 7B is a diagram illustrating a change in the voltage level when the voltage of the power supply 9 gradually rises.

First, the operation when the program circuit 1000 is connected to the redundant row address decode circuit will be described. Referring to FIG. 10, program circuit 100
At 0, first, the fuse 3 is not blown when the corresponding redundant memory cell row is not used. Therefore, the ground voltage is applied to node N1, and node N1 is always fixed at L level. When the node N1 is fixed at the L level, the output of the half latch circuit 4, that is, the output of the program circuit 1000 is always at the H level. Therefore, an H-level signal is output from the program circuit 1000. In response to the H-level output signal, the redundant row address decode circuit outputs an L-level inactivation signal to inactivate a corresponding redundant word line. Therefore, the redundant memory cell row corresponding to this program circuit 1000 is not selected.

Next, when using the redundant memory cell row, the fuse 3 is cut. Referring to FIG. 10 and FIG. 11A, when the voltage of power supply 9 sharply rises at the time of power-on (time t1), capacitive coupling occurs by capacitor 1. Therefore, node N1 is raised to H level. However, when the power is turned on (time t1) and the voltage of the power supply 9 rises slowly, the above-described capacitive coupling does not occur. Therefore, the high resistance 2 is provided, and as shown in FIGS. 10 and 11B, the node N1 is gradually but surely raised to the H level by the high resistance 2. When the potential of the node N1 becomes H level, the output signal of the half latch circuit 4, that is, the output signal of the program circuit 1000 becomes L level. This L
In response to the output signal at the level, the redundant row address decode circuit outputs an activation signal at the H level to activate the corresponding redundant bit line pair. Therefore, a redundant memory cell row connected to the activated redundant bit line pair can be selected.

When the program circuit 1000 is connected to the redundant column address decode circuit, the operation is the same as that in the case where the program circuit 1000 is connected to the redundant row address decode circuit, except that the rows are replaced with the columns. Referring to FIG.
When the corresponding redundant memory cell column is not used in program circuit 1000, fuse 3 is not blown, as in the case where it is connected to the redundant row address decode circuit. Therefore, program circuit 1000 outputs an H-level signal. In response to the H level output signal, the redundant column address decode circuit outputs an L level inactivation signal to inactivate a corresponding redundant bit line pair. Therefore, the redundant memory cell column corresponding to this program circuit is not selected.

When a redundant memory cell column is used, the fuse 3 is blown in the same manner as when connected to the redundant row address decode circuit. At this time, the change in the voltage level of the node N1 with respect to the voltage of the power supply 9 is the same as that in FIG.
1 (a) and 1 (b). That is, when the voltage of the power supply 9 rises sharply at the time of power-on (time t1), capacitive coupling occurs by the capacitor 1, and the node N1 is raised to the H level. But,
At power-on (time t1), if the voltage of the power supply 9 rises slowly, the above-described capacitive coupling by the capacitor 1 does not occur, so that the node N1 is gradually but surely raised to the H level by the high resistance 2. It has become. Therefore, when node N1 goes high, program circuit 1000 outputs an activation signal at low level. In response to the L-level activation signal, the redundant row address decode circuit outputs an H-level activation signal to activate a corresponding redundant bit line pair. Therefore, a redundant memory cell column connected to the activated redundant bit line pair can be selected.

[0013]

However, even when a redundant circuit such as a redundant memory cell row or a redundant memory cell column is used in the program circuit 1000,
As described above, when the voltage of the power supply 9 rises slowly, since the capacitive coupling by the capacitor 1 does not occur, the level of the input node N1 is not easily fixed at the H level until the power supply voltage rises to some extent. Therefore, the activation signal of the L level is not stably output from the program circuit 1000, and there is a possibility that a defective memory cell is erroneously selected. As a result, there is a problem that a malfunction such as reading or writing of data is caused despite the defective memory cell.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. For example, data can be read from or written to a defective memory cell regardless of the rate of rise of power supply voltage when power is turned on. It is an object of the present invention to provide a program circuit provided in a semiconductor memory device capable of preventing a malfunction.

[0015]

A program circuit provided in a semiconductor memory device according to the present invention is connected between a predetermined node and ground, is disconnected when a redundant circuit is used, and uses the redundant circuit. Disconnection / connection means that is connected when not in operation, activation signal generation means for generating the activation signal in response to a voltage of a predetermined node, one end of which is connected to a power supply, and the voltage of the power supply is set to a predetermined level. A switching means that is turned on when it reaches, and a first capacitor having one electrode connected to the other end of the switching means and the other electrode connected to a predetermined node are provided.

According to a second aspect of the present invention, there is provided a program circuit provided in the semiconductor memory device, wherein one electrode is connected to a power supply and the other electrode is connected to a predetermined node. A second capacitor is further provided.

According to a third aspect of the present invention, there is provided a program circuit provided in the semiconductor memory device according to the first or second aspect, wherein one end is connected to a power supply and the other end is connected to a predetermined node. This is further provided with a set resistor.

According to a fourth aspect of the present invention, in the program circuit provided in the semiconductor memory device according to any one of the first to third aspects, the switching means is a MOS transistor.

According to a fifth aspect of the present invention, in the program circuit provided in the semiconductor memory device according to any one of the first to fourth aspects, the disconnection / connection means is a fuse.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.

(1) First Embodiment FIG. 1 is a block diagram showing a configuration of an SRAM 100 including a program circuit according to a first embodiment of the present invention.
Referring to FIG. 1, SRAM 100 includes a memory cell array 101, a row redundancy memory cell group 102A, a column redundancy memory cell group 102B, a row address buffer 103, a column address buffer 104, a row decoder 105, and a column decoder. 106, a word line driver 107, a multiplexer 108, a data input / output buffer 109, a read / write control circuit 110, a program circuit group 111A,
111B, redundant row address decode circuit 112, redundant column address decode circuit 113, and bit line load group 1
14 and data input / output lines (hereinafter referred to as I / O lines) 11
5 is provided. The memory cell array 101 is provided with a plurality of memory cells connected to a plurality of word lines and a plurality of bit line pairs crossing the word lines, but is not shown here. Further, a row redundant memory cell group 1
02A is provided with a plurality of redundant word lines, and the column redundant memory cell group 102B is provided with a plurality of redundant bit line pairs, which are also not shown. A bit line load group 114 is connected to the plurality of bit line pairs.

The row redundant memory cell group 102A includes a plurality of redundant memory cell rows arranged in the row direction. Each of the redundant memory cell rows includes a plurality of redundant memory cells connected to a common redundant word line. Each of these redundant memory cells is connected to a different bit line pair. On the other hand, the column redundant memory cell group 102B includes a plurality of redundant memory cell columns arranged in the column direction. Each of the redundant memory cell columns includes a plurality of redundant memory cell columns connected to a common bit line pair. Each of these redundant memory cell columns is connected to a different word line.

In the SRAM 100, a row address signal is input to the row address buffer 103 from outside. The row address signal is input to the row decoder 105 via the row address buffer 103, and the row decoder 105 outputs a row address decode signal. The row address decode signal is input to the word line driver 107 and the redundant row address decode circuit 112. The redundant row address decode circuit 112 is connected to the program circuit group 111A and the redundant word line group. Column address buffer 10
4 receives a column address signal from outside. The column address signal is input to the column decoder 106 via the column address buffer 104, and the column decoder 106 outputs a column address decode signal. The column address decode signal is input to the word line driver 107 and the redundant column address decode circuit 113. The redundant column address decode circuit 113 is connected to the program circuit group 111B and the redundant bit line pair.

Input data externally input to the data input / output buffer 109 is transmitted to a bit line or a redundant bit line via the I / O line 115 and the multiplexer 108. Then, the selected memory cell array 101
, Or the redundant memory cells in the row redundant memory cell group 102A and the column redundant memory cell group 102B. A memory cell in the memory cell array 101, or a row redundant memory cell group 102A or a column redundant memory cell group 1
Data read from a redundant memory cell in the data input / output buffer 10B via a bit line or a redundant bit line, a multiplexer 108, and an I / O line 115
9 is transmitted. The data is then output from the data input / output buffer 109 to the outside as output data. Read / write control circuit 110 activates and operates data input / output buffer 109 based on a read / write control input signal R / W input from outside. Further, the read / write control circuit 110
A chip is selected based on a chip selection control input signal CS input from outside.

When a redundant memory cell is used, a program circuit in program circuit group 111A outputs an activation signal for activating a redundant word line via redundant row address decode circuit 112. A program circuit in program circuit group 111B outputs an activation signal for activating a redundant bit line pair via redundant column address decode circuit 113. When the redundant memory cells are not used, the program circuits in the program circuit group 111A output a cancel signal for canceling the activation signal of the redundant word line. Also, the program circuits in the program circuit group 111B are composed of redundant bit line pairs and I / O output lines 115.
And a control signal for turning off the
8 is output. The operation will be described below in detail. In the following example, the redundant word line is activated when the output signal from this program circuit is at the L level,
Inactive when at level.

First, the program circuits in the program circuit group 111A provided corresponding to the row redundancy memory cell group 102A will be described.

FIG. 2 shows the program circuit group 1 shown in FIG.
FIG. 11 is a circuit diagram showing a program circuit 200 in 11A.
Referring to FIG. 2, a program circuit 200 includes a PMOS transistor 7, a capacitor 1, a fuse 3, and a half latch circuit 4. Half latch circuit 4
MOS transistor 5, inverter 6, and capacitor 11
And One source of the PMOS transistor 7
The drain electrode is connected to the power supply 9, and the other source / drain electrode is connected to one electrode of the capacitor 1.
The other electrode of capacitor 1 is connected to node N1. One end of fuse 3 is connected to node N1, and the other end is grounded.

In the half latch circuit 4, the input node of the inverter 6 is connected to the node N1, and the output node is connected to the output node N2 of the program circuit 200. One source / drain electrode of the PMOS transistor 5 is connected to the power supply 9, and the other source / drain electrode is connected to the input node of the inverter 6. One electrode of capacitor 11 is connected to the output node of inverter 6, and the other electrode is grounded.

Referring to FIGS. 1 and 2, to set program circuit 200 such that a predetermined redundant memory cell row is selected corresponding to the row address of a defective memory cell,
Fuse 3 of program circuit 200 corresponding to the redundant word line to which the redundant memory cell row is connected is cut in advance.

FIG. 3 shows the program circuit 20 shown in FIG.
FIG. 7A is a diagram showing a change in the voltage level of the node N1 with respect to the voltage of the power supply 9 of 0, and FIG. 7A is a diagram showing a change in the voltage level when the voltage of the power supply 9 rises sharply;
(B) is a diagram showing a change in voltage level when the voltage of the power supply 9 rises slowly.

First, referring to FIGS. 2 and 3A, when the voltage of power supply 9 rises sharply at power-on (time t1), the voltage of power supply 9 becomes the threshold voltage of PMOS transistor 7. Reaches the absolute value | Vthp |
2) Charge is supplied to one electrode of the capacitor 1 via the PMOS transistor 7. Therefore, one electrode of the capacitor 1 has a level equal to the voltage of the power supply 9. Further, since the voltage of the power supply 9 rises steeply, capacitive coupling occurs by the capacitor 1, and the voltage level of the other electrode (on the node N1 side) of the capacitor 1 is also raised to a level equal to the voltage of the power supply 9. Therefore, the voltage level of node N1 becomes equal to the voltage of power supply 9 and becomes H level. Therefore, the output signal from inverter 6 is L
Level.

Referring to FIGS. 2 and 3B, when the voltage of power supply 9 rises slowly at power-on (time t1), the voltage of power supply 9 is increased
When the threshold voltage | Vthp | becomes equal to or higher than the threshold voltage | Vthp |, the voltage of the power supply 9 equal to or higher than the threshold voltage | Vthp | is supplied to one electrode of the capacitor 1 at a stretch. Therefore, capacitive coupling by the capacitor 1 occurs,
The other electrode (node N1 side) is also boosted to a level equal to the voltage of the power supply 9, and the node N1 goes high. Therefore, the output signal from inverter 6 is at L level.

Therefore, the row address buffer 10
3 is a row address signal of a defective memory cell, the program circuit 2 corresponding to the row address signal regardless of the rising speed of the voltage of the power supply 9.
From 00, an L-level output signal is output to the redundant row address decode circuit 112. An activation signal of H level is output from redundant row address decode circuit 112 based on the output signal of L level. Therefore, a predetermined redundant word line corresponding to the row address signal in the redundant word line group is activated. Therefore, row redundancy memory cell group 10
The redundant memory cell row connected to the activated redundant word line in 2A can be selected. When the bit line pair is activated by the column address decode signal, a redundant memory cell connected to the activated bit line pair is selected from the redundant memory cell row. Therefore, data is read / written in the selected redundant memory cell instead of the defective memory cell.

Further, at the same time, a cancel signal for canceling an H-level row address decode signal for activating a word line connected to a defective memory cell is sent from redundant row address decode circuit 112 to word line driver 10.
7 is input. The word line connected to the defective memory cell is not activated by the cancel signal, and the defective memory cell is not selected.

Subsequently, when the row redundancy memory cell group 102A is not used, the fuse 3 in the program circuit 200
Do not cut off. At this time, the voltage level of node N1 is always fixed to the ground potential (that is, L level).
Therefore, the output signal output from inverter 6 is at H level. This H level output signal is turned into an L level inactivation signal by the redundant row address decode circuit 112. As a result, the redundant word line is not activated, and the redundant memory cell row is not selected. Therefore, no read / write operation is performed in the redundant memory cell.

The program circuits in the program circuit group 111A provided corresponding to the row redundant memory cell group 102A have been described above.
Program circuit group 111B provided corresponding to 02B
Program circuit 200 has the same configuration as the above-described program circuit 200, and performs the same operation for column redundant memory cell group 102B. When a redundant memory cell column is used, the fuse 3 of the program circuit 200 provided corresponding to the redundant bit line pair to which the redundant memory cell column is connected is cut in advance.

When the column redundant memory cell group 102B is used, and when the power is turned on (time t1), the voltage of the power supply 9 rises sharply, as in the case of the row described above,
When the voltage of the power supply 9 reaches the absolute value | Vthp | of the threshold voltage of the PMOS transistor 7 (time t2), the PMOS
The transistor 7 is turned on, capacitive coupling by the capacitor 1 occurs, and the voltage level of the node N1 is boosted to a level equal to the voltage of the power supply 9, that is, the H level. Therefore, the output signal from inverter 6 is at L level.

When the power supply is turned on (time t1), the voltage of the power supply 9 gradually rises to the threshold voltage | Vthp | of the PMOS transistor 7 in the same manner as in the above-described row. When it reaches (time t3) PM
The OS transistor 7 is turned on, capacitive coupling by the capacitor 1 occurs, and the voltage level of the node N1 becomes H level. Therefore, the output signal from inverter 6 is at L level.

Therefore, based on the L-level output signal output from program circuit 200, redundant column address decode circuit 112 causes row redundant address decode circuit 112 to output an H-level activation signal to word line driver 107. 113 outputs an activation signal of H level to the multiplexer 108. Therefore, a predetermined redundant bit line pair corresponding to the column address signal in the redundant bit line group is activated, and redundant memory cells connected to the activated redundant bit line pair in column redundant memory cell group 102B. The column becomes selectable. When the word line is activated by the row address decode signal, a redundant memory cell connected to the activated word line is selected from among the redundant memory cell columns, and instead of the defective memory cell,
Data reading / reading in the selected redundant memory cell
Writing is performed.

At this time, a control signal for turning off the bit line pair connected to the defective memory cell and the I / O line 115 is input from the redundant column address decode circuit 113 to the multiplexer 108. This control signal cancels the column address decode signal for activating the bit line pair. Therefore, the defective memory cell is not selected, and data reading / writing in the defective memory cell is not performed.

When column redundancy memory cell group 102B is not used, fuse 3 is not blown, and the voltage level of node N1 is always fixed to the ground potential (that is, L level), as in the case of the row described above. , The output signal output from inverter 6 attains an H level. Since the redundant column address decode circuit 113 does not activate the redundant bit line pair by this H level output signal, the read / write operation in the redundant memory cell column is not performed.

As described above, according to the SRAM 100 of the first embodiment of the semiconductor memory device of the present invention, even if the voltage of the power supply 9 rises slowly, the program circuit 200 in which the fuse 3 has been cut has the node N1 connected to the node N1. The voltage level stabilizes at the H level. Thereby, a redundant memory cell can be selected instead of a defective memory cell, and a read / write operation can be performed in the selected redundant memory cell.

As described above, according to the program circuit 200 provided in the SRAM 100 according to the first embodiment of the present invention, when a redundant circuit such as the row redundant memory cell group 102A or the column redundant memory cell group 102B is used, Irrespective of the rising speed of the voltage at the time of turning on, it is possible to prevent a malfunction such as reading or writing of data to a defective memory cell.

(2) Second Embodiment The SRAM according to the second embodiment is the same as the SRAM shown in FIG.
It has the same basic configuration as 100.

FIG. 4 shows an SR according to the second embodiment of the present invention.
The program circuit group 111A (111
FIG. 4B is a circuit diagram showing a program circuit 400 in B). Referring to FIG. 4, a program circuit 400 is obtained by further adding a capacitor 8 to the program circuit 200 according to the first embodiment of FIG. One electrode of the capacitor 1 is connected to the power supply 9 and the other electrode is connected to the node N1.

Here, as in the first embodiment, in this example, when the output signal of program circuit 400 is at L level, the redundant word line (redundant bit line pair) is activated and at H level. At that time.

FIG. 5 shows the program circuit 40 shown in FIG.
FIG. 7A is a diagram showing a change in the voltage level of the node N1 with respect to the voltage of the power supply 9 of 0, and FIG. 7A is a diagram showing a change in the voltage level when the voltage of the power supply 9 rises sharply;
(B) is a diagram showing a change in voltage level when the voltage of the power supply 9 rises slowly.

Referring to FIG. 4, similarly to the case of program circuit 100 according to the first embodiment, when a redundant memory cell is not used, fuse 3 is not blown, and the voltage level of node N1 is always grounded. It is fixed to the potential (ie, L level). Therefore, the output signal from inverter 6 becomes H level. The fact that the redundant memory cell is not selected based on the H-level output signal is the same as described in the first embodiment, and a description thereof will be omitted.

Next, a case where a redundant memory cell is used will be described. First, referring to FIGS. 4 and 5 (a), when the voltage of power supply 9 sharply rises at the time of power-on (time t1), capacitive coupling occurs in capacitor 8 and immediately the other electrode (node N1) is raised to the level of the voltage of the power supply 9. Therefore,
In the program circuit 400 according to the second embodiment shown in FIG.
When the voltage of the power supply 9 reaches or exceeds the threshold voltage | Vthp | of the PMOS transistor 7, capacitive coupling occurs in the capacitor 8, and the program circuit 30 according to the first embodiment.
At 0, the voltage level of the node N1 can be set to the H level earlier than the time required until the voltage of the node N1 changes to the H level (time t2). Therefore, the output signal from inverter 6 is at L level. Since the selection of the redundant memory cell based on the L-level output signal is as described in the first embodiment, the description is omitted here.

Referring to FIG. 4 and FIG. 5B, when the voltage of power supply 9 rises slowly at power-on (time t1), capacitive coupling by capacitor 8 does not occur.
Therefore, as in the case of the program circuit 200 according to the first embodiment in FIG. 2, when the voltage of the power supply 9 reaches the threshold voltage | Vthp | of the PMOS transistor 7 (time t3), the PMOS transistor 7 is turned on and the capacitor is turned on. 1
Causes the node N1 to go to the H level. Therefore, the output signal from inverter 6 is at L level. Since the selection of the redundant memory cell based on the L-level output signal is as described in the first embodiment, the description is omitted here.

As described above, according to the program circuit 400 provided in the SRAM according to the second embodiment of the present invention, in addition to the effect of the program circuit 200 according to the first embodiment, when the redundant memory cell is used (the fuse 3 is cut). When the voltage of the power supply 9 rises sharply at
, The voltage of the node N1 can be more rapidly increased to the voltage of the power supply 9.

(3) Third Embodiment An SRAM according to a third embodiment of the present invention is the SRAM shown in FIG.
It has the same configuration as AM100.

FIG. 6 shows an SR according to the third embodiment of the present invention.
The program circuit group 111A (111
FIG. 3B is a circuit diagram showing a program circuit 600 in B). Referring to FIG. 6, a program circuit 600 is obtained by further providing high resistance 2 to program circuit 200 according to the first embodiment of FIG. One end of the high resistance 2 is connected to the power supply 9 and the other end is connected to the node N1.

As in the case of the first embodiment, in this example, the redundant word line (redundant bit line pair) is activated when the output signal of program circuit 600 is at H level, and is at L level. It shall be deactivated at some point.

FIG. 7 shows the program circuit 60 shown in FIG.
FIG. 7A is a diagram showing a change in the voltage level of the node N1 with respect to the voltage of the power supply 9 of 0, and FIG. 7A is a diagram showing a change in the voltage level when the voltage of the power supply 9 rises sharply;
(B) is a diagram showing a change in voltage level when the voltage of the power supply 9 rises slowly.

Referring to FIG. 6, similarly to the case of program circuit 200 according to the first embodiment of FIG. 2, when a redundant memory cell is not used, fuse 3 is not blown, and the voltage level of node N1 is always maintained. It is fixed to the ground potential (that is, L level). Therefore, the output signal from inverter 6 becomes H level. The fact that the redundant memory cell is not selected based on the H-level output signal is the same as described in the first embodiment, and a description thereof will be omitted.

Next, a case where a redundant memory cell is used will be described. First, referring to FIGS. 6 and 7 (a), when the voltage of power supply 9 rises sharply at the time of power-on (time t1), the voltage of power supply 9 is reduced to PMOS transistor 7
The power supply voltage is supplied to the node N1 through the high resistance 2 until the voltage exceeds the threshold voltage | Vthp | of the node N1, and the node N1 is slightly boosted (time t1 to t2). Then the capacitor 8
And the node N1 is boosted at once to a voltage equal to the voltage of the power supply 9. Therefore, the output signal from inverter 6 is at L level. Since the selection of the redundant memory cell based on the L-level output signal is as described in the first embodiment, the description is omitted here.

Referring to FIGS. 6 and 7B, when the voltage of power supply 9 rises slowly at power-on (time t1), the voltage of power supply 9 becomes the threshold voltage of PMOS transistor 7. When it is less than | Vthp |, the voltage of the node N1 gradually increases due to the high resistance 2. This is because electric charges are supplied from the power supply 9 to the parasitic capacitance such as the gate capacitance of the inverter 6 via the high resistance 2. The voltage of the power supply 9 is equal to the threshold voltage of the PMOS transistor 7 | Vthp |
(Time t3), the PMOS transistor 7 is turned on, and the threshold voltage | Vthp is applied to one electrode of the capacitor 1.
| The voltage of the power supply 9 is supplied at a stretch. Therefore, capacitive coupling by the capacitor 1 occurs, the other electrode (node N1 side) also has a level equal to the voltage of the power supply 9, and the node N1 has an H level. Therefore, the inverter 6
Is at L level. Since the selection of the redundant memory cell based on the L-level output signal is as described in the first embodiment, the description is omitted here.

Therefore, the voltage level of node N1 gradually but surely rises until the voltage of power supply 9 reaches threshold voltage | Vthp |, so that the embodiment in which high resistance 2 is not provided is provided. 1 by the programming circuit 20
Compared with the case of 0, the time until the voltage of the node N1 becomes H level can be reduced.

As described above, according to the program circuit 700 provided in the SRAM according to the third embodiment of the present invention, in addition to the effect of the program circuit 200 according to the first embodiment, when the redundant memory cell is used (the fuse 3 When cutting),
When the voltage of power supply 9 gradually rises, it becomes possible to fix node N1 to the H level in a shorter time after the voltage of power supply 9 reaches threshold voltage | Vthp |.

(4) Fourth Embodiment An SRAM according to a fourth embodiment of the present invention is the same as the SRAM shown in FIG.
It has the same configuration as AM100.

FIG. 8 shows an SR according to the fourth embodiment of the present invention.
The program circuit group 111A (111
FIG. 3B is a circuit diagram showing a program circuit 800 in B). Referring to FIG. 8, a program circuit 111A is different from program circuit 400 according to the second embodiment in FIG.
Is provided. That is, it is a combination of the program circuit 400 according to the second embodiment and the program circuit 600 according to the third embodiment. One end of the high resistance 2 is connected to the power supply 9 and the other end is connected to the node N1. .

As in the case of the first embodiment, in this example, the redundant word line (redundant bit line pair) is activated when the output signal of program circuit 800 is at L level, and is at H level. It shall be deactivated at some point.

FIG. 9 shows the program circuit 80 shown in FIG.
FIG. 7A is a diagram showing a change in the voltage level of the node N1 with respect to the voltage of the power supply 9 of 0, and FIG. 7A is a diagram showing a change in the voltage level when the voltage of the power supply 9 rises sharply;
(B) is a diagram showing a change in voltage level when the voltage of the power supply 9 rises slowly.

Referring to FIG. 8, similarly to the case of program circuit 200 according to the first embodiment of FIG. 2, when a redundant memory cell is not used, fuse 3 is not blown and the voltage level of node N1 is always maintained. It is fixed to the ground potential (that is, L level). Therefore, the output signal from inverter 6 becomes H level. The fact that the redundant memory cell is deselected based on the H-level output signal is the same as described in the first embodiment, and a description thereof will be omitted.

Next, a case where a redundant memory cell is used will be described. First, referring to FIGS. 8 and 9 (a), when the voltage of power supply 9 sharply rises at the time of power-on (time t1), as described in the second embodiment, due to the capacitive coupling of capacitor 8, , Node N1 is raised in voltage level. Therefore, the node N1 is boosted almost at the same time as the power supply 9 is boosted. When the voltage at the node N1 is raised to H level, the output signal from the inverter 6 becomes L level.
Level. Since the selection of the redundant memory cell based on the L-level output signal is as described in the first embodiment, the description is omitted here.

Next, referring to FIGS. 8 and 9B, when the voltage of power supply 9 gradually rises at the time of power-on (time t1), as described in the third embodiment, power supply 9 The voltage is the threshold voltage of the PMOS transistor 7 | Vth
When the value is less than p |, the voltage of the node N1 is gradually increased due to the high resistance 2, so that the program circuit 100 of the first embodiment or the program circuit 600 of the second embodiment in which the high resistance 2 is not provided. As compared with, the time until the voltage of the node N1 becomes H level can be reduced.

When the voltage of power supply 9 becomes equal to or higher than threshold voltage | Vthp | of PMOS transistor 7 (time t3), P
MOS transistor 7 is turned on, capacitive coupling by capacitor 1 occurs, and node N1 attains H level. Therefore, the output signal from inverter 6 is at L level. Since the redundant memory cell is selected based on the L-level output signal as described in the third embodiment,
Here, the description is omitted.

As described above, the program circuit 800 provided in the SRAM according to the fourth embodiment of the present invention includes the program circuits 200, 400, and 400 according to the first to third embodiments.
It has 600 effects. That is, the program circuit 8
According to 00, in addition to the effect of the program circuit 200 of the first embodiment, when a redundant memory cell is used (when the fuse 3 is cut), when the voltage of the power supply 9 rises slowly, the node N1 is set to H in a shorter time. It becomes possible to fix to the level.

In all of the first to fourth embodiments, the threshold voltages at H level and L level are assumed to be equal to threshold voltage | Vthp |. Further, although the program circuit in the SRAM has been described, the present invention can be applied to a semiconductor memory device having a redundant circuit such as a DRAM. Further, contrary to the above example, the level of the output signal from the program circuit 200 is H
It is also possible to set so that the redundant memory cell is selected when the level is at the level and unselected when the level is at the L level.

[0071]

According to the program circuit provided in the program circuit according to the first aspect, when the redundant circuit is used, disconnection /
When the connection means is disconnected and the voltage of the power supply reaches a predetermined level, the switching means is turned on. Therefore, the voltage from the power supply is applied to the one electrode of the first capacitor at a stretch. As a result, capacitive coupling by the first capacitor occurs, the voltage level of the other electrode of the first capacitor is raised at a stretch, and the predetermined node is fixed at the predetermined level. Therefore, irrespective of the rising speed of the power supply voltage at power-on, the activation signal generation means appropriately outputs an activation signal for activating the redundant circuit, so that data is read or written to the defective memory cell. It is possible to prevent malfunctions such as the above.

According to the program circuit provided in the semiconductor memory device according to the second aspect, in addition to the effect of the first aspect,
When using a redundant circuit, when the supply voltage of the power supply rises sharply, capacitive coupling by the second capacitor occurs and the predetermined node is boosted even if the supplied voltage level does not reach the predetermined level. Therefore, the voltage of the predetermined node can be set to the predetermined level more rapidly as compared with the case where only the first capacitor is connected.

According to the program circuit provided in the semiconductor memory device according to the third aspect, in addition to the effect of the first or second aspect, when the supply voltage of the power supply rises slowly when the redundant circuit is used, the power is supplied. Until the voltage level reaches the predetermined level, the voltage is gradually supplied from the power supply to the predetermined node via the high resistance. Therefore, the predetermined node is gradually boosted to such an extent that the output of the activating means does not become unstable, so that the time required for the voltage level of the predetermined node to reach the predetermined level can be reduced. It becomes possible.

According to the program circuit provided in the semiconductor memory device of the fourth aspect, in addition to the effect of any one of the first to third aspects, in addition to the effect of the first aspect, the power supply is supplied from the power supply to the one electrode of the first capacitor via the MOS transistor. It is possible to supply a voltage.

According to the program circuit provided in the semiconductor memory device according to the fifth aspect, in addition to the effect of any one of the first to fourth aspects, when a redundant circuit is used by using a fuse, a predetermined node and a ground potential are used. And a predetermined node can be connected to the ground potential when the redundant circuit is not used.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an SRAM including a program circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a program circuit in a program circuit group shown in FIG. 1;

3A and 3B are diagrams illustrating a change in a voltage level of an input node of an inverter with respect to a power supply voltage of the program circuit illustrated in FIG. 1; FIG. 3A illustrates a change in a voltage level when the power supply voltage rises steeply; FIG. 3B is a diagram showing a change in voltage level when the power supply voltage rises slowly.

FIG. 4 is a circuit diagram showing a program circuit in a program circuit group provided in an SRAM according to a second embodiment of the present invention;

5A and 5B are diagrams illustrating a change in a voltage level of an input node of an inverter with respect to a power supply voltage of the program circuit illustrated in FIG. 4, wherein FIG. 5A illustrates a change in a voltage level when the power supply voltage sharply rises; FIG. 3B is a diagram showing a change in voltage level when the power supply voltage rises slowly.

FIG. 6 is a circuit diagram showing a program circuit in a program circuit group in an SRAM according to a third embodiment of the present invention;

7A and 7B are diagrams illustrating a change in the voltage level of the input node of the inverter with respect to the power supply voltage of the program circuit illustrated in FIG. 6; FIG. 7A illustrates a change in the voltage level when the power supply voltage sharply rises; FIG. 3B is a diagram showing a change in voltage level when the power supply voltage rises slowly.

FIG. 8 is a circuit diagram showing a program circuit in a program circuit group in an SRAM according to a fourth embodiment of the present invention;

9A and 9B are diagrams illustrating a change in the voltage level of the input node of the inverter with respect to the power supply voltage of the program circuit illustrated in FIG. 8; FIG. 9A illustrates a change in the voltage level when the power supply voltage rises steeply; FIG. 3B is a diagram showing a change in voltage level when the power supply voltage rises slowly.

FIG. 10 is a circuit diagram showing a conventional program circuit.

11A and 11B are diagrams showing a change in the voltage level of a node N1 with respect to the power supply voltage of the program circuit shown in FIG. 10, and FIG. 11A shows a change in the voltage level when the power supply voltage rises steeply; FIG. 7B is a diagram showing a change in voltage level when the power supply voltage rises slowly.

[Explanation of symbols]

1,11 capacitor, 3 fuse, 4 half latch circuit, 5,7 PMOS transistor, 6 inverter, 9 power supply, 100 SRAM, 101 memory cell array, 102A row redundant memory cell group, 102B column redundant memory cell group, 103 row address buffer , 10
4 column address buffer, 105 row decoder, 106
Column decoder, 107 word line driver, 108 multiplexer, 111A program circuit group, 111B
Program circuit group, 112 redundant row address decode circuit, 113 redundant column address decode circuit, 200,
400, 600, 800 program circuits.

Claims (5)

[Claims] 1. A program circuit for outputting an activation signal for using a redundant circuit, the program circuit being connected between a predetermined node and a ground, being disconnected when the redundant circuit is used, Disconnection / connection means connected when not used; activation signal generation means for generating the activation signal in response to the potential of the predetermined node; one end connected to a power supply; A switching unit that is turned on when a predetermined level is reached; one electrode is connected to the other end of the switching unit;
A program circuit provided in the semiconductor memory device, comprising: a first capacitor having the other electrode connected to the predetermined node. 2. The program circuit provided in the semiconductor memory device according to claim 1, further comprising a second capacitor having one electrode connected to said power supply and another electrode connected to said predetermined node. 3. The program circuit provided in the semiconductor memory device according to claim 1, further comprising a resistor having one end connected to said power supply and the other end connected to said predetermined node. 4. The program circuit provided in the semiconductor memory device according to claim 1, wherein said switching means is a MOS transistor. 5. The disconnection / connection means is a fuse.
A program circuit provided in the semiconductor memory device according to claim 1.