JPH10313426A - Motion detection solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a motion detecting solid-state image pickup device where eternal image processing is not required and a mobile body is detected with high performance through a simple configuration. SOLUTION: A motion detecting slid-state image pickup device 10 is provided with pixels 1 that provide an output of an electric signal is response to an incident light, vertical read lines 2a provided to each column of the pixels 21, a vertical scanning circuit 6 that transfers the electric signal from a specific row of the pixels 1 to the vertical read lines 2a in a prescribed timing, and horizontal scanning circuit 13 that transfers the electric signal to horizontal read lines 12. On each of the vertical read lines 2a is mounted a different value detection circuit 7 that stores the electric signal from the pixels 1 in a prescribed timing as an electric signal with respect to a just preceding frame and compares the electric signal with an electric signal with respect to a current frame outputted from the same pixels 1 in a succeeding prescribed timing to provide an output of the signal is placed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[Detailed description of the invention]

[0002]

2. Description of the Related Art Conventionally, image data is obtained from a large number of pixels arranged in a matrix, this image data is stored as a value in the immediately preceding frame, and then a value in the current frame is detected. There is known a motion detection image processing apparatus that compares moving images with each other to detect a moving object.

FIG. 16 shows a conventional motion detection image processing apparatus 200. This motion detection image processing apparatus 200 includes:
A solid-state imaging device 201 and an AD conversion circuit 202 for converting a video signal (analog signal) representing image data obtained by the solid-state imaging device 201 into a digital signal
An image memory (first image memory) 203 and an image memory (second image memory) 204 for storing digital signals from the AD conversion circuit 202;
The image processing circuit 205 obtains image data representing motion by comparing digital image data stored in the image data 3204 with each other.

That is, the motion detection image processing apparatus 200
First, after the video signal (analog signal) in the first frame obtained by the solid-state imaging device 201 is converted into a digital signal by the AD conversion circuit 202, the first image is converted into a video signal in the immediately preceding frame. It is stored in the memory 203. Next, the video signal (analog signal) obtained by the solid-state imaging device 201 in the second frame following the first frame (the immediately preceding frame) is
After being converted into a digital signal at 02, it is stored in the second image memory 204 as a video signal of the current frame.

The digital signal stored in the first image memory 203 by the image processing circuit 205 and the second
The magnitude of the digital signal stored in the image memory 204 is compared for each pixel, and the first frame (the immediately preceding frame) and the second frame (the current frame) are compared.
Pixels in which the difference between the compared digital signals is equal to or greater than a predetermined value are detected.

In this case, the first frame and the second frame are continuous, and the digital signal stored in the first image memory 203 is the luminance of each pixel of the solid-state imaging device 201 in the first frame. The digital signal corresponding to the signal and stored in the second image memory 204 corresponds to the luminance signal of each pixel of the solid-state imaging device 201 in the second frame.

Therefore, by comparing these two digital signals, the difference between the luminance signals between two consecutive frames (the immediately preceding frame and the current frame) can be detected, and only the moving object can be detected from the subject. . Then, by repeating the above operation, moving object detection can be performed continuously.

[0008]

However, when a moving object is detected using the above-described conventional motion detection image processing apparatus 200, the solid-state imaging device 201 outputs a video signal (analog signal), and then outputs an A / D conversion circuit. The digital signal is converted into a digital signal at 202 and then temporarily stored in the image memories 203 and 2.
04, the digital signal is stored, and the image processing circuit 205 performs a moving object detection process (comparison of the digital signal between the immediately preceding frame and the current frame) using the stored digital signal. The peripheral circuit of the solid-state imaging device 201 is complicated, and the motion detection image processing device 2
As a whole, there is a problem that it becomes expensive.

A signal corresponding to the incident light generated by each pixel (not shown) of the solid-state imaging device 201 is an analog signal, and thereafter, the analog-to-digital conversion circuit 20
2 was easily affected by noise. Further, in the conventional motion detection image processing apparatus 200, the effective range of the video signal (analog signal), that is, the dynamic range is limited by the input of the AD conversion circuit 202. Thus, the input dynamic range of the AD conversion circuit 202 depends on the solid-state imaging device 2.
Since the dynamic range is smaller than 01, the wide dynamic range of the solid-state imaging device 201 cannot be effectively used in the process of detecting a moving object.

In order to avoid the above-mentioned problems, a memory for storing the video signals of the immediately preceding frame and the current frame is provided for each pixel of the solid-state imaging device 201,
Further, it is conceivable to provide a circuit for comparing the video signal stored in the memory for each pixel to generate a signal representing a moving object for each pixel, but using such a method,
The structure of each pixel becomes complicated, causing a decrease in the aperture ratio of the solid-state imaging device 201 and a decrease in resolution, and there is a problem that it is impossible to respond to the increase in the number of pixels.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has no object to externally perform image processing in detecting a moving object, and has a simple structure and is capable of detecting a high-performance moving object. It is an object to provide a solid-state imaging device.

[0012]

According to a first aspect of the present invention, there is provided a motion detection solid-state imaging device, comprising: a plurality of pixels arranged in a matrix to output an electric signal according to incident light; A plurality of vertical read lines provided for each column of the plurality of pixels, and a vertical scan for selecting a specific row of the plurality of pixels and transferring an electric signal from the pixel to the vertical read line at a fixed timing; Means for storing an electric signal output from a pixel at a certain timing arranged on the vertical readout line as an electric signal for the immediately preceding frame and output from the pixel at the next certain timing with the stored electric signal. Signal comparing means for comparing the electric signal with respect to the current frame and outputting a signal representing the result of the comparison, and In which and a signal transfer means for transferring the sequentially horizontal output line a signal representing the force has been a result of the said comparison.

According to a second aspect of the present invention, in the solid-state imaging device for motion detection, the signal transfer unit includes a switch unit for connecting / disconnecting the vertical readout line and the horizontal readout line; And a horizontal scanning circuit that outputs a signal for controlling on / off.
In the solid-state imaging device for motion detection according to claim 3, signal charge accumulating means for accumulating electric charge according to a signal from the signal comparing means is arranged on the vertical readout line, and the switch means includes It is arranged between the signal charge storage means and the horizontal read line.

According to a fourth aspect of the present invention, in the solid-state imaging device for motion detection, the signal transfer means is arranged on the plurality of vertical read lines, and an input terminal thereof is connected to each of the plurality of vertical read lines. The shift register stores a signal output from each of the plurality of vertical read lines, and sequentially outputs the stored signal from its output terminal according to an external clock signal. It was made.

According to a fifth aspect of the present invention, in the motion-detecting solid-state imaging device, the pixel generates and accumulates a charge corresponding to the incident light, and the pixel responds to the incident light from the light detecting means. A charge holding unit for holding charges, a signal generating unit for generating an electric signal corresponding to the charges held in the charge holding unit, and connecting / disconnecting the signal generating unit of the pixel and the vertical read line. And connection separating means.

According to a sixth aspect of the present invention, in the solid-state imaging device for motion detection, the light detecting means includes a photoelectric conversion element that generates and accumulates a charge corresponding to incident light, and is provided on an output side of the photoelectric conversion element. Amplifying means of the pixel is connected, and the amplifying means outputs an electric signal corresponding to the charge when the charge corresponding to the incident light is held in the control region.
8. The solid-state imaging device for motion detection according to claim 7, wherein the pixel directly transfers a charge generated by the photoelectric conversion element to a control region of the amplification unit, and a control region of the amplification unit. Reset means for discharging the charge accumulated in the pixel to the outside of the pixel, wherein the connection / separation means connects / separates the amplification means of the pixel from the vertical readout line.

Further, in the solid-state imaging device for motion detection according to the present invention, the amplifying means is constituted by a junction field effect transistor, and the charge corresponding to the incident light is directly transferred to the gate. Thus, the current between the source and the drain is controlled to a value corresponding to the charge. According to a ninth aspect of the present invention, in the solid-state imaging device for motion detection, the connection / separation unit includes a switching MOS transistor interposed between a source of the junction field effect transistor and a vertical read line. Is what it is.

According to a tenth aspect of the present invention, in the solid-state imaging device for motion detection, the connection / separation means includes a capacitor connected to a gate of the junction field effect transistor, and one terminal of the capacitor is connected to one terminal of the capacitor. The connection / separation between the amplifying means and the vertical read line is performed by adding a connection / separation signal. 12. The motion detection solid-state imaging device according to claim 11, wherein the signal comparing unit determines that a magnitude of a difference between an electric signal value for the current frame and an electric signal value for the immediately preceding frame is a predetermined value. At the time, a signal indicating a logic low level or a logic high level is output.

In the solid-state imaging device for motion detection according to the twelfth aspect, the signal comparing means may include a first charge storage means for storing an electric signal for the immediately preceding frame, and an electric signal for the current frame. And an electric signal for the immediately preceding frame stored in the first charge storage means and an electric signal for the current frame stored in the second charge storage means. And outputs a signal indicating a logical low level or a logical high level when the magnitude of the difference is equal to or greater than a predetermined value.

In the solid-state imaging device for motion detection according to a thirteenth aspect, the first switch means is provided between the vertical readout line and the first charge storage means, and the first readout means is connected to the second readout line. Second switch means are respectively disposed between the first switch means and the second switch means, and charge storage control means is connected to the first switch means and the second switch means. When you select a row,
After transferring an electric signal corresponding to the electric charge stored in the control region of the amplification unit of the pixel using the connection separation unit to the vertical readout line as an electric signal for the immediately preceding frame, using the reset unit The charge accumulated in the control region of the amplifying unit is released to the outside of the pixel, and thereafter, the charge generated and accumulated in the photoelectric conversion element using the transfer unit is newly added to the control region of the amplifying unit. After that, an electric signal corresponding to the electric charge transferred to the control area is transferred to the vertical readout line as an electric signal for the current frame, and the electric charge accumulation control unit outputs the electric signal for the immediately preceding frame. Turning on the first switch means at the timing of appearing as electric charge on the vertical readout line and accumulating the electric charge in the first electric charge accumulating means; And turning on the second switching means at a timing at which an electric signal appears as a charge to the vertical readout line to the within the frame in which to accumulate the charges to the second charge storage means.

According to another aspect of the present invention, the signal comparing means is connected to a binarizing means having two input terminals and one input terminal of the binarizing means. A first sample-and-hold circuit, and a second sample-and-hold circuit connected to the other input terminal of the binarization means, and the first sample-and-hold circuit is used to electrically control the current frame. When the difference between the value of the signal and the value of the electric signal for the immediately preceding frame is higher than a first predetermined value, a signal indicating a logic high level or a logic low level is output, and the second sample-hold circuit is used. A logic high level or a logic low level when a difference between the value of the electrical signal for the current frame and the value of the electrical signal for the immediately preceding frame is higher than a second predetermined value. It is intended to output a signal indicative.

According to a fifteenth aspect of the present invention, in the motion detection solid-state imaging device, the pixel includes an embedded photodiode as photoelectric detection means for generating a charge corresponding to incident light.

(Operation) According to the first aspect of the present invention,
Since the signal comparing means provided for each of the plurality of vertical read lines compares the electric signal for the immediately preceding frame with the electric signal for the current frame, it is possible to easily generate a different value signal indicating an operation change, Further, since the generated different value signal is binarized and transmitted from the vertical read line to the output terminal via the horizontal read line, the binarized different value signal is transmitted when passing through the horizontal read line. Even if the value signal is affected by noise, the influence of the noise is smaller than in the case of an analog signal.

According to the second aspect of the present invention, the binarized different-value signal is output to the horizontal readout line by simply driving the switch means based on the driving signal from the horizontal scanning circuit. can do. According to the third aspect of the present invention, since the different value signal is temporarily stored in the signal charge storage means, the different value signal can be appropriately read from the output terminal by the signal transfer means.

According to the fourth aspect of the present invention, the different value signal binarized by the signal comparing means is stored in the register of the shift register, and then synchronized with the clock pulse input to the shift register. Then, the data can be output to the horizontal readout line. In this case, since the outlier signal is completely digitally processed, the operation can be further speeded up.

According to the invention described in claim 5, 1
An electric charge corresponding to the incident light generated and accumulated by the light detection means during one frame is held in the electric charge holding unit, and based on the held electric charge, an electric signal for the immediately preceding frame and a current frame are stored. Can be obtained. According to the invention described in claim 6, the electric charge generated and accumulated in the photoelectric conversion element during one frame is held in the control region of the amplifying means, and based on the held electric charge, And an electric signal for the current frame can be obtained.

According to the present invention, the electric charge generated and stored in the photoelectric conversion element can be directly and simply supplied to the control region of the amplifying means, so that the electric charge is supplied via the signal line. In the transfer process, signal deterioration due to charge distribution is reduced as compared with the case where the signal is transferred to the control region. Also,
According to the eighth aspect of the present invention, only by directly supplying the charge generated and accumulated by the photoelectric conversion element to the control region of the junction field-effect transistor, the electricity corresponding to the charge supplied to the gate is obtained. The signal can be output as two signals, an electrical signal for the immediately preceding frame and an electrical signal for the current frame. Also in this case, by directly transferring the charge to the gate, deterioration of the signal due to the charge distribution can be suppressed as compared with the case where the charge is transferred via the signal line.

According to the ninth aspect of the present invention, connection / disconnection between the pixel and the vertical readout line can be easily performed.
According to the tenth aspect of the present invention, the connection / separation between the pixel and the vertical read line is performed by capacitive coupling,
Compared to the case where an OS transistor or the like is used, the configuration is simplified, and the size of the entire pixel can be reduced.

According to the eleventh aspect of the present invention,
By setting the predetermined value in accordance with the motion to be detected when generating the outlier signal, a desired motion can be detected. According to the twelfth aspect of the present invention, the electric signal sequentially output from the pixel is used as the electric signal for the immediately preceding frame and the electric signal for the current frame, and the first electric signal is arranged on the vertical readout line. Different value signals can be obtained only by storing the signals in the charge storage means and the second charge storage means and comparing the stored signals with each other.

According to the thirteenth aspect of the present invention,
The electric signal output from the pixel at a certain timing is stored in the first charge storage means at a desired timing, and is stored as an electric signal for the immediately preceding frame. The electric signal output from the same pixel at the next certain timing Can be stored in the second charge storage means at a desired timing, and this can be stored as an electric signal for the current frame as appropriate.

According to the fourteenth aspect of the present invention,
The value held in the first sample and hold circuit is a value reflecting the electric signal for the immediately preceding frame and the first predetermined value, and the value held in the second sample and hold circuit is the value for the immediately preceding frame. Since a value reflecting the electric signal and the second predetermined value can be set, a threshold value used for determining the magnitude relationship between the electric signal for the current frame and the electric signal for the immediately preceding frame can be set freely.

According to the fifteenth aspect of the present invention,
In the photoelectric conversion element of each pixel, the depletion layer generated at the pn junction of the photodiode does not reach the pixel surface, so that dark current is suppressed.

[0033]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) Hereinafter, a first embodiment will be described with reference to FIGS. The first embodiment corresponds to claims 1 to 3, claims 5 to 9, claims 11 to 13, and claim 15.

FIG. 1 is a schematic circuit diagram showing a schematic configuration of a solid state imaging device 10 for motion detection according to the first embodiment. still,
In the first embodiment, to simplify the description, 4
Description will be made using an example in which two pixels 1, 1, 1, 1 are arranged in a matrix. First, the outline of the motion detection solid-state imaging device 10 will be described.

In the solid state imaging device 10 for motion detection, the pixels 1, 1, 1, 1 are arranged in a matrix as described above.
The vertical readout lines 2a, 2 corresponding to the pixels 1, 1,.
b. Further, a specific row is selected for the pixels 1, 1,... And an electric signal corresponding to the incident light from the pixels 1, 1,... Is transferred to the corresponding vertical readout lines 2a, 2b at a fixed timing. A vertical scanning circuit 6 is connected via clock lines 3a, 3b, 4a, 4b, 5a, 5b and the like. Note that these vertical scanning circuits 6,
The clock lines 3a, 3b, 4a, 4b, 5a, 5b and the like constitute vertical scanning means.

The vertical read lines 2a and 2b provided for each column are connected to the horizontal value through an alien value detection circuit 7 and n-channel type horizontal read switch MOS transistors (switch means) QH1 and QH2. The read line 12 is connected. And MO for horizontal readout switch
The horizontal scanning circuit 13 connects the horizontal selection signal lines 11 to the gates of the S transistors (switching means) QH1 and QH2.
a and 11b.

Further, a capacitor (signal charge storage means) C for storing a different value signal is connected to the vertical readout lines 2a and 2b.
O1 and CO2 are connected. The vertical read line 2
When an electric signal corresponding to incident light is output from each of the pixels 1, 1,... to each of the vertical readout lines 2a, 2b at a fixed timing, the outlier detection circuit 7 disposed in each of The electric signal is stored as an electric signal for the immediately preceding frame, and the stored electric signal is compared with the electric signal for the current frame output from the same pixel 1, 1,... At the next fixed timing. It outputs a signal (different value signal) representing the result.

The different value signal output from the different value detection circuit 7 is temporarily stored in the different value signal storage capacitors CO1, C
When the switching MOS transistors QH1 and QH2 are turned on by the drive pulses φH1 and φH2 stored in O2 and transmitted from the horizontal scanning circuit 13 via the horizontal selection signal lines 11a and 11b,
The output buffer amplifier 1 is transferred to the horizontal read line 12 and
5 through an output terminal VO.

Next, a specific circuit configuration of each pixel 1, 1, 1, 1 of the solid-state imaging device 10 for motion detection, and connection relations with the vertical readout lines 2a, 2b, clock lines 3a, 3b,. Will be described with reference to FIG. Pixels 1, 1, 1, 1 are photodiodes (photodetectors; photoelectric conversion elements) PD that generate and accumulate charges corresponding to incident light.
And an amplifying transistor (amplifying means; in this embodiment, an n-channel junction type electric field) which outputs an analog signal corresponding to incident light between its source and drain in accordance with the charge supplied to the control region (gate). Effect transistor JFE
T) a p-channel transfer MOS for directly and selectively transferring the charge generated and accumulated by the photodiode PD to the control region of the amplifying transistor QA.
A transistor (transfer means) QT, a p-channel type reset MOS transistor (reset means) QP for resetting charges in a control region of the amplification transistor QA, an amplification transistor QA, and the vertical read lines 2a and 2b. Amplifying transistor Q provided between
It is composed of a source of A and an n-channel type pixel separating MOS transistor (connection separating means) QX for separating / connecting the vertical readout line 2a or 2b.

By transferring the charges directly to the gate (control region) as described above, the deterioration of the signal due to the charge distribution during the transfer can be suppressed as compared with the case where the charges are transferred via another signal line. Thus, the image S / N ratio of the motion detection solid-state imaging device 10 is improved.

In each of the pixels 1, 1, 1, 1, a signal (signal charge) corresponding to the incident light detected by the photodiode PD is supplied to the gate (control region) of the amplifying transistor QA. The current is amplified by the source follower operation, and the electric signal is thereafter read out to the corresponding vertical readout lines 2a and 2b. In this case, the source of each amplifying transistor QA is commonly connected to the vertical read line 2a or 2b for each column arranged in a matrix via the pixel separating MOS transistor QX. The power supply voltage V is applied to the drain of each amplifying transistor QA and the cathode of the photodiode PD.
D (positive) is applied.

The source and drain of the transfer MOS transistor QT are connected to the anode side of the photodiode PD and the gate (control region) of the amplification transistor QA. Further, the transfer MOS transistor Q
The transfer gate of T is connected to the clock lines 3a, 3b for each row of the pixels 1, 1, 1, 1 arranged in a matrix.
And the driving pulse φTG transmitted from the vertical scanning circuit 6 connected to the clock lines 3a and 3b.
1, φTG2, the drive pulse φTG1,
Transfer MOS transistor Q according to the level of φTG2
T operates sequentially for each row.

The reset MOS transistor QP
Supply voltage VRD is applied to each pixel 1, 1, 1,
The common voltage is applied to each of them and the voltage is applied.
The gate of the reset MOS transistor QP is
Clock lines 4a, 4b connected to vertical scanning circuit 6
, And its source is shared with the source of the transfer MOS transistor QT.

Then, the drive pulse φ from the vertical scanning circuit 6 is applied to the gate of the reset MOS transistor QP.
When RG1 and φRG2 are given, the reset MOS
The transistor QP is driven by the driving pulses φRG1, φRG
It operates according to the second level. Also,
The gate of the pixel separating MOS transistor QX is provided for each row of the pixels 1, 1, 1, 1 arranged in a matrix.
The pixel separating MOS transistors QX are commonly connected to the clock lines 5a and 5b, and operate sequentially for each row in accordance with the levels of the driving pulses φPX1 and φPX2 from the vertical scanning circuit 6.

The vertical read lines 2a, 2b
In the middle of the process, a different value detection circuit (signal comparing means) 7 is provided for each column.
Is arranged. The different value detection circuit 7 is connected to different value signal storage capacitors (signal charge storage means) CO1 and CO2 via switching MOS transistors (n-channel type) QO1 and QO2, respectively.

Further, the different value signal storage capacitor CO
1 and CO2 are connected to a horizontal read line 12 via n-channel type horizontal read switch MOS transistors (switch means) QH1 and QH2. The gates of the switching MOS transistors QO1 and QO2 are connected to a node 19 on a drive pulse generating circuit (not shown) side via a clock line 19a, and receive a drive pulse φTO supplied from the drive pulse generating circuit. The switching MOS transistors QO1,
QO2 operates.

Also, the horizontal readout switch MOS
The gates of the transistors QH1 and QH2 are connected to horizontal selection signal lines 11a and 11b connected to the horizontal scanning circuit 13.
And reads out signals (controls horizontal reading) stored in the different value signal storage capacitors CO1 and CO2 in accordance with the levels of the driving pulses φH1 and φH2 supplied from the horizontal scanning circuit 13. Will be

In this case, what is read out to the horizontal read line 12 is a signal output from the outlier detection circuit 7 (an outlier signal representing the difference between an electric signal between the immediately preceding frame and the current frame, which will be described in detail later). ), And the different value signals are sequentially output from the output terminal VO via the output buffer amplifier 15. Further, a reset switch MOS transistor (n-channel type) Q
The drain of RSH is connected.

The source of the reset switch MOS transistor QRSH is grounded, and the gate thereof is
It is connected to a node 14 on the side of a drive pulse generation circuit (not shown) via a clock line 14a. Then
The reset switch MOS transistor QRSH
Is the drive pulse φRSH from the drive pulse generation circuit.
It is designed to work according to the level.

As shown in the lower part of FIG. 1, a reset switch MOS transistor (n-channel type) QRSV is connected to each of the vertical read lines 2a and 2b.
1, the drains of QRSV2 and the constant current sources 17a, 17
b is connected. In this case, the sources of the reset switch MOS transistors QRSV1 and QRSV2 are grounded, and the constant current sources 17a and 17b are connected to the power supply voltage VC.
(Negative) is supplied.

The gates of the reset switch MOS transistors QRSV1 and QRSV2 are connected to a node 16 on a drive pulse generating circuit (not shown) side via a clock line 16a. The reset switch MOS transistors QRSV1 and QRSV2 operate according to the level of the drive pulse φRSV supplied through the switch.

As shown in FIG. 1, the above-mentioned outlier detection circuit 7 is arranged corresponding to each of the vertical read lines 2a and 2b.
Similarly to the transistor (first switch means) QR, an n-channel type switching MOS transistor (second switch means) QS and an electric signal corresponding to incident light output from the pixel 1, 1, 1, 1 A first signal storage capacitor (first charge storage means) CR and a second signal storage capacitor (second charge storage means) CS for storing, and first and second signal storage capacitors CR and CS And a different value detector XA that outputs a logical high level or low level signal (a different value signal) when the stored electric signals are different from each other.

In the thus configured outlier detection circuit 7, an outlier signal (digital signal) is output from the outlier detector XA as an output signal.
More specifically, as shown in FIG. 1, in the different value detection circuit 7, the vertical read lines 2a and 2b are respectively connected to two read lines 2a-1, 2a-2 and 2b-1, at nodes n1 and n2. 2
It is branched to b-2.

Then, each of the vertical read lines 2a, 2b
One terminal of the first signal storage capacitors CR, CR is connected to the read lines 2a-1, 2b-1 on the downstream side of the switching MOS transistors QR, QR. In this case, the other terminals of the first signal storage capacitors CR, CR are grounded. Further, the switching MOS transistors QS, QS of the respective vertical read lines 2a, 2b
One terminal of the second signal storage capacitors CS, CS is connected to the read lines 2a-2, 2b-2 on the downstream side of. In this case, the second signal storage capacitors CS,
The other terminal of CS is grounded.

The read lines 2a-1 and 2a-2 on the vertical read line 2a side are respectively connected to two input terminals of the different value detector XA, while the read lines 2b-1 on the vertical read line 2b side are connected. , 2b-2 are respectively connected to two input terminals of the different value detector XA. The gates of the switching MOS transistors QR, QR are connected to a node 8 of a drive pulse generating circuit (charge storage control means) (not shown) via a clock line 8a, and the gates of the switching MOS transistors QS, QS are connected. Is connected to a node 9 on the side of a drive pulse generating circuit (not shown) via a clock line 9a. The switching MOS transistors QR, QR and the switching MOS transistors QS, QS operate according to the levels of the drive pulses φTR, φTS supplied from the drive pulse generation circuit.

Next, the operation of the solid-state imaging device for motion detection 10 having the above configuration will be described with reference to a timing chart shown in FIG. In FIG. 2, one pixel 1 that detects incident light at a certain timing detects incident light in two consecutive frames, that is, the (N−1) th frame (the immediately preceding frame) and the Nth frame (the current frame). The case where the read operation is performed upon detection is shown.

The pixels 1 arranged in a matrix are
The reading operation of the pixels 1 and 1 in the same row among 1, 1 and 1 is the same, and the period t10 to t15 of the (N-1) th frame or the Nth frame in FIG. In the operation, a period from t20 to t25 indicates the readout operation of the pixel 1 in the second row. Hereinafter, the read operation of the pixel 1 in the first row in the N-th frame (current frame) will be mainly described. Accordingly, the description will be made from the time when the period t10 of the Nth frame in the timing chart of FIG. 2 has been reached. Note that the read operation in the (N-1) th frame is the same as the read operation in the Nth frame described below.

Before the period t10 in the Nth frame (at the end of the period t25 in the (N-1) th frame), the driving pulse φ
TG1 and TG2 are both held at a high level, drive pulses φPX1 and φPX2 are both held at a low level, and drive pulses φRG1 and φRG2 are both held at a high level. In addition, drive pulses φRSV, φTR, φTS
Is held at a low level, and the drive pulse φTO is held at a low level. In addition, drive pulses φH1, φH
2, φRSH is held at a low level.

As described above, before the period t10, since the driving pulses φTG1 and φTG2 are at the high level, the transfer MOS transistor QT is turned off, and the driving pulse φR
Since G1 and φRG2 are at a high level, the reset MO
The S transistor QP is off.

Therefore, the gate (control region) of the amplifying transistor QA is set in a floating state. However, due to the effect of the parasitic capacitance, the gate (control region) is already turned on when each transfer MOS transistor QT is on in the immediately preceding N-1 frame. M for transfer
Each amplifying transistor Q via the OS transistor QT
The charge (first signal charge) corresponding to the incident light generated by each photodiode PD transferred to the gate (control region) of A is amplified by each amplifier even after the transfer MOS transistor QT is turned off. The state is held at the gate (control region) of the transistor QA. Thus, the amplifying transistor QA outputs an electric signal according to the gate voltage by the source follower operation until the charge stored in the gate (control region) is reset.

After the transfer MOS transistor QT is turned off, a charge (second signal charge) is newly generated and stored in each photodiode PD according to the incident light. The first signal charge at this time is the photodiode P
D is a charge corresponding to the incident light in the (N-1) th frame (the immediately preceding frame) generated and stored in D, and the second signal charge is generated in and stored in the photodiode PD in the Nth frame.
The electric charges corresponding to the incident light in the frame (current frame).

Before the period t10, the driving pulse φ
Since PX1 and φPX2 are at low level, the pixel separation M
The OS transistor QX is off, and each pixel 1 is separated from the vertical readout lines 2a and 2b. At this time, since the drive pulse φRSV is at a low level, the reset switch MOS transistor QRSV
1 and QRSV2 are both off.

Since the driving pulses φTR and φTS are both at low level, the switching MOS transistors QR and Q
S is turned off, and the electric signals on the vertical read lines 2a and 2b are transferred to the first and second signal storage capacitors CR and
It is not supplied to any of the CSs.

Since the driving pulse φTO is at a low level, the switching MOS transistors QO1 and QO2 are turned off, so that the electric signal from the different value detection circuit 7 is not supplied to the different value signal storage capacitors CO1 and CO2. It has become. Next, when the period t10 is reached, the drive pulse φRSV, the drive pulse φTR, and the drive pulse φTS
Is inverted from a low level to a high level.

At this time, the reset switch MOS transistors QRSV1 and QRSV2 are turned on, and the switch M
When the OS transistors QR and QS are turned on, the first signal storage capacitor CR and the second signal storage capacitor C
The electric charges remaining in S are discharged. At the end of the period t10, that is, at the start of the period t11, the driving pulse φRSV is inverted to a low level, and the driving pulse φTS
Is also inverted to low level. These drive pulses φRS
V and the inversion of the drive pulse φTS turn off the reset switch MOS transistors QRSV1 and QRSV2 and the switch MOS transistor QS. At this time, the switching MOS transistor QR remains on.

In the period t11, the driving pulse φ
PX1 is inverted to high level. This drive pulse φP
By the inversion of X1, the pixel separating MOS transistor QX of each pixel 1 in the first row is turned on, and the source of the amplifying transistor QA is the vertical readout line 2a,
2b and turned on (selected). At this time, the first
The gate (control region) of the amplifying transistor QA of each pixel 1 in the row already has the (N-th-
Since the first signal charge corresponding to the incident light is transferred (in the period t13 of one frame) and the first signal charge is held even after the transfer MOS transistor QT is turned off, the first signal charge is held. An electric signal corresponding to the first signal charge is output to the vertical read lines 2a and 2b.

As described above, during the period t11, the reset switch MOS transistors QRSV1 and QRSV1
Since SV2 is off, each amplifying transistor QA in the first row selected in this period t11
Performs a source follower operation, the potential of the source becomes
The current (drain current) flowing between the source and drain is
It rises until it reaches IB (current value flowing through the constant current sources 17a and 17b).

At this time, as described above, each of the amplifying transistors QA in the first row has, at its gate (control region), a period t1 of the immediately preceding frame (the (N-1) th frame).
In 3), the first signal charge is transferred, and after the transfer is completed (the transfer MOS transistor QT is off), the gate voltage is maintained. Therefore, the first output corresponding to the first signal charge is performed by the source follower operation. Signal (a first electric signal), and the first output signal is output during the period t11.
Then, the first signal storage capacitor CR is charged through the switching MOS transistor QR already turned on.

At this time, with respect to each amplifying transistor QA in the second row, since the drive pulse φPX2 is still at a low level, each pixel separating MOS transistor QX in the second row is off. The source of each amplifying transistor QA in the second row is connected to the vertical read line 2.
a, 2b are not connected (not selected).
Then, at the end of the period t11, that is, when the period t12 is reached, the driving pulse φRG1 is inverted to a low level, and the driving pulse φTR is inverted to a low level.

When the driving pulse φTR goes low, the switching MOS transistor QR is turned off, and the first signal storage capacitor CR is brought into a floating state to hold the first output signal as it is. As described above, in this period t11, the first output signal held in the first signal storage capacitor CR is the immediately preceding frame (the period t13 of the (N-1) th frame).
The first signal charge is transferred via the transfer MOS transistor QT, and the output of the amplification transistor QA whose first signal charge is held in the gate (control region) even after the transfer MOS transistor QT is turned off. (Output signal of the amplifying transistor QA when the current flowing between the source and drain becomes IB due to the source follower operation).

Assuming that the first output signal is VSS1,
The value of VSS1 is a value represented by the following equation (1). VSS1 = VRD + VS1-VT (1) where VRD is the reset MOS in the (N-1) th frame.
Power supply voltage supplied when the transistor QP is on,
VS1 is the rise of the gate potential of the amplifying transistor QA according to the first signal charge in the (N-1) th frame,
T is a voltage between the gate and the source when the drain current of the amplifying transistor QA is IB. Note that the value of VS1 is obtained by (first signal charge / gate capacitance according to incident light).

In the period t11, the driving pulse φ
Since TR is at a high level (the switching MOS transistor QR is on), the first signal storage capacitor CR
At both ends becomes the potential VSS1 represented by the equation (1) charged in the period t11. Note that this potential VSS1
By the time the drive pulse φTR is inverted to the low level at the end of the period t11 (at the start of the period t12), the first switching pulse is turned off and the switching MOS transistor QR is turned off.
Is charged in the signal storage capacitor CR, and its value VSS
1 is held.

Returning to the description of FIG. 2, in the period t12 after the end of the period t11, when the drive pulse φRG1 becomes low level, each reset MOS transistor QP in the first row is turned on, and the power supply voltage VRD ( The read level is transmitted to the gate (control region) of each amplifying transistor QA in the first row. By turning on the reset MOS transistor QP, the amplification transistor Q
The first signal charge is discharged from the gate (control region) of A, and the gate (control region) of the amplifying transistor QA is connected to the power supply voltage VRD (read level).
Biased.

At the end of the period t12, that is, when the period t13 is reached, the drive pulse φTG1 is inverted to a low level,
The drive pulse φRG1 is inverted to a high level. When the drive pulse φRG1 goes high, the first
Each resetting MOS transistor QP in the row is turned off again, and the gate (control region) of the amplifying transistor QA in the first row is set in a floating state. Voltage V
The state of being kept biased at RD (read level) is maintained.

On the other hand, when the drive pulse φTG1 goes low, the transfer MOS transistor QT of each pixel 1 in the first row is turned on, and is generated and accumulated in the photodiode of each pixel 1 in the first row. The charge (second signal charge) corresponding to the incident light is transferred to the gate (control region) of the amplification transistor QA of each pixel 1 in the first row. This second signal charge becomes a signal charge corresponding to the incident light in the Nth frame.

When charges (second signal charges) corresponding to the incident light in the N-th frame (current frame) are transferred to the gate (control region) of the amplification transistor QA in this manner, each amplification transistor QA Since the gate potential of QA rises by the amount of the transferred charges, the amplifying MOS transistor QA in the first row performs a source follower operation, and the potential of the source of the amplifying transistor QA rises by the rise of the gate potential. Just rise.

In this case, a second output signal (second electric signal) corresponding to the second signal charge is turned on at this time from each amplifying transistor QA in the first row performing the source follower operation. Is output to the vertical readout lines 2a and 2b via the pixel separating MOS transistor QX. At the end of the period t13, that is, at the start of the period t14, the driving pulse φTG1 is inverted to a high level, and the driving pulse φT
S, the drive pulse φTO is inverted to a high level.

When the drive pulse φTG1 goes high, each transfer MOS transistor QT in the first row is turned off, and the incident light generated and accumulated in the photodiode PD of the pixel 1 in the first row is turned off. Transfer of the corresponding charge (second signal charge) to the gate (control region) of the amplifying transistor QA ends, and the gate (control region) of the amplifying transistor QA is again brought into a floating state. Due to the effect of the capacitance, the state is maintained while the potential of the gate is increased by the amount of the transferred charge (second signal charge).

Meanwhile, in the Nth frame, the charge transferred to the gate (control region) as the second signal charge for the current frame is reset in the next (N + 1) th frame (not shown). (Until the reset MOS transistor QP is turned on). As a result, the charge accumulated in the gate at this time is used as the first signal charge (charge for the immediately preceding frame) in the (N + 1) th frame.

As described above, the transfer MOS transistor QT
Is turned on, the second signal charge is once transferred to the gate (control region) of the amplification transistor QA, and then, even if the transfer MOS transistor QT is turned off, the second signal charge is transferred to the gate ( (A control amount region), the source follower operation from the amplifying transistor QA until the gate is reset (period t14 and thereafter) corresponds to the charge (second signal charge) accumulated in the gate. A signal (voltage signal) is output.

When the driving pulse φTS goes high, the switching MOS transistor QS is turned on, and the source follower operation causes the second transistor charge in the gate to store the second signal charge. The second output signal output from the QA is charged to the second signal storage capacitor CS via the pixel separating MOS transistor QX and the vertical readout lines 2a and 2b which are in the ON state.

In this period t14, when the current flowing between the source and the drain becomes IB due to the source follower operation, the value of the potential of the source of the amplifying transistor QA (second output signal; denoted as VSS2) VSS2 is , The value shown in the following equation (2). VSS2 = VRD + VS2-VT (2) Here, VS2 is an increase in the gate potential of the amplifying transistor QA according to the second signal charge. The value of VS2 is the same as that of VS1 described above (the second value corresponding to the incident light).
Signal charge / gate capacitance).

In this period t14, since the driving pulse φTS is at the high level (the switching MOS transistor QS is turned on), both ends of the second signal storage capacitor CS are charged during the period t14. It becomes the potential VSS2 represented by the equation (2). Note that this potential V
SS2 is at the end of period t14 (at the start of period t15)
By the time the drive pulse φTS is inverted to a low level and the switching MOS transistor QS is turned off, the second signal storage capacitor CS is charged.

As described above, the second output signal (voltage signal) represented by the equation (2) is stored and held in the second signal storage capacitor CS. As described above, the first output signal (voltage signal) represented by the equation (1) is stored and held in the capacitor for use CR. Then, the stored second output signal (voltage signal) and first output signal (voltage signal) are input to the different value detector XA.

As will be described later in detail, the different value detector XA outputs a first output signal (analog signal) and a second output signal (analog signal).
Output signal (digital signal) whose output is high level (logic level high level) or low level (logic level low level) only when the difference from the output signal (analog signal) is equal to or greater than a predetermined value. Is output.

In the period t14, the driving pulse φ
When TO goes high, the switching MOS transistors QO1 and QO2 are turned on. The different value signal output from the different value detector XA is charged to the different value signal storage capacitors CO1 and CO2 via the ON switching MOS transistors QO1 and QO2. Next, at the end of the period t14, that is, at the start of the period t15, the driving pulse φPX1, the driving pulse φTS, and the driving pulse φTO are inverted to low level.

As described above, when the drive pulse φPX1 goes low, the pixel separating MOS transistor QX is turned off, and the pixels 1, 1 in the first row are separated from the vertical readout lines 2a, 2b. You. When the driving pulse φTS goes low, the switching MO
The S transistor QS is turned off.

When the drive pulse φTO goes low, the switching MOS transistors QO1,
QO2 is turned off, and the capacitor CO for storing a different value signal is turned off.
Since the first and CO2 are in a floating state, the different value signal is held in the different value signal storage capacitors CO1 and CO2. After the above state at the beginning of the period t15,
In the period t15, the drive pulse φH1 from the horizontal scanning circuit 13 further rises to a high level for a certain period of time, and is thereafter kept at a low level. The driving pulse φ
With respect to H2, after the drive pulse φH1 is held at a low level, the drive pulse φH1 is raised to a high level for a predetermined period at predetermined intervals, and thereafter held at a low level. Further, the drive pulse φRSH is raised to a high level for a certain period of time after the drive pulse φH1 falls to a low level and before the drive φH2 rises, and is thereafter kept at a low level. Pulse φH2
Falls to a low level, then rises again to a high level for a certain period of time, and is thereafter kept at a low level.

When the drive pulse φH1 is switched to the high level, the different value signal held in the different value signal storage capacitor CO1 is read out to the horizontal readout line 12, and the output buffer amplifier 15 is turned on. Through,
The signals are sequentially output to the output terminal VO.

Subsequently, when the reset switch MOS transistor QRSH is turned on by the high-level switching of the drive pulse φRSH, the horizontal read line 12 is reset (initialized). This reset occurs because the parasitic capacitance of the horizontal read line 12 causes a part of the voltage signal to be retained in the horizontal read line 12 when the voltage signal is read out to the horizontal read line 12. This is to eliminate the electric signal that is present. After the electric signal is eliminated, the drive pulse φRSH is inverted to a low level.

Then, by the subsequent high-level switching of the driving pulse φH2, the different value signal held in the different value signal storage capacitor CO2 is read out to the horizontal readout line 12, and is output via the output buffer amplifier 15 to The signals are sequentially output to the output terminal VO. Finally, when the drive pulse φRSH switches to the high level again, the reset switch MOS
The transistor QRSH is turned on, the horizontal read line 12 is reset (initialized) again, and then the drive pulse φRSH is inverted to a low level.

Note that, due to the influence of the parasitic capacitance of the horizontal read line 12, the voltage signal (different value signal) read to the horizontal read line 12 takes a long time until its waveform is distorted and reaches a steady state. In the present embodiment, since the electric signal (different value signal) appearing on the horizontal read line 12 is binarized (digitized), even if it does not reach the steady state, it reaches a certain level (threshold level of the logic circuit).
When the threshold value is reached, it is possible to determine whether the logical level is a high level or a low level, and the reading operation is speeded up.

In the subsequent period t20 to t25, the second
The period t10 to t1 described above is applied to the pixels 1 and 1 in the row.
5, the same operation as the readout operation of the pixels 1 and 1 in the first row is repeatedly performed.
, The different value signal (digital signal) in the Nth frame is sequentially output from the output terminal VO.

As described above, each pixel 1, 1, 1, which is obtained according to the incident light and obtained between two consecutive frames (the (N-1) th frame and the Nth frame), respectively.
The analog signal (electric signal indicating luminance) from 1 is
The respective pixels 1, 1, 1 and 1 output signals (different value signals) when the magnitude of the difference is equal to or greater than a certain value.

As described above, two consecutive frames (N-th frame)
Moving object detection can be performed by detecting pixels in which the difference between the electric signals (luminance signals) obtained between the 1st frame and the Nth frame is different. Then, by repeatedly performing the above operation, the moving object can be detected between two or more consecutive frames.

Next, the specific configuration and operation of the above-described outlier detection circuit 7 will be described in detail with reference to FIG. FIG. 3 shows a vertical readout line 2a and clock lines 8a and 9 in the motion detection solid-state imaging device 10 shown in FIG.
a, 10a, switching MOS transistors QR, Q
FIG. 3 is a circuit diagram showing S, QO1, and an outlier detection circuit 7;

As shown in FIG. 3, the different value detector XA of the different value detector 7 has two voltage comparators AP1 and AP2.
And an OR operator OR. The voltage comparator AP1 has a non-inverting input terminal,
The read line 2a-1 and one terminal of the first signal storage capacitor CR connected thereto are connected, and the read line 2a-2 is connected to its inverting input terminal.
And one terminal of the second signal storage capacitor CS connected thereto.

The voltage comparator AP2 has its non-inverting input terminal connected to the read line 2a-2 and one terminal of the second signal storage capacitor CS connected thereto. The readout line 2a-1 and one terminal of the first signal storage capacitor CR connected to the readout line 2a-1 are connected to the inverting input terminal.

Then, the above-mentioned two voltage comparators AP
The outputs of AP1 and AP2 are both connected to two input terminals of a logical sum OR, and the output of the logical sum OR is an output of the different value detection circuit 7. Next, the outlier detection circuit 7
Will be described again with reference to FIG.
Here, only those related to the operation of the different value detection circuit 7 will be described.

As described above, in the period t10 shown in FIG. 2, since the pixel separating MOS transistor QX is off (the driving pulse φPX1 is at the high level), each pixel 1, 1, 1, 1 is vertically It is separated from the read lines 2a and 2b. Then, in this period t10, the charges stored in the first and second signal storage capacitors CR and CS are eliminated as described above.

In the next period t11, the electric signal from the amplifying transistor QA is supplied to the first signal storage capacitor CR.
(First output signal VSS1). Period t12
Thus, the electric signal stored in the gate of the amplification transistor QA is reset as described above. And
In a period t13, the signal charge newly generated and accumulated in the photodiode PD is transferred to the gate (control region) of the amplifying transistor QA, and an electric signal corresponding to the signal charge is transferred from the pixel 1 to the vertical read line. 2a and 2b.

In the next period t14, the electric signal transferred to the vertical read lines 2a and 2b is stored in the second signal storage capacitor CS via the switching MOS transistor QS (at this time, on). (The second output signal VSS2). By the way, in this period t14, as described above, the first output signal VSS1 is already stored and held in the first signal storage capacitor CR.
The first output signal VSS1 is supplied to a non-inverting input terminal of the voltage comparator AP1 and an inverting input terminal of the voltage comparator AP2.

Then, during this period t14, when the second output signal VSS2 is newly stored and held in the second signal storage capacitor CR, the second output signal VSS2
2 is input to the non-inverting input terminal of the voltage comparator AP2 and the inverting input terminal of the voltage comparator AP1. As a result, in the different value detection circuit 7, the voltage comparator AP1 and the voltage comparator AP
2, the magnitudes of the first output signal VSS1 and the second output signal VSS2 are separately compared.

At this time, the first output signal VSS1 is expressed by the above equation (1), and the second output signal VSS2
Is represented by the above equation (2). Therefore, the voltage comparator AP1 and the voltage comparator AP2 use the following equation (3).
The difference between the first output signal VSS1 and the second output signal VSS2 is determined. VSS1−VSS2 = (VRD + VS1−VT) − (VRD + VS2−VT) = VS1−VS2 (3) Thus, the magnitudes of the first output signal VSS1 and the second output signal VSS2 are compared. This means that the luminance of the incident light in the (N-1) th frame (corresponding to VS1) in the specific pixel 1 changes from the luminance of the incident light in the Nth frame (VS2), that is, the luminance of the luminance between two consecutive frames. Synonymous with detecting a change.

By the way, both the voltage comparator AP1 and the voltage comparator AP2 for comparing the value shown in the above equation (3) are different from the signal input to the non-inverting input terminal in the signal input to the inverting input terminal. If it is higher, the power supply voltage level (high level) is output. If the signal input to the non-inverting input terminal is equal to or smaller than the signal input to the inverting input terminal, the ground level (low level) is output. Is output.

Therefore, when the first output signal VSS1 is larger than the second output signal VSS2, the voltage comparator AP
1 becomes the power supply voltage level (high level), and conversely, the second output signal VSS2 becomes the first output signal VSS1.
If it is larger, the output of the voltage comparator AP2 becomes the power supply voltage level (high level). When the first output signal VSS1 is equal to the second output signal VSS2,
The outputs of the voltage comparators AP1 and AP2 are both at the ground level (low level).

The voltage comparator AP thus obtained
The outputs of AP1 and AP2 are both input to an OR operator OR to perform an OR operation. In this case, the first output signal VS
Only when the magnitudes of S1 and the second output signal VSS2 are different (either one is larger or smaller than the other), the output of the OR operator OR, that is, the different value detector XA, is at a high level (logic level high). Level).

When the magnitudes of the first output signal VSS1 and the second output signal VSS2 are equal, the output of the logical sum operation unit OR, that is, the different value detector XA is at low level (logic level is low level). Becomes It is known that the value of VT (gate-source voltage) in the above formulas (1) and (2) varies from one amplification transistor QA to another and causes so-called fixed pattern noise.
However, as shown in the above equation (3), when detecting an outlier, that is, when calculating the difference between the first output signal VSS1 and the second output signal VSS2, the outlier signal is a VT value. , It is possible to perform outlier detection (moving object detection) without being affected by fixed pattern noise.

It is known that the first output signal VSS1 and the second output signal VSS2 usually include a random noise component in addition to the fixed pattern noise component. Therefore, when detecting a different value, an erroneous signal may be generated due to these random noise components.

However, in the present embodiment, the voltage comparator AP1 and the voltage comparator AP2 are connected to the signal voltage input to the non-inverting input terminal in order to prevent the generation of an erroneous signal due to the random noise component. The output is inverted when the difference between the signal voltages input to the input terminals exceeds a certain threshold voltage. FIG. 4 is a characteristic diagram illustrating an example of input / output characteristics of the voltage comparators AP1 and AP2 included in the outlier detector XA according to the present embodiment.

In FIG. 4, the voltage ΔH is a threshold voltage and is set so as to be sufficiently larger than the magnitude of a normal random noise component. V1 is a voltage comparator A
V1 is the input voltage value input to the non-inverting input terminals of P1 and AP2, and V2 is the input voltage value input to the inverting input terminals.
out indicates an output voltage value. In this case, (V1-V2)
Is greater than the threshold voltage ΔH, the output Vout
Is inverted (inverted from low level to high level).

As described above, by making the voltage comparators AP1 and AP2 constituting the outlier detector XA have the above characteristics,
In particular, by setting the threshold voltage ΔH sufficiently large compared to the magnitude of the random noise component, the voltage comparator AP1
First output signal voltage VSS1 and second output signal voltage VS
When the difference from S2 is larger than the threshold voltage ΔH (VSS1-
VSS2> .DELTA.H), the output thereof becomes the power supply voltage level (high level).

Similarly, the voltage comparator AP2 determines that the difference between the second output signal voltage VSS2 and the first output signal voltage VSS1 is larger than the threshold voltage ΔH (VSS2−VSS1>
ΔH), the output becomes the power supply voltage level (high level). In other words, the magnitude of the difference between the first output signal VSS1 and the second output signal VSS2, that is, the absolute value | VSS
Only when 1−VSS2 | is greater than the threshold voltage ΔH,
Either the output of the voltage comparator AP1 or the output of the voltage comparator AP2 becomes the power supply voltage level (high level), and the abnormal value detection (moving object detection) can be performed without generating an erroneous signal due to a random noise component.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIG. In addition, this second
Corresponds to claims 1 to 3, claim 5 to claim 8, claim 10 to claim 13, and claim 15. As shown in FIG. 5, the solid-state imaging device 20 for motion detection according to the second embodiment is different from the above-described first embodiment only in the configuration of the pixels 21, 21, 21, 21 arranged in a matrix. I do. Accordingly, in the motion-detecting solid-state imaging device 20 of the second embodiment, the same components as those of the motion-detection solid-state imaging device 10 of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

In the solid-state imaging device 20 for motion detection, each pixel 21, 21, 21, 21 has a photodiode PD for generating and accumulating electric charges according to incident light, and electric charges supplied to a gate (control region). Transistor (n-channel type JFET) QA that outputs an electric signal corresponding to the above, and the charges generated and accumulated by the photodiode PD are selectively and directly transferred to the gate (control region) of the amplification transistor QA. Transfer MOS transistor (p-channel type) QT and drive pulse φPX1 from vertical scanning circuit 6
A capacitor CG for supplying (voltage signal) to the gate (control region) of the amplifying transistor QA by capacitive coupling, and a reset for selectively resetting the charge of the gate (control region) of the amplifying transistor QA. MOS transistor (p-channel type) QP.

In this case, each pixel 21, 21, 21, 21, 21
Then, even after the transfer of the charge, once the charge is accumulated in the gate (control region) by the source follower operation by the amplifying transistor QA, the charge is accumulated until the charge of the gate is reset. An electric signal corresponding to the electric charge is read. When the output (electric signal) of the amplifying transistor QA according to the temporarily stored charge has a value corresponding to the incident light with respect to the immediately preceding frame, this output is used as the first signal storage capacitor (first charge storage capacitor). The output is stored in a second signal storage capacitor (second charge storage means) CS when the value is stored according to the light incident on the current frame.

Further, also in the second embodiment, since the charge is directly transferred to the gate (control region) as described above, when the charge is transferred via another signal line or the like. In comparison, signal deterioration due to charge distribution during transfer is suppressed, and the S / N ratio of the motion detection solid-state imaging device 20 is improved. In the solid-state imaging device 20 for motion detection according to the second embodiment configured as described above, when the high-level drive pulse φPX1 or φPX2 appears on the clock line 5a or 5b connected to the vertical scanning circuit 6, The gate of the amplifying transistor QA (control region) is formed by capacitive coupling by the capacitors CG provided in the pixels 1, 1,...
Is controlled to turn on the amplifying transistor QA (selection).

As described above, by controlling the control region of the amplifying transistor QA (the gate of the JFET in this case) by applying a voltage to the gate using capacitive coupling,
The operation is performed as follows. That is, when the high-level drive pulse φPX1 or φPX2 appears on the clock line 5a or 5b while the gate (control region) of the amplification transistor QA is in a floating state, the gate of the gate capacitively coupled to the clock line 5a or 5b. The potential goes high. Then, the amplification transistor QA is turned on (selection) by the rise in the potential of the gate.

Conversely, when the drive pulse φPX1 or φPX2 of the clock line 5a or 5b goes low, the amplifying transistor QA is turned off (not selected). As described above, the capacitively coupled gate in FIG. 5 operates exactly the same as the pixel separating MOS transistor QX in FIG.
a and 2b). Therefore, the motion detecting solid-state imaging device 20 shown in FIG.
Can be operated according to the pulse timing chart of FIG. 2 in exactly the same manner as the motion detection solid-state imaging device 10 shown in FIG.

That is, the drive pulses φPX1, PX2 supplied to the gate of the pixel separating MOS transistor QX of the first embodiment are supplied to the corresponding capacitors CG, CG,... In the second embodiment. Good. In the above-described example, the control region capacitively coupled by the capacitor CG is used as the gate (control region) of the amplifying transistor QA, thereby easily forming the control region. In this case, since the pixel separating MOS transistor QX as shown in FIG. 1 is not required, the size of each pixel 21, 21, 21, 21 is reduced to improve the aperture ratio or the resolution. The effect of this is obtained.

(Third Embodiment) Next, a motion detection solid-state imaging device 30 according to a third embodiment of the present invention will be described with reference to FIG. It should be noted that the third embodiment corresponds to claims 1, 2, 5, 5 to 9, 11 to 13, and 15. In the solid-state imaging device 30 for motion detection according to the third embodiment, as shown in FIG. 6, the outlier detection circuits 7,... Capacitor CO1,
CO2) is connected to the horizontal readout line 12 only through the switching MOS transistors (n-channel type) QH11 and QH21 without using the switching MOS transistors (n-channel type) QH21. And different.

Therefore, in the motion-detecting solid-state imaging device 30, the same components as those of the motion-detecting solid-state imaging device 10 of the first embodiment are denoted by the same reference numerals, and description thereof is omitted. The solid-state imaging device 30 for motion detection has a configuration in which each outlier detection circuit 7 is connected to the horizontal read line 12 via horizontal read MOS transistors (n-channel type) QH11 and QH21 (switch means). Therefore, the horizontal read line 12 is provided with the reset switch MOS transistor QRSH as shown in the first embodiment (FIG. 1).
Becomes unnecessary.

Also in the third embodiment, each pixel 1, 1, 1,
In the devices 1 and 1, once charge is accumulated in the gate (control region) even after transfer of the charge by the source follower operation by the amplifying transistor QA, the charge is accumulated until the charge of the gate is reset. An electric signal corresponding to the stored electric charge is read. And
The amplifying transistor Q corresponding to the accumulated charge
When the output (electric signal) of A has a value corresponding to the incident light with respect to the immediately preceding frame, this output is stored in the first signal storage capacitor (first charge storage means) CR, and is converted into the incident light with respect to the current frame. This output is stored in the second signal storage capacitor (second charge storage means) CS when the value is in accordance with the value.

Next, the operation of the solid state imaging device 30 for motion detection according to the third embodiment will be described with reference to the pulse timing chart of FIG. FIG. 7 shows the operation of reading out two consecutive frames (the (N−1) th frame and the Nth frame) of the solid-state imaging device 30 for motion detection. In this case, the read operation in each frame (the (N-1) th frame and the Nth frame) is the same.

In the timing chart of FIG. 7, periods t10 to t15 show the readout operation of the pixels 21 in the first row, and periods t20 to t25 show the readout operation of the pixels 21 in the second row. I have. Incidentally, in the timing chart, periods t10 to t14 (and period t20)
Operations 24 to 24) are performed during the period t10 of the timing chart (FIG. 2) of the solid-state imaging device 10 for motion detection according to the first embodiment.
The operation is the same as that in the period t15 (and the periods t20 to t24), and a detailed description thereof will be omitted. Here, the operation in the period t15 in the Nth frame will be described.

By the end of the period t14 of the N-th frame, that is, by the start of the period t15, the first output signal VSS1 is supplied to the first signal storage capacitor CR and the second signal storage capacitor CS. The second output signal VSS2 is stored and held, and the first output signal V
SS1 and the second output signal VSS2 are compared with each other by the different value detection circuit 7, and the different value detection circuit 7 outputs a different value signal.

Then, when the period t15 is reached, first, the driving pulse φH1 from the horizontal scanning circuit 13 rises to a high level for a certain period, and is thereafter kept at a low level. Next, after the drive pulse φH1 is held at a low level, the drive pulse φH2 is raised to a high level for a certain period of time, and then held at a low level. At this time, the different value signal from the different value detection circuit 7 is applied to the drive pulses φH1, φH
At the timing of the rising edge of 2, the data is sequentially read out to the horizontal read line 12 for each column, and then output to the output terminal VO via the output buffer amplifier 15 sequentially.

At this time, the voltage signal read out to the horizontal read line 12 takes a long time until it reaches a steady state because its waveform is distorted due to the influence of the parasitic capacitance of the horizontal read line 12. Since the voltage signal appearing at 12, ie, the different value signal has already been binarized (high-level or low-level digital signal),
Even if it does not reach the steady state, if it reaches a certain level (threshold level of the logic circuit), it becomes possible to determine the high level / low level, and the reading operation can be speeded up.

The OR operator OR operates the parasitic capacitance C of the horizontal read line 12 so that the horizontal read line 12 is at a predetermined level (high level or low level).
Since H is charged or discharged, the operation of resetting (initializing) the horizontal read line 12 becomes unnecessary, and reading can be performed at higher speed. (Fourth Embodiment) Next, a motion detection solid-state imaging device 40 according to a fourth embodiment of the present invention will be described with reference to FIG. It should be noted that the fourth embodiment is described in claims 1, 2,
Claims 5 to 8 correspond to claims 10 to 13, and claim 15.

The motion detection solid-state imaging device 40 according to the fourth embodiment comprises, as shown in FIG.
Switching MOS transistors (n-channel type) QH11, QH without means for accumulating the different value signals (the different value signal storage capacitors CO1, CO2 of the second embodiment).
The difference from the solid-state imaging device 20 for motion detection according to the above-described second embodiment is that it is connected to the horizontal readout line 12 only via 21.

Therefore, in the motion detection solid-state imaging device 40, the same portions as those of the motion detection solid-state imaging device 20 of the second embodiment are denoted by the same reference numerals, and description thereof will be omitted. Further, when the solid-state imaging device 40 for motion detection according to the fourth embodiment is compared with the solid-state imaging device 30 for motion detection according to the third embodiment, the pixels 21 21 21 21
1 and the method of selecting / non-selecting the amplification transistor QA of the pixels 21, 21, 21, 21 are different from the pixels 1, 1, 1, 1 of the third embodiment.

Therefore, the operation of the solid-state imaging device for motion detection 40 of the fourth embodiment is different from the operation of the solid-state imaging device for motion detection 30 of the third embodiment (operation according to the timing chart of FIG. 7). Is the same. That is, the drive pulses φPX1 and PX2 supplied to the gates of the pixel separating MOS transistors QX of the third embodiment are changed to the corresponding capacitors C21 and C2 in the fourth embodiment.
1 may be supplied.

As described above, in the fourth embodiment, the gate (control region) of the amplifying transistor QA is capacitively coupled by the capacitor C21.
Since the transistor (for example, the transistor QX in FIG. 6) is not required, the size of each of the pixels 41, 41, 41, 41 can be reduced.
Also in the fourth embodiment, each pixel 21, 21, 21, 22,
In No. 1, once charge is accumulated in the gate (control region) even after transfer of charge by the source follower operation by the amplifying transistor QA, the charge is accumulated until the charge of the gate is reset. An electric signal corresponding to the electric charge is read out. Then, the amplifying transistor QA corresponding to the accumulated charge
When the output (electric signal) is a value corresponding to the incident light with respect to the immediately preceding frame, this output is stored in the first signal storage capacitor (first charge storage means) CR, and according to the incident light with respect to the current frame. When this value is obtained, this output is stored in the second signal storage capacitor (second charge storage means) CS.

(Fifth Embodiment) Next, a fifth embodiment of the present invention will be described with reference to FIGS.
It should be noted that the fifth embodiment is described in claim 1, claim 2, claim 5 to claim 8, claim 10, claim 11, and claim 1.
4 and Claim 15. The motion detection solid-state imaging device 50 according to the fifth embodiment includes a configuration of each pixel 51, 51,.
The configuration of the different value detection circuit 60 that compares the electric signals between two consecutive frames (1, 1st frame, Nth frame) and outputs a different value signal is the same as that of the first to fifth frames described above. This is different from the solid-state imaging device for motion detection according to the fourth embodiment.

FIG. 9 shows only one pixel 51 among a plurality of pixels 51 arranged in a matrix for the sake of simplicity. As illustrated in FIG. 9, the pixel 51 of the motion detection solid-state imaging device 50 includes a photodiode PD that generates and accumulates a charge corresponding to incident light,
Amplifying transistor (n-channel type JFE) that outputs an electric signal corresponding to the electric charge supplied to the gate (control region)
T) QA, a transfer MOS transistor (p-channel type) QT for selectively and directly transferring the charge generated and accumulated by the photodiode PD to the gate (control region) of the amplification transistor QA, and not shown. A capacitor C51 for supplying a drive pulse φP from the vertical scanning circuit to the gate (control region) of the amplifying transistor QA by capacitive coupling, and selectively resetting the charge of the gate (control region) of the amplifying transistor QA. And a reset MOS transistor (p-channel type) QP.

Specifically, the anode side of the photodiode PD in the pixel 51 and the gate (control region) of the amplifying transistor QA are connected to the transfer MOS transistor QA, respectively.
It is connected to the source and drain of T. The transfer gate of the transfer MOS transistor QT is commonly connected to the clock line 53 together with the transfer gates of the other pixels 51 (not shown) in the same row, and the vertical scanning circuit ( (Not shown), the driving pulse φTG
The transfer MOS transistor QT operates according to the level of the transfer MOS transistor QT.

The reset MOS transistor QP
A constant voltage power supply (not shown) is connected to the drain of
A predetermined voltage VG is selectively applied to the gate (control region) of the amplification transistor QA of each pixel 51 from the constant voltage power supply. The gate of the reset MOS transistor QP is connected to a vertical scanning circuit (not shown).
The source is connected to the drain of the transfer MOS transistor QT.

When a drive pulse φRSG is applied to the gate of the reset MOS transistor QP from a vertical scanning circuit (not shown), the reset MOS transistor QP operates according to the level of the drive pulse φRSG. It has become. A capacitor C51 used for connection / separation between the pixel 51 and the vertical readout line 52 is commonly connected to a clock line 55 for each row of the pixel 51, and a level of a driving pulse φP from a vertical scanning circuit (not shown). In response, the amplifying transistor QA of the pixel 51 is turned on / off (selection / non-selection), and the electric charge corresponding to the incident light, that is, the electric signal corresponding to the incident light is supplied to the gate (control region). , And are selectively transferred.

In the pixel 51 configured as described above, once the charge is accumulated in the gate (control region) of the amplifying transistor QA, the source follower operation is performed after the transfer of the charge until the charge is reset. As a result, an electric signal corresponding to the charge is output from the amplifying transistor QA.

In the solid-state imaging device 50 for motion detection, the charges are directly transferred to the gate (control region) as described above. Signal degradation due to the charge distribution of
The image S / N ratio of the motion detection solid-state imaging device 50 is improved. Further, an outlier detection circuit (signal comparing means) 60 is connected to the vertical read line 52.

This outlier detection circuit 60 is not shown in the drawing, but, as in the first embodiment, its output side is provided with an outlier signal storage capacitor via a switching MOS transistor, A readout line is connected, and an electric signal (a different value signal representing a difference between an electric signal of a previous frame and an electric signal of a current frame) stored in a capacitor for storing a different value signal is changed according to a drive pulse supplied from a horizontal scanning circuit. The data is sequentially output from an output terminal via an output buffer amplifier.

Next, the configuration of the outlier detection circuit 60 arranged on the vertical read line 52 will be described in detail. As shown in the figure, the different value detection circuit 60 includes two capacitors CCA and CCB and five inverters INB1 to INB.
5 and 4 switching MOS transistors QB1 to QB
B4 and an OR circuit OR.

The first sample and hold circuit 60A is constituted by the capacitor CCA and the switching MOS transistor QB1, and the second sample and hold circuit 60B is constituted by the capacitor CCB and the switching MOS transistor QB2. in this case,
One electrode of each of the capacitors CCA and CCB is connected to the vertical read line 52.

The other electrodes of the capacitors CCA and CCB are connected to the input terminals of the inverters INB1 and INB2 (binarizing means), respectively, and the switch MO
They are connected to the drains of S transistors QB1 and QB2, respectively. Also, the switching MOS transistor QB
1 and QB2 are connected to a constant voltage power supply VR (not shown).
1 and VR2 are connected to each other.

In this case, a clock line 56 is commonly connected to the gates of the switching MOS transistors QB1 and QB2, and a drive pulse φSA is supplied to each gate via the clock line 56. . The output terminal of the inverter INB1 is connected to the OR circuit OR via inverters INB3 and INB5.
Is connected to one of the input terminals.

On the other hand, the other input terminal of the OR circuit OR is connected to the output terminal of the inverter INB2 via the inverter INB4. The output terminal of the inverter INB3 is connected to the input terminal of the inverter INB1 to form a closed loop, and the output terminal of the inverter INB4 is connected to the input terminal of the inverter INB2 to form a closed loop.

A switching MOS transistor QB3 is provided on a signal line extending from the output terminal of the inverter INB3 to the input terminal of the inverter INB1.
A switching MOS transistor QB4 is provided on a signal line from the output terminal of the inverter 4 to the input terminal of the inverter INB2. In this case, the driving pulse φ is connected to the gates of the switching MOS transistor QB3 and the switching MOS transistor QB4 via the clock line 57.
SB is supplied.

Next, the operation of the solid-state imaging device for motion detection 50 having the above configuration will be described with reference to a timing chart shown in FIG. FIG. 10 shows that, as in FIG. 2, one pixel 51 that detects incident light at regular intervals detects incident light in two consecutive frames (the (N−1) th frame and the Nth frame). The case where a read operation is performed is shown. Note that this timing chart is for describing the operation of the outlier detection circuit 60, and the description of the operation related to the final output of the motion detection solid-state imaging device 50 will be omitted.

Hereinafter, the operation immediately before the period t20 of the Nth frame in the timing chart of FIG. 10 will be described focusing on the readout operation of the pixels 1 in the first row in the Nth frame. Before reaching the period t20 of the N-th frame (N-th frame)
During one frame period t14), the driving pulse φTG and the driving pulse φRSG are held at a high level, and the driving pulse φ
P, the drive pulse φSA is held at a low level, and the drive pulse φSB is held at a high level.

Therefore, before the period t20, the transfer MOS transistor QT is off because the drive pulse φTG is at a high level, and the reset MOS transistor QP is also off because the drive pulse φRSG is at a high level.
At this time, the gate (control region) of the amplification transistor QA
Is in a floating state, but the signal charge already transferred to the gate (control region) at this time due to the effect of the parasitic capacitance, that is, the charge (first signal charge) corresponding to the incident light in the immediately preceding frame. Is maintained in a biased state.

On the other hand, on the photodiode PD side, charges (second signal charges) corresponding to the incident light in the current frame.
Are generated and accumulated. Then, in the period t20, the drive pulse φP and the drive pulse φSA are inverted from the low level to the high level, and the drive pulse SB is inverted from the high level to the low level.

When the drive pulse φP goes high, the charge (first signal charge) that has already been transferred to the gate (control region) of the amplifying transistor QA in the (N-1) th frame and is held at the gate as it is. ) Is generated by the source-follower operation of one electrode CC of the two capacitors CCA and CCB.
A1 and CCB1.

When drive pulse φSA attains a high level, switching MOS transistor QB
1, QB2 is turned on and two capacitors CCA,
A constant voltage V is applied to the other electrodes CCA2 and CCB2 of the CCB.
R1 (= VT−Vth) and VR2 (= VT + Vth) are supplied. Further, since the drive pulse φSB becomes low level, the path from the output terminal of the inverter INB3 to the input terminal of the inverter INB1 and the inverter IB3
The path from the output terminal of NB4 to the input terminal of inverter INB2 is cut off.

By these operations, capacitor CCA
Is equal to an electric signal (denoted as VA) according to the incident light in the (N-1) th frame and a constant voltage VR1 (=
VT−Vth; where Vth is a difference from the first predetermined value). On the other hand, in the capacitor CCB, the potential difference between both ends is the difference between the electric signal VA in the (N-1) th frame and the constant voltage VR2 (= VT + Vth; here, Vth is a second predetermined value).

At the end of the period t20, that is, at the start of the period t21, the driving pulse φSA and the driving pulse φ
RSG is both inverted to low level. Drive pulse φS
When A is inverted to a low level, the difference between the electric signal VA in the (N-1) th frame and the constant voltage VR1 (= VT-Vth) is stored directly at both ends of the capacitor CCA, and the Nth frame is directly stored at both ends of the capacitor CCB. -1 frame, the electric signal VA and the constant voltage VR2 (= VT + V
th) is stored as it is.

When the drive pulse φRSG goes low, the reset MOS transistor (p-channel type) QP turns on, and the amplifying transistor QA
The charge stored in the gate (control region) is discharged (reset). Then, at the end of the period t21, that is,
In the period t22, the driving pulse φTG is inverted to a low level, and the driving pulse φRSG is inverted to a high level again.

When the drive pulse φRSG goes high, the reset is released. When the drive pulse φTG goes low, the transfer MOS
The transistor QT is turned on, and a charge (second signal charge) corresponding to the incident light generated and accumulated in the photodiode PD up to this point is newly transferred to the gate (control region) of the amplification transistor QA. The data is directly transferred via the transistor QT.

In this case, the amplifying transistor QA performs a source follower operation, and a second output signal (second electric signal) corresponding to the second signal charge is transferred to the vertical readout line 52 (at this time, the drive is performed). The pulse φP is at a high level, and the amplifying transistor QA is on). Then, at the end of the period t22, that is, at the start of the period t23, the drive pulse φTG is inverted to the high level, the transfer MOS transistor QT is turned off, and the drive pulse φTG is turned off according to the incident light generated and accumulated in the photodiode PD. The transfer of the charge (second signal charge) to the gate (control region) of the amplification transistor QA ends.

At this time, the gate (control region) of the amplifying transistor QA is again in a floating state, but due to the effect of the parasitic capacitance, the voltage of the gate is increased by the transferred charge (second signal charge). That state is maintained while being raised. In this case, an electric signal (denoted as VB) corresponding to the electric charge (second signal electric charge) remaining in the gate after the electric charge is transferred from the amplifying transistor QA by the source follower operation to the two capacitors CC.
A and CCB are output to one electrode CCA1 and CCB1.

By the way, an electric signal VB corresponding to the electric charge (second signal electric charge) obtained in the N-th frame (current frame) is applied to one electrode C of the capacitors CCA and CCB.
At the time of output to CA1 and CCB1, both ends of these two capacitors CCA and CCB are connected to the electric signal VA and the constant voltage VR in the (N-1) th frame as described above.
1 (= VT−Vth), and similarly, the difference between the electric signal VA and the constant voltage VR2 (= VT + Vth) is stored.

When the electric signal VB newly obtained in the Nth frame is supplied to one electrode CCA1 of the capacitor CCA, the potential of the other electrode CCA2 of the capacitor CCA becomes (VB + VR1-VA). Become. On the other hand, as for the capacitor CCB, when the electric signal VB is supplied to one electrode CCB1, the potential of the other electrode CCB2 becomes (VB + VR2-VA).

Here, VR1 (= VT−Vth), VR
Consider a case where VT among the values that determine 2 (= VT + Vth) is the threshold voltage of the inverter INB1 and the inverter INB2. At this time, the potential of the input side (in this case, VB + VR1-VA) of the inverter INB1 is VT
When it becomes larger (VB + VR1-VA> VT),
Since a low-level signal is output, a low-level signal is output when the electric signal VB obtained in the current frame becomes larger than VT + VA-VR1.

Here, since VR1 is (VT-Vth), as a result, the inverter INB1 sets VB to (V
A low-level signal is output when VB becomes larger than (A + Vth), and a high-level signal is output when VB becomes smaller than (VA + Vth). Further, regarding the inverter INB2, the potential on the input side (in this case, VB + VR2
-VA) becomes larger than VT (VB + VR2-
VA> VT), and outputs a low-level signal, so that the electric signal VB obtained in the current frame is VT +
When it becomes larger than VA-VR2, a low-level signal is output.

Here, since VR2 is (VT + Vth), as a result, the inverter INB2 sets VB to (V
A low-level signal is output when VB is larger than (A-Vth), and a high-level signal is output when VB is smaller than (VA-Vth).

The output signal of the inverter INB1 is inverted by the inverter INB3 and the inverter INB5, and then transferred to one input terminal of the OR circuit OR. The output signal of the inverter INB2 is
After being inverted by NB4, it is transferred to the other input terminal of the OR circuit OR. In the next period t24, the driving pulse φP is inverted to a low level, and the driving pulse φSB is inverted to a high level.

When the drive pulse φP goes low, the amplifying transistor QA is turned off (non-selected) again. On the other hand, when the drive signal φSB goes high, the output terminal of the inverter INB3 and the inverter INB3
1 are connected to each other to form a closed loop, while the output terminal of the inverter INB4 is connected to the inverter INB4.
The two input terminals are connected to form a closed loop.

By forming a closed loop between the inverter INB3 and the inverter INB1, the output of the inverter INB1 is fixed.
By forming a closed loop between the inverter INB4 and the inverter INB2, the output of the inverter INB3 is fixed. As described above, the outlier detection circuit 60
(The output of the OR circuit OR) is (1) VB is (V
A + Vth), that is, (VB−V
(A) becomes larger than Vth, (2) when VB becomes smaller than (VA-Vth), that is, (VA)
-VB) outputs a signal of a logic high level when any of the conditions when VB becomes larger than Vth is satisfied.

Note that also in the fifth embodiment, the voltage signal (different value signal) supplied to the read line (not shown) is already binarized (digitized) by the different value detection circuit 60. Therefore, if a certain level (threshold level of the logic circuit) is reached even if the steady state is not reached due to the parasitic capacitance of the read line, it is determined whether the level is a logic high level / low level. This makes it possible to speed up the reading operation.

The charge transferred to the gate of the amplifying transistor QA in the Nth frame is treated as a second signal charge in the Nth frame. However, in the next (N + 1) th frame (not shown), the first signal is transferred. Will be treated as signal charges. (Sixth Embodiment) Next, FIG.
This will be described with reference to FIG. The sixth embodiment corresponds to claims 1, 4 to 9, 11 to 13, and 15.

The sixth embodiment is different from the first embodiment in that the shift register 113 is used as the signal transfer means.
Different from the fifth embodiment. First, the outline of the motion detection solid-state imaging device 110 will be described. In the solid-state imaging device 110 for motion detection, as in the first to fifth embodiments, the pixels 101, 101, 101, 101 are arranged in a matrix, and the pixels 101, 101,. It is connected to the read lines 102a and 102b.

The pixels 101 are composed of a photodiode PD, an amplifying transistor QA, a transfer MOS transistor QT, a reset MOS transistor QP,
The specific configuration and the connection relationship are the same as those of the pixels 1, 1... Of the above-described first and third embodiments, and the detailed description thereof is omitted. I do.

In this embodiment, the charge from the photodiode PD is directly transferred to the gate (control region) of the amplification transistor QA by the transfer MOS transistor QT. With such a configuration, signal deterioration due to charge distribution at the time of transfer is suppressed as compared with the case where charges are transferred to the charge accumulation region via another signal line, and the image of the motion detection solid-state imaging device 110 is reduced. The S / N ratio is improved.

The pixels 101, 101,... Select a specific row, and transfer the electric signal corresponding to the incident light to the corresponding vertical readout lines 102a, 102b at a constant timing. Is connected. The vertical scanning circuit 106 and the clock lines 103a, 103b, 104a, 104b, 10
Vertical scanning means is constituted by 5a, 105b and the like.

An outlier detection circuit (signal comparing means) 107 is arranged on the vertical read lines 102a and 102b provided for each column, and an output of the outlier detection circuit 107 is connected to a shift register (signal transfer). Means) 113 are connected. The different value detection circuits 107 arranged on the vertical read lines 102a and 102b respectively output the corresponding vertical read lines 102 from the pixels 101, 101,.
When an electric signal corresponding to the incident light is output to a and 102b, the electric signal is stored as an electric signal for the immediately preceding frame, and the same pixels 101 and 101 as the stored electric signal at the next fixed timing. ., And outputs a different value signal indicating the result of the comparison.

The specific configuration of the outlier detection circuit 107 is the same as that of the outlier detection circuit 7 of the first to fourth embodiments.
This is the same as (FIG. 3), and a detailed description thereof will be omitted. The different value detection circuit 107 arranged for each column outputs
Each column is connected to a corresponding bit register of the shift register 113. This outlier detection circuit 10
The different value signal from 7 is supplied to a shift register (signal transfer means).
The data is stored in the corresponding register of the shift register 113, and thereafter, sequentially transferred to the horizontal read line 112 by the operation of the shift register 113, and then output from the output terminal VO.

That is, the first column (the vertical read line 10
2a), the output of the different value detection circuit 107 is the data input terminal Q of the first bit register of the shift register 113.
1 and the second column (on the vertical read line 102b)
Is output from the shift register 113.
Of the second bit register is connected to the data input terminal Q2.

A load signal input terminal LD of the shift register 113 is connected to a node 111 on a drive pulse generating circuit (not shown) side via a clock line 111a. In accordance with the level of the drive pulse φLD input to the load signal input terminal LD, the shift register 113 responds to the electric signals from the different value detection circuit 107 input to the data input terminals Q1 and Q2, respectively. In a register (not shown).

The output terminal of this shift register 113 is
It is connected to the output terminal VO via the horizontal read line 112. In this case, what is read out to the horizontal read line 112 is an electric signal (a different value signal) output from the different value detection circuit 107, and a clock pulse applied to a clock terminal (not shown) of the shift register 113 rises. At the timing, the different value signals stored in each register are sequentially output from the output terminal VO.

The vertical read lines 102a, 102
2b, the reset switch MOS transistors QRSV1 and QRSV2, and the constant current sources 117a and 117
The operation and the like of 7b are the same as those of the reset switch MOS transistors QRSV1 and QRSV2 of the first embodiment, and a detailed description thereof will be omitted. Next, the operation of the motion detection solid-state imaging device 110 having the above configuration will be described with reference to a timing chart shown in FIG.

FIG. 12 is a timing chart similar to that in the case of the solid-state imaging device 10 for motion detection according to the first embodiment, in which one pixel 101 for detecting the incident light at a fixed timing includes two continuous frames. That is, the (N-1) th frame (the immediately preceding frame), the Nth frame (the current frame)
2 shows a case where the incident light is detected and the reading operation is performed. Here, the period t10 to t15 corresponds to the reading operation of the pixel 1 in the first row, and the period t20 to t25 corresponds to the second operation.
The read operation of the pixel 1 in the row is shown.

In the following description, shift register 1
13 will be mainly described. Before the period t10 of the N-th frame shown in FIG. 12 (the period t2 of the (N-1) th frame)
5), the drive pulses φTG1, TG2 are both held at a high level, the drive pulses φPX1, φPX2 are both held at a low level, and the drive pulses φRG1, φRG
2 are both held at a high level. The drive pulses φRSV, φTR, and φTS are held at a low level,
Further, the drive pulse φLD is also held at a low level.

Therefore, before the period t10, the transfer M
The OS transistor QT is off, the reset MOS transistor QP is off, and the gate (control region) of the amplifying transistor QA is in a floating state.
Due to the effect of the parasitic capacitance, each amplifying transistor Q
The charge (first signal charge) corresponding to the incident light transferred to the gate (control region) of A is held in the gate as it is. Therefore, the amplifying transistor Q
A outputs an electric signal corresponding to the gate voltage by a source follower operation until the electric charge accumulated in the gate (control region) is reset.

After the transfer MOS transistor QT is turned off, a charge (second signal charge) is newly generated and stored in each photodiode PD according to the incident light. Before the period t10, the pixel separating MOS transistor QX is off, and each pixel 101 is in a state of being separated from the vertical readout lines 102a and 102b. At this time, the reset switch MOS transistors QRSV1 and QRSV2, the switch MOS
The transistors QR and QS are all turned off so that electric signals on the vertical read lines 102a and 102b are not supplied to any of the first and second signal storage capacitors CR and CS.

Since the drive pulse φLD is at a low level, signals from the vertical read lines 102a and 102b are not inputted to the register of the shift register 113 corresponding to each bit. Next, when the period t10 is reached, the driving pulse φRSV, the driving pulse φTR, and the driving pulse φTS are inverted from a low level to a high level.

At this time, the reset switch MOS transistors QRSV1 and QRSV2 are turned on, and the switch M
When the OS transistors QR and QS are turned on, the first signal storage capacitor CR and the second signal storage capacitor C
The electric charges remaining in S are discharged. Then, when the period t11 is reached, the driving pulse φRSV is inverted to a low level, and the driving pulse φTS is also inverted to a low level.
As a result, the reset switch MOS transistors QRSV1 and QRSV2 and the switch MOS transistor QS are turned off. Note that the switching MOS transistor QR remains on.

In the period t11, the driving pulse φ
PX1 is inverted to a high level, and each pixel 1 in the first row is inverted.
Is turned on, and the source of the amplifying transistor QA is connected to the vertical readout lines 102a and 102b (selection). At this time, the first signal charge corresponding to the incident light in the immediately preceding frame (the (N-1) th frame) is transferred to the gate (control region) of the amplification transistor QA of each pixel 1 in the first row. Since the signal is held, an electric signal corresponding to the first signal charge is output to the vertical read lines 102a and 102b.

In this period t11, the first output signal (first electric signal) from each of the amplifying transistors QA in the selected first row is charged in the first signal storage capacitor CR. You. At this time, with respect to each amplifying transistor QA in the second row, each pixel separating MOS transistor QX in the second row is turned off and is not connected to the vertical readout lines 102a and 102b (non-connected state). Choice).

At time t12, drive pulse φTR is inverted to low level, and drive pulse φRG1 is inverted to low level. At this time, the switching MOS transistor QR is turned off, and the first signal storage capacitor CR
Are in a floating state and hold the first output signal as it is. At this time, the first signal storage capacitor C
The first output signal held in R is the output of the amplifying transistor QA that has been holding the first signal charge since the immediately preceding frame (period t13 of the (N-1) th frame).

In this case, VSS indicating the first output signal
The value of 1 is represented by the equation (1) in the first embodiment described above. Further, in the period t12, the drive pulse φRG1 is at a low level, the reset MOS transistors QP in the first row are turned on, and the power supply voltage VRD (read level) is equal to the gate of each of the amplifying transistors QA in the first row. (Control region), the gate is reset.

That is, at this time, the amplifying transistor Q
The first signal charge is discharged from the gate (control region) of A, and the gate (control region) is connected to the power supply voltage VR.
D biased. In the period t13, the driving pulse φRG1 is inverted to a high level, and the driving pulse φTG1
Is inverted to a low level. As a result, each reset MOS transistor QP in the first row is turned off again, and the gate (control region) of the amplifying transistor QA in the first row is set in a floating state. The gate is connected to the power supply voltage VRD.
(Read level) is maintained.

At this time, the transfer MOS transistor QT of each pixel 1 in the first row is turned on, and the charge corresponding to the incident light generated and accumulated in the photodiode of each pixel 1 in the first row. When the (second signal charge) is transferred to the gate (control region) of the amplification transistor QA of each pixel 1 in the first row, the gate potential of each amplification transistor QA is equal to the transferred charge. The potential of the source rises by the rise of the gate potential. At this time, a second output signal (second electric signal) corresponding to the second signal charge is output from each amplification transistor QA in the first row.
Is output to the vertical readout lines 102a and 102b via the pixel separating MOS transistor QX.

In the period t14, the drive pulse φTG1
Is inverted to a high level, and the drive pulse φTS,
The drive pulse φLD is inverted to a high level. At this time, each transfer MOS transistor QT in the first row is turned off, and the charge (second signal charge) according to the incident light generated and accumulated in the photodiode PD of the pixel 1 in the first row is amplified. (Control area) of transistor QA
When the transfer to the amplifier transistor QA is completed, the gate (control region) of the amplifying transistor QA is again brought into a floating state. The state is maintained while the potential of the signal rises.

This state is continued until the gate is reset thereafter, and a signal (voltage signal) corresponding to the second signal charge is output by the source follower operation of the amplifying transistor QA (after the period t14). Will be. At this time, since the switching MOS transistor QS is on (the drive pulse φTS is at a high level), the output voltage signal is charged in the second signal storage capacitor CS.

In this period t14, when the current flowing between the source and the drain becomes IB due to the source follower operation of the amplifying transistor QA, the source potential VS
The value of S2 is the value shown in equation (2) of the first embodiment described above.

In this period t14, the switching MOS transistor QS is turned on, so that the voltage across the second signal storage capacitor CS becomes VSS2. As described above, the second output signal (voltage signal) represented by Expression (2) is supplied to the second signal storage capacitor CS in the same manner as in the first embodiment. , The first output signal (voltage signal) represented by Expression (1) is also stored and held, similarly to the first embodiment.

Then, the first output signal VSS1 (analog signal) and the second output signal are output by the different value detector XA of the different value detection circuit 107 as expressed by the equation (3) in the first embodiment. Only when the magnitude of the difference from the signal VSS2 (analog signal) is equal to or greater than a predetermined value, a different value signal (digital signal) whose output is high level (logic level high level) or low level (logic level low level) is output. Will be output.

In the period t14, the driving pulse φ
When LD goes high, shift register 1
The register corresponding to each of the 13 bits stores a different value signal (digital signal) from the different value detector XA. In the period t15, the driving pulse φPX1, the driving pulse φTS, and the driving pulse φTO are inverted to a low level. At this time, the pixel separating MOS transistor QX is turned off, and the pixels 101, 101 in the first row are separated from the vertical readout lines 102a, 102b. Also, the switching MOS transistor QS is turned off.

The register corresponding to each bit of the shift register 113 holds the different value signal (digital signal) stored in the period t14. This period t
In 15, a clock pulse (not shown) is further input to the shift register 113, and the different value signal (digital signal) held in the register corresponding to each bit is changed according to the timing at which the clock pulse is generated. , Are sequentially read out to the horizontal readout line 112 and output to the output terminal VO.

In the present embodiment, the horizontal read line 11
The electric signal (hetero signal) appearing in 2 is completely binarized (digitized). As is generally well known, a digital signal can be read at a higher speed than an analog signal, and therefore, the reading operation can be further speeded up. Further, since the signal read to the horizontal read line 112 is a digital signal, the signal can be output without being affected by noise.

In the subsequent period t20-t25, the second
The above-described period t1 is applied to the pixels 101 in the row.
The same operation as the readout operation of the pixels 101, 101 in the first row at 0 to t15 is repeatedly performed.
Different value signals (digital signals) in the Nth frame are sequentially output from the output terminal VO from the pixels 101 in the row.

As described above, each of the pixels 101 and 10 output in response to the incident light, obtained between two consecutive frames (the (N-1) th frame and the Nth frame), respectively.
Analog signals (electric signals representing luminance) from the pixels 101, 101, and 101 are compared with each other.
A signal (different value signal) is output from 1,101.

As described above, two consecutive frames (N-th frame)
Moving object detection can be performed by detecting pixels in which the difference between the electric signals (luminance signals) obtained between the 1st frame and the Nth frame is different. Then, by repeatedly performing the above operation, the moving object can be detected between two or more consecutive frames.

(Seventh Embodiment) Next, a seventh embodiment of the present invention will be described with reference to FIG. This seventh embodiment corresponds to claims 1, 4 to 8, 10 to 13, and 15.

As shown in FIG. 13, in the solid-state imaging device 120 for motion detection according to the seventh embodiment, only the configuration of the pixels 131, 131, 131, 131 arranged in a matrix is the same as in the sixth embodiment. It is different from the form. Accordingly, in the motion detecting solid-state imaging device 120 of the seventh embodiment, the same portions as those of the motion detecting solid-state imaging device 110 of the sixth embodiment are denoted by the same reference numerals, and description thereof is omitted.

The motion detecting solid-state imaging device 120
Have the same configuration as the pixels 21, 21,... Of the solid-state imaging device 20 for motion detection according to the second embodiment. That is, each of the pixels 131, 131... Includes a photodiode PD, an amplifying transistor (n-channel JFET) QA, and a transfer MOS transistor QT.
, A capacitor CG, and a reset MOS transistor QP.

Also in the seventh embodiment, since charges are directly transferred to the gate (control region) as described above, compared with the case where charges are transferred via another signal line or the like. In addition, signal deterioration due to charge distribution during transfer is suppressed, and the S / N ratio of the motion detection solid-state imaging device 120 is improved. In each of the pixels 131, 131,..., The source follower operation by the amplifying transistor QA
Once the charge is accumulated in the gate (control region) even after the transfer of the charge, an electric signal corresponding to the accumulated charge is read out until the charge of the gate is reset. ing. Then, the output of the amplifying transistor QA according to the previously stored charge is stored in the first signal storage capacitor (first charge storage means) CR,
Next, an output corresponding to the stored charge is stored in a second signal storage capacitor (second charge storage means) CS.
The outputs thus stored are compared by an outlier detector XA to obtain an outlier signal.

In the solid-state imaging device 120 for motion detection according to the seventh embodiment, the vertical scanning circuit 106
When a high-level drive pulse φPX1 or φPX2 appears on the clock line 105a or 105b connected to the pixel 101, the gate of the amplifying transistor QA (control region) ) Is controlled to turn on the amplification transistor QA (selection).

As described above, by controlling the control region of the amplifying transistor QA (the gate of the JFET in this case) by applying a voltage to the gate using capacitive coupling,
The operation is performed as follows. That is, when the high-level drive pulse φPX1 or φPX2 appears on the clock line 105a or 105b while the gate (control region) of the amplifying transistor QA is in a floating state, the gate of the gate capacitively coupled to the clock line 105a or 105b. The potential goes high. The rise of the potential of the gate causes the amplification transistor Q
A turns on (selection).

On the contrary, the clock line 105a or 1
When the drive pulse φPX1 or φPX2 of 05b goes low, the amplifying transistor QA is turned off (not selected). Thus, the capacitively coupled gates have the same function as the pixel separating MOS transistor QX in FIG. 11 of the sixth embodiment (the pixels 101, 101... Are separated or connected to the vertical readout lines 102a, 102b). 13), the solid-state imaging device 120 for motion detection shown in FIG. 13 can be operated according to the timing chart of FIG.

The control region capacitively coupled by the capacitor CG is used as the gate (control region) of the amplifying transistor QA, thereby easily forming the control region. In this case, since the pixel separating MOS transistor QX as shown in FIG. 11 is not required, the size of each of the pixels 131, 131, 131, 131 is reduced to improve the aperture ratio or the resolution. The effect of this is obtained.

(Eighth Embodiment) Next, an eighth embodiment of the present invention will be described with reference to FIGS. It is to be noted that the eighth embodiment corresponds to claims 1, 4 to 9, 11, 11, 14 and 15.
Corresponding to The solid-state imaging device 140 for motion detection according to the eighth embodiment includes a plurality of pixels 14 arranged in a matrix.
, And each pixel 141, 141,.
Only the configuration of the different value detection circuit 150 that compares the electric signals between two consecutive frames (the (N-1) th frame and the Nth frame) and outputs a different value signal is the same as that of the sixth and seventh embodiments described above. It is different from the motion detecting solid-state imaging devices 110 and 120 of the embodiment.

In FIG. 14, a plurality of pixels 141 and 141 arranged in a matrix are shown for the sake of simplicity.
, Only one pixel 141 is shown. This pixel 141 has an amplifying transistor Q as shown in FIG.
The difference from the pixel 101 of the sixth embodiment is that a p-channel type pixel separating MOS transistor QX is used as a connection separating means for separating / connecting the source of A and the vertical read line 142. Therefore, other specific configurations and connection relationships of the pixel 141 are the same as those of the first and third pixels.
Are the same as the pixels 1, 1... Of the embodiments described above, and a detailed description thereof will be omitted.

Note that the pixel 141 has a pixel separating MOS.
The gate of the transistor QX is connected to a clock line 145 connected to a vertical scanning circuit (not shown), and the pixel separating MOS transistor QX receives a driving pulse φP from the vertical scanning circuit (not shown).
It is designed to work according to the level. In the pixel 141 thus configured, the amplifying transistor QA
Once the electric charge is accumulated in the gate (control region), the source follower operation outputs an electric signal corresponding to the electric charge from the amplifying transistor QA until the control region is reset after the electric charge is transferred. You.

The motion detecting solid-state imaging device 140
However, since the charge is directly transferred to the gate (control region) as described above, signal deterioration due to charge distribution at the time of transfer is suppressed as compared with the case where the charge is transferred via a signal line or the like, and the movement is not affected. The image S / N ratio of the detection solid-state imaging device 140 is improved. Although the outlier detection circuit (signal comparison means) 150 arranged on the vertical readout line 142 is not shown in the drawing, its output is supplied to a shift register (signal transfer means) as in the sixth embodiment. Is connected to the data input terminal of the corresponding bit register. The output signal from the outlier detection circuit 150 (an outlier signal representing the difference between the electric signal in the immediately preceding frame and the electric signal in the current frame) corresponds to a shift register (not shown in FIG. 14) at a predetermined timing. The data is stored in a register and sequentially output from an output terminal according to a clock pulse input to the shift register.

The configuration of the outlier detection circuit 150 is the same as that of the fifth embodiment.
This is the same as the outlier detection circuit 60 of the embodiment. That is, the different value detection circuit 150 includes two capacitors CCA and CCB and five inverters IN as shown in FIG.
V1 to INV5, four switching MOS transistors QB1 to QB4, and an OR circuit OR.

The capacitor CCA and the switch M
The first sample and hold circuit 150A is connected to the capacitor CCB and the switch M by the OS transistor QB1.
A second sample and hold circuit 150B is configured by the OS transistor QB2. The output of the OR circuit OR is the output of the different value detection circuit 150.

Next, the operation of the solid-state imaging device 140 for motion detection will be described with reference to the timing chart shown in FIG. FIG. 15 shows that, as in FIG. 12, one pixel 141 for detecting incident light
A case is shown in which incident light is detected in a frame (the (N-1) th frame and the Nth frame) and the reading operation is performed. This timing chart is based on the outlier detection circuit 15.
The operation of the solid-state imaging device 140 for motion detection is not described, and the operation of the solid-state imaging device 140 for motion detection is not described.

The operation immediately before the period t20 of the Nth frame in FIG. 15 will be described. First, the period t2 of the Nth frame
Before reaching 0 (the period t14 of the (N-1) th frame), the driving pulse φTG, the driving pulse φRSG, and the driving pulse φP are held at a high level, the driving pulse φSA is held at a low level, and the driving pulse φSB is set at a high level. Is held.

Accordingly, the transfer MOS transistor QT is turned off, and the reset MOS transistor QP is also turned off. At this time, the gate (control region) of the amplifying transistor QA is in a floating state. , The signal charge already transferred to the gate (control region), that is, the voltage corresponding to the charge (first signal charge) corresponding to the incident light in the immediately preceding frame is held in a biased state, On the diode PD side, charges (second signal charges) corresponding to the incident light in the current frame
Are generated and accumulated.

Then, when the period t20 is reached, the driving pulse φP becomes low level, the pixel separating MOS transistor QX is turned on (selected), and an electric signal (voltage signal) corresponding to the first signal charge is obtained. By the source follower operation of the amplifying transistor QA, two capacitors CCA and CC
B is supplied to one of the electrodes CCA1 and CCB1. Also, the drive pulse φSA becomes high level, and the other electrodes CCA2 and CCB of the two capacitors CCA and CCB
2, constant voltages VR1 (= VT−Vth) and VR2 (=
VT + Vth).

The drive pulse φSB goes low, and the output terminal of the inverter INV3 outputs the drive signal φSB.
Path to input terminal of NV1 and inverter INV4
From the output terminal of the inverter INV2 to the input terminal of the inverter INV2.

At this time, the electric potential difference between both ends of the capacitor CCA is determined by the electric signal (denoted as VA) corresponding to the incident light in the (N-1) th frame and the constant voltage VR1 (= VT−Vt).
h; here, Vth is the difference from the first predetermined value).
On the other hand, in the capacitor CCB, the potential difference between both ends is Nth.
Signal VA and constant voltage VR2 in -1 frame
(= VT + Vth; here, Vth is a second predetermined value).

At time t21, drive pulse φSA is inverted to low level, and the difference between electric signal VA and constant voltage VR1 (= VT−Vth) in the (N−1) th frame is stored at both ends of capacitor CCA. The difference between the electric signal VA in the (N-1) th frame and the constant voltage VR2 (= VT + Vth) is stored at both ends of the capacitor CCB.

At this time, the drive pulse φRSG goes low, and the charge stored in the gate (control region) of the amplification transistor QA is discharged (reset). In the period t22, the drive pulse φRSG becomes high level, and the reset is released. When the drive pulse φTG becomes low level, the charge (second signal charge) corresponding to the incident light generated and accumulated in the photodiode PD up to this point is newly added to the gate (control signal) of the amplifying transistor QA. Area) via the transfer MOS transistor QT.

In this case, the amplifying transistor QA performs a source follower operation, and a second output signal (second electric signal) corresponding to the second signal charge is transferred to the vertical read line 142 (at this time, the drive is performed). The pulse φP is already at low level and the amplifying transistor QA is on). When the period t23 is reached, the drive pulse φTG is inverted to the high level, and the drive pulse φTG is transferred to the gate (control region) of the transistor QA for amplifying the charge (second signal charge) generated and stored in the photodiode PD according to the incident light. Is completed.

At this time, the gate (control region) of the amplifying transistor QA is again in a floating state. However, due to the effect of the parasitic capacitance, the voltage of the gate is increased by the amount of the transferred charge (second signal charge). That state is maintained while being raised. In this case, the electric signal (V) corresponding to the electric charge (second signal electric charge) stored in the gate is output from the amplifying transistor QA by the source follower operation.
B) is output to one electrode CCA1, CCB1 of two capacitors CCA, CCB.

In this embodiment, as in the fifth embodiment, the potential of the electrode CCA1 of the capacitor CCA is input to the inverter INV1 as a signal, and after being inverted by the inverter INV3 and the inverter INV5, the logical sum is obtained. The signal is transferred to one input terminal of the circuit OR. The potential of the electrode CCB1 of the capacitor CCB is input as a signal to the inverter INV2,
After being inverted by 4, the signal is transferred to the other input terminal of the OR circuit OR.

When the period t24 is reached, the drive pulse φP goes high, the amplifying transistor QA turns off (non-selected) again, the drive signal φSB goes high, and the output terminal of the inverter INV3 and the inverter INV3.
1 are connected to each other to form a closed loop, while the output terminal of the inverter INV4 is connected to the inverter INV4.
The two input terminals are connected to form a closed loop.

By forming a closed loop between the inverter INV3 and the inverter INV1, the output of the inverter INV1 is fixed.
By forming a closed loop between the inverter INV4 and the inverter INV2, the output of the inverter INV2 is fixed. In the outlier detection circuit 150 according to the eighth embodiment, its output (the output of the OR circuit OR) is
Like the outlier detection circuit 60 of the fifth embodiment, (1)
When VB becomes larger than (VA + Vth), that is,
When (VB−VA) becomes larger than Vth, (2)
When VB becomes smaller than (VA-Vth), that is, when any of the conditions when (VA-VB) becomes larger than Vth is satisfied, a signal of a logic high level is output. I have.

Note that also in the eighth embodiment, the voltage signal (different value signal) supplied to the horizontal read line (not shown) is already binarized (digitized) by the different value detection circuit 150. Therefore, the speed of the read operation is increased. Further, since the signal read to the horizontal read line is a digital signal, the signal can be output without being affected by noise.

In the eighth embodiment, the pixel 14
Although the case where a MOS transistor is used as means for connecting / disconnecting the vertical read line 142 from the pixel 1 has been described, as described in the seventh embodiment and the like, the gate of the amplification transistor QA of the pixel 141 is connected via a capacitor. You may use it so that a connection / separation signal may be given. Further, in the first to eighth embodiments, the photoelectric conversion element of the pixel is described as a photodiode, but it can be easily formed as a buried photodiode. Since the depletion layer generated at the pn junction can be prevented from reaching the surface by using a buried photodiode as the photoelectric conversion element, dark current can be suppressed, and charge is transferred to the photodiode after signal charges are transferred. Is not left, and ideal characteristics in which afterimages and reset noise are suppressed can be obtained.

In the first to eighth embodiments, the case where the amplifying section (amplifying transistor QA) of each of the pixels 1, 21, 51, 101, 131, and 141 is used as a JFET has been described. Is not limited to this,
MOS transistors and bipolar transistors can also be applied to devices that can control output voltage and current such as drain or collector, source or emitter by the voltage of control electrodes such as gate and base,
They may be used in combination.

In the first to eighth embodiments, the case has been described in which the charge corresponding to the incident light generated by the photoelectric conversion element is directly transferred to the control region of the amplification element. The present invention is not limited to this, and is similarly applicable to a case where charges corresponding to incident light are transferred to a diffusion region and held, and then the potential is detected at a gate of an amplification element such as a MOS transistor via a signal line. Needless to say. Examples of such a pixel include, for example, a document “Acti
ve Pixel Sensors: Are CCD's Dinosaurs? ', Fossum E.
R., Proceeding of SPIE: Charge-Coupled Device and S
olid State Optical Sensors III, Vol. 1900, pp2-14 (199
The one described in 3) is well known.

Further, in the first to eighth embodiments, the case where the pixels 1 are arranged in a two-dimensional matrix has been described. However, the present invention can be similarly applied to the case where the pixels 1 are arranged in a one-dimensional manner.

[0235]

According to the first to fifteenth aspects of the present invention, the luminance difference between two consecutive frames can be binarized and output at the time of transferring the luminance difference to the horizontal readout line. Moving object image processing can be performed in the apparatus, and it is not necessary to provide peripheral circuits such as an AD conversion circuit, an image memory, and an image processing circuit outside the apparatus, and the cost of the entire apparatus can be reduced.

In addition, since the externally required AD conversion circuit is no longer necessary, the dynamic range is not limited, and the signal processing can be performed in the wide dynamic range of the motion detection solid-state imaging device itself. it can. Further, since there is no need to provide a circuit (signal comparing means) for generating a different value signal for each pixel, the aperture ratio and the resolution are improved.

Further, since the different value signal is generated by using the electric signal output from the pixel as the electric signal for the immediately preceding frame and the electric signal for the current frame, the fixed pattern noise and the fixed pattern noise for each amplifying transistor are generated. The moving object detection process can be performed without being affected by random noise, and a highly accurate and stable moving object detection process can be performed.

Further, since the different value signal is a binarized signal at the time of reading to the horizontal read line, the processing can be speeded up. According to the fourth aspect of the present invention, the binarized different value signal is stored in the register of the shift register, and thereafter, the binary signal is output to the horizontal read line in synchronization with the clock pulse input to the shift register. Since the output is performed, the signal processing can be further speeded up.

Further, according to the inventions of claims 5 to 14, in each pixel, the electric charge generated and accumulated in the photoelectric conversion element is directly transferred to the control region of the amplifying means. Signal deterioration due to charge distribution or the like is suppressed as compared with the case where charges are transferred using lines, and the image S / N ratio is improved. According to the fifteenth aspect of the present invention, the dark current is suppressed, and no charge remains in the photodiode after the signal charge has been transferred, so that ideal characteristics in which afterimages and reset noise are suppressed are obtained. be able to.

[Brief description of the drawings]

FIG. 1 is a schematic circuit diagram illustrating a schematic configuration of a solid-state imaging device for motion detection 10 according to a first embodiment of the present invention.

FIG. 2 is a timing chart illustrating the operation of the motion detection solid-state imaging device 10.

FIG. 3 is an outlier detection circuit 7 of the solid-state imaging device 10 for motion detection.
FIG. 2 is a circuit diagram showing an internal configuration of the device.

FIG. 4 is a characteristic diagram showing an example of input / output characteristics of an outlier detector XA in an outlier detector 7;

FIG. 5 is a schematic circuit diagram illustrating a schematic configuration of a motion detection solid-state imaging device 20 according to a second embodiment of the present invention.

FIG. 6 is a schematic circuit diagram illustrating a schematic configuration of a solid-state imaging device 30 for motion detection according to a third embodiment of the present invention.

FIG. 7 is a timing chart for explaining the operation of the motion detection solid-state imaging device 30;

FIG. 8 is a schematic circuit diagram illustrating a schematic configuration of a motion detection solid-state imaging device 40 according to a fourth embodiment of the present invention.

FIG. 9 is a schematic circuit diagram illustrating a schematic configuration of a solid-state imaging device for motion detection 50 according to a fifth embodiment of the present invention.

FIG. 10 is a timing chart for explaining the operation of the solid-state imaging device for motion detection 50;

FIG. 11 is a schematic circuit diagram illustrating a schematic configuration of a solid-state imaging device for motion detection 110 according to a sixth embodiment of the present invention.

FIG. 12 is a timing chart for explaining the operation of the solid-state imaging device for motion detection 110;

FIG. 13 is a schematic circuit diagram illustrating a schematic configuration of a solid-state imaging device for motion detection 120 according to a seventh embodiment of the present invention.

FIG. 14 is a schematic circuit diagram illustrating a schematic configuration of a motion detection solid-state imaging device 140 according to an eighth embodiment of the present invention.

FIG. 15 is a timing chart illustrating the operation of the solid-state imaging device for motion detection 140.

FIG. 16 is a block diagram showing a conventional image processing apparatus 200 for motion detection for generating a different value signal.

[Explanation of symbols]

1, 21, 51, 101, 131, 141 Pixels 2a, 2b, 102a, 102b, 142 Vertical read line 6, 106 Vertical scanning circuit (vertical scanning means) 7, 60, 107, 150 Different value detection circuit (signal comparing means 8a, 8b, 108a, 108b Clock lines 9a, 9b, 109a, 109b Clock lines 10, 20, 30, 40, 50, 110, 120, 14
0 solid-state imaging device for motion detection 12, 112 horizontal readout line 13 horizontal scanning circuit (signal transfer means) 113 shift register (signal transfer means) PD photodiode (photodetection means: photoelectric conversion element) QA amplifying transistor (junction electric field) Effect transistor: amplifying means) QH1, QH2 MOS transistor for horizontal readout switch (switching means: signal transfer means) CO1, CO2 Capacitor for storing different value signal (signal charge storage means) QT MOS transistor for transfer (transfer means) QP reset MOS transistor (reset means) QX MOS transistor for pixel separation (connection / separation means) QR MOS transistor for switch (first switch means) QS MOS transistor for switch (second switch means) CG Capacitor (connection / separation means) CR Signal storage capacitor (first charge storage means) CS Signal storage capacitor (second charge storage means) XA Different value detector INV1, INV2 Inverter (binarization means) CCA capacitor (first sample hold circuit) CCB capacitor (second sample hold circuit) CV hold capacitance QV switch MOS transistor

Claims (15)

[Claims] 1. A plurality of pixels arranged in a matrix and outputting an electric signal according to incident light, a plurality of vertical read lines provided for each of the plurality of pixels, and identification of the plurality of pixels Vertical scanning means for selecting a row and transferring an electric signal from the pixel to the vertical readout line at a constant timing; and an electric device arranged on the vertical readout line and output from the pixel at a constant timing. A signal that stores the signal as an electric signal for the immediately preceding frame, compares the stored electric signal with the electric signal for the current frame output from the pixel at the next fixed timing, and indicates a result of the comparison. Signal comparing means for outputting a signal representing the result of the comparison output from each of the plurality of vertical read lines, sequentially to a horizontal read line. Motion detection for a solid-state imaging apparatus characterized by and a signal transfer means for feeding. 2. The signal transfer means includes: switch means for connecting / disconnecting the vertical read line and the horizontal read line; and a horizontal scanning circuit for outputting a signal for controlling on / off of the switch means. The solid-state imaging device for motion detection according to claim 1, wherein: 3. A signal charge accumulating means for accumulating electric charge according to a signal from the signal comparing means is disposed on the vertical read line, and the switch means comprises a signal charge accumulating means, the horizontal read line, The solid-state imaging device for motion detection according to claim 2, wherein the solid-state imaging device is disposed between the solid-state imaging devices. 4. The signal transfer means is constituted by a shift register arranged on the plurality of vertical read lines, and an input terminal thereof is connected to each of the plurality of vertical read lines. 2. The motion detecting device according to claim 1, wherein the signal output from each of the vertical readout lines is stored, and the stored signal is sequentially output from its output terminal in accordance with an external clock signal. Solid-state imaging device. 5. A photodetector, wherein the pixel generates and accumulates a charge corresponding to incident light, a charge holding unit that holds a charge corresponding to the incident light from the photodetector, and A signal generation unit for generating an electric signal according to the held electric charge, and a connection / separation unit for connecting / separating the signal generation unit of the pixel and the vertical readout line. The solid-state imaging device for motion detection according to claim 1. 6. The photodetector includes a photoelectric conversion element that generates and accumulates a charge according to incident light, and an output side of the photoelectric conversion element is connected to an amplifying unit of a pixel. 6. The solid-state imaging device for motion detection according to claim 5, wherein when a charge corresponding to the incident light is held in the control region, an electric signal corresponding to the charge is output. 7. The pixel, wherein: a transfer unit that directly transfers a charge generated by the photoelectric conversion element to a control region of the amplifying unit; and a charge that is accumulated in the control region of the amplifying unit is emitted outside the pixel. 7. The solid-state imaging device for motion detection according to claim 6, further comprising: a reset unit configured to connect / separate the amplifying unit of the pixel and the vertical readout line. 8. The amplifying means is constituted by a junction field effect transistor, and a charge corresponding to the incident light is directly transferred to the gate, and a current between the source and the drain corresponds to the charge. The solid-state imaging device for motion detection according to claim 6, wherein the solid-state imaging device according to claim 6, wherein the value is controlled to a value obtained by the adjustment. 9. The switching device according to claim 8, wherein said connection / separation means comprises a switching MOS transistor interposed between a source of said junction field effect transistor and a vertical read line. Solid state imaging device for motion detection. 10. The connection / separation means comprises a capacitor connected to the gate of the junction field-effect transistor, and a connection / separation signal is applied to one terminal of the capacitor to connect the amplification means to the one terminal. 9. The solid-state imaging device for motion detection according to claim 8, wherein connection / disconnection with the vertical read line is performed. 11. The signal comparing means, when the magnitude of the difference between the value of the electrical signal for the current frame and the value of the electrical signal for the immediately preceding frame is equal to or greater than a predetermined value, The solid-state imaging device for motion detection according to any one of claims 1 to 10, wherein a signal indicating a level is output. 12. The signal comparing means includes: first charge storage means for storing an electric signal for the immediately preceding frame; and second charge storage means for storing an electric signal for the current frame. When the magnitude of the difference between the electric signal for the immediately preceding frame stored in the first charge storage means and the electric signal for the current frame stored in the second charge storage means is greater than or equal to a predetermined value, The solid-state imaging device for motion detection according to any one of claims 1 to 11, which outputs a signal indicating a logical low level or a logical high level. 13. A first switch means between the vertical read line and the first charge storage means, and a second switch between the vertical read line and the second charge storage means. The first switch means and the second switch means are connected to a charge storage control means, and the vertical scanning means switches the connection / separation means when a specific row is selected. After transferring an electric signal corresponding to the electric charge stored in the control region of the amplifying unit of the pixel to the vertical readout line as an electric signal for the immediately preceding frame, using the reset unit to control the amplifying unit The charge accumulated in the region is released to the outside of the pixel, and thereafter, the charge generated and accumulated in the photoelectric conversion element is newly transferred to the control region of the amplifying unit using the transfer unit. After that, an electric signal corresponding to the electric charge transferred to the control area is transferred to the vertical readout line as an electric signal for the current frame, and the electric charge accumulation control unit sets the electric signal for the immediately preceding frame to be vertical. The first switch means is turned on at the timing of appearing as a charge on the readout line, and the charge is stored in the first charge storage means. At the timing at which the electric signal for the current frame appears as a charge on the vertical readout line. The solid-state imaging device for motion detection according to claim 12, wherein the second switch is turned on to accumulate the electric charge in the second electric charge accumulating means. 14. The signal comparing means includes: a binarizing means having two input terminals; a first sample and hold circuit connected to one input terminal of the binarizing means; A second sample-and-hold circuit connected to the other input terminal of the first and second circuits, and using the first sample-and-hold circuit, a value of an electric signal for the current frame and a value of an electric signal for the immediately preceding frame. And outputs a signal indicating a logical high level or a logical low level when the difference with respect to the first predetermined value is higher than the first predetermined value. Outputting a signal indicating a logical high level or a logical low level when a difference between the value of the electrical signal and the value of the electrical signal for the frame is higher than a second predetermined value. Claim items 1 1
2. The solid-state imaging device for motion detection according to claim 1. 15. The pixel according to claim 1, wherein the pixel includes a buried photodiode as a photoelectric detection unit that generates a charge according to incident light.
The solid-state imaging device for motion detection according to any one of the above.