JPH10312690A - Read-write non-volatile memory circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a non-volatile memory circuit for enabling read and write which stores data even after power source is interrupted or a circuit with its equivalent function in an integrated circuit device to be used for a portable appliance, etc., of which the power source energy is limited. SOLUTION: A first memory circuit 10 composed from non-volatile memory alone and a second memory circuit 11 of comparatively low power consumption are installed. Only when the power source is interrupted, the first memory circuit 10 is used and usually the second memory circuit is controlled so as to make read and write operations. Therefore, even when the power is interrupted, data is stored in the non-volatile memory and in addition the non-volatile memory is usually not employed so that a low-powered integrated circuit device which is suitable for portable appliances is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a circuit configuration for operating a readable and writable nonvolatile memory circuit in a semiconductor integrated circuit with low power consumption.

[0002]

2. Description of the Related Art A conventional readable / writable nonvolatile memory circuit generally has a floating gate as shown in the examples of E2PROM and FLASH, and has a circuit configuration in which the memory circuit is directly used for both read operation and write operation. I was

[0003]

The above-mentioned conventional readable and writable nonvolatile memory circuit requires a high voltage to inject electric charges into the floating gate at the time of writing. Therefore, there is a problem that frequent writing operation consumes a large amount of power.

In a read operation, since a floating gate is used, the driving capability is weak, and the read / write operation circuit is complicated. Therefore, the data read speed is reduced to that of a normal static random access memory (hereinafter abbreviated as SRAM). There was a problem that it was extremely slow in comparison.

Accordingly, the present invention is to solve such a problem. The purpose of the present invention is to enable low-power consumption and high-speed read operation in normal use, and to retain data even when the power is turned off. It is an object of the present invention to provide a low-power readable / writable nonvolatile memory circuit to be stored.

[0006]

According to the present invention, there is provided a read / write nonvolatile memory circuit comprising: a) a read / write nonvolatile memory circuit of a semiconductor integrated circuit; b) a first read / write nonvolatile memory circuit; And d) writing data to the first memory circuit with a first type of write signal and the second type of read signal with a second type of read signal.
Read data from the memory circuit, read data from the first memory circuit with a third type of read / write signal, and write the data to the second memory circuit.
It is characterized by comprising a read / write control circuit.

[0007] A readable / writable nonvolatile memory circuit according to the present invention is characterized in that the second memory circuit comprises a static random access memory circuit.

In a readable / writable nonvolatile memory circuit according to the present invention, the second memory circuit comprises a latch circuit.

The read / write nonvolatile memory circuit according to the present invention includes: a) a read / write nonvolatile memory circuit of a semiconductor integrated circuit; b) a first read / write nonvolatile memory circuit; and c) a second read / write nonvolatile memory circuit. D) a power supply voltage detecting circuit for monitoring a power supply operating the first memory circuit and the second memory circuit; and e) a normal power supply and a backup power supply are connected to a signal of the power supply voltage detecting circuit. A) a power supply control circuit switched by the following: f) A fourth type of write signal writes data only to the first memory circuit, and a second type of read signal reads data only from the second memory circuit. With three types of read / write signals, data is read from the first memory circuit, and the data is written to the second memory circuit. In the left fifth type of read write signal subjected to signal the circuit reads data from said second memory circuit, and writes the data to the first memory circuit, characterized by comprising the read write control circuit.

In a readable / writable nonvolatile memory circuit according to the present invention, the second memory circuit comprises a static random access memory circuit.

In a readable / writable nonvolatile memory circuit according to the present invention, the read / write control circuit is a microprocessor,
It is performed by a combination of instructions such as a microcomputer and a central processing unit.

[0012]

According to the above configuration of the present invention, the normal data read / write operation is performed by the second memory circuit composed of an SRAM or the like. In this case, the data is stored in the first readable / writable nonvolatile memory circuit, so that a readable / writable nonvolatile memory circuit having both the non-volatility of data, low power consumption, and high-speed reading operation characteristics is realized.
The normal data reading and writing is performed by the second
And the operation of the first readable / writable nonvolatile memory circuit is limited to the minimum necessary.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to embodiments. FIG. 1 is a circuit diagram showing a first embodiment of the present invention. In FIG. 1, reference numeral 10 denotes a first memory circuit, which is, for example, a readable / writable nonvolatile memory circuit constituted by an E2PROM. Reference numeral 11 denotes a second memory circuit, for example, an SRAM. Reference numeral 12 denotes a read / write control circuit. Data write operation to memory is E2PR
This is performed by a WRITE1 signal through the signal line 101 to the first memory 10 composed of the OM. The normal read operation is performed by the signal READ1 through the signal line 104, and is performed only on the second memory circuit formed of the SRAM. Data transfer from the first memory circuit 10 to the second memory circuit 11 is performed by a signal RW3 including a read operation through the signal line 102 and a write operation through the signal line 103. At this time, data is transferred from the signal line 105 to the signal line 106 via the signal line 107.
Pass through. The read / write control circuit 12 controls the above operation. This configuration is suitable for using the first memory circuit 10 as a read-only memory (ROM). Only at the time of initial setting, data is written in the first memory constituted by the E2PROM, and the data is stored in the SRAM. Is transferred to the second memory circuit 11 composed of After that, data reading is performed by the second memory circuit 11. E
The 2PROM has the advantage of retaining data even when the power is turned off, but requires a very large voltage and power in a write operation that requires injecting charges into a floating gate for storing data. In addition, the reading speed is very slow due to a special structure for reading the data of the floating gate. On the other hand, an SRAM can perform low-power consumption and high-speed read operation. Therefore, writing of data with a very small number of times and holding of data when the power is turned off are performed by E2
The PROM and the repeated reading of data by performing the SRAM can provide a low-power readable / writable nonvolatile memory circuit having characteristics of data non-volatility, low power consumption, and high-speed reading operation.

Note that the first memory circuit 10 is E2PRO
Although it is simply expressed as M, a wide-read / write nonvolatile memory circuit including a FLASH type can be applied.

Although the second memory circuit 11 is an SRAM, it may be a latch circuit when the storage capacity is relatively small. Further, in the present embodiment, only the initial setting is performed. However, it is also possible to perform writing to the first memory when necessary and similar to this, and a certain effect can be obtained.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention. In FIG. 2, reference numeral 20 denotes a first memory circuit, which is, for example, a readable / writable nonvolatile memory circuit composed of an E2PROM. Reference numeral 21 denotes a second memory circuit, for example, an SRAM. Reference numeral 22 denotes a read / write control circuit, reference numeral 23 denotes a power supply voltage detection circuit, reference numeral 24 denotes a supply power supply control circuit, and a broken line 25 indicates a boundary between the inside and the outside of the integrated circuit device. Negative power is supplied to the power supply control circuit 24 through a terminal 213, and
The normal power supply is supplied through the
5, the positive power of the backup battery is supplied, and the normal power is supplied to the positive and negative power supplies 211 and 212 of the integrated circuit device or the backup power is supplied by the signal line 210 of the power supply voltage detection circuit 23. Switch. Note that the normal power supply and the backup battery exist outside the semiconductor integrated circuit device equipped with the present invention. By the way, the normal data write operation to the memory is performed through the signal line 203 to the second memory 21 composed of the SRAM through the WR.
This is performed by the signal of ITE2. The normal read operation is performed with the signal READ1 through the signal line 204,
This is performed on the second memory circuit 21 composed of AM.
Also, the first memory circuit 20 to the second memory circuit 21
The transfer of data to the RW consists of a read operation through the signal line 202 and a write operation through the signal line 203.
3 is performed. The transfer of data from the second memory circuit 21 to the first memory circuit 20 is performed on the signal line 20.
4 and a write operation through the signal line 201. Further, the power supply voltage detection circuit 23 senses a decrease or disconnection of the voltage of the normal power supply coming from the terminals 213 and 214 and passing through the signal line 209, and notifies the read / write control circuit 22 through the signal line 208. The read / write control circuit 22 first responds to the signal of the RW4 by using the second memory circuit 21 composed of an SRAM which manages normal data.
, And writes the data into the first memory circuit 20 composed of an E2PROM, and retains the data even when the power is turned off. The backup battery only needs to have an ability to supply power during data transfer by the RW4. After the power is restored, the power supply voltage detection circuit 23 detects the power and transmits it to the read / write control circuit 22 through the signal line 208. The read / write control circuit 22 responds to the RW3 signal to
The stored data is read from the first memory circuit 20 composed of 2PROM and written to the second memory circuit 21 composed of SRAM. The read / write control circuit 22 controls the above operation. This configuration is suitable when the first memory circuit 20 is used as a random access memory (RAM). When the power supply drops or the power is cut off, the first memory circuit 20 retains data using an E2PROM. One memory circuit 20 performs normal data read / write management in a second memory circuit 21 composed of an SRAM, which has the characteristics of non-volatility of data, low power consumption, and high-speed read operation. A low-power readable / writable nonvolatile memory circuit can be provided.

The second memory circuit 21 is an SRAM, but may be a dynamic random access memory.

The read / write control circuit 22 is not an independent circuit, but may be a microprocessor, microcomputer, central processing unit (CPU).
Etc. may be performed in combination.

Although an example using a backup battery has been described, a capacitor having a large capacitance may be used.

[0020]

As described above, according to the present invention, E2
Low power consumption and high-speed access operation by using a combination of a first memory circuit such as PROM which has non-volatility of data and a second memory circuit such as SRAM which has characteristics of low power consumption and high speed reading. The non-volatile memory circuit described above can be provided.

Further, according to the present invention, the number of times the nonvolatile memory circuit is directly operated is greatly reduced, so that the life of the nonvolatile memory is extended.

Further, according to the present invention, the number of times of directly operating the nonvolatile memory circuit is greatly reduced, so that the nonvolatile memory circuit can be used even with a low-reliability nonvolatile memory, and the cost can be reduced indirectly. .

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

[Explanation of symbols]

10, 20 ... first memory circuit 11, 21 ... second memory circuit 12, 22 ... read / write control circuit 23 ... power supply voltage detection circuit 24 ... supply power supply control circuit 25 .. boundary 101, 103, 201, 203 between the inside and outside of the integrated circuit device ... write signal line 102, 104, 202, 204 ... read signal line 105, 106, 107, 205, 206, 207
-Data signal lines 208, 210 ... Power supply voltage detection circuit signal lines 209, 214 ... Positive power supply for normal power supply 211 ... Positive power supply for integrated circuit device 212, 213 ... Negative power supply for integrated circuit device 214: Positive power supply for normal power supply 215 ... Positive power supply for backup power supply

Claims (6)

[Claims] 1. A read / write nonvolatile memory circuit of a semiconductor integrated circuit, wherein: b) a first read / write nonvolatile memory circuit; c) a second read / write memory circuit; and d) a first type write. A signal writes data to the first memory circuit, and a second type of read signal writes the data to the second memory circuit.
Read data from the memory circuit, read data from the first memory circuit with a third type of read / write signal, and write the data to the second memory circuit.
A readable / writable nonvolatile memory circuit comprising a read / write control circuit. 2. The read / write nonvolatile memory circuit according to claim 1, wherein said second memory circuit comprises a static random access memory circuit. 3. The read / write nonvolatile memory circuit according to claim 1, wherein the second memory circuit comprises a latch circuit. 4. A read / write nonvolatile memory circuit of a semiconductor integrated circuit, comprising: b) a first read / write nonvolatile memory circuit; c) a second read / write memory circuit; and d) the first memory. A power supply voltage detection circuit that monitors a circuit and a power supply operating the second memory circuit; e) a supply power supply control circuit that switches between a normal power supply and a backup power supply by a signal of the power supply voltage detection circuit; ) A fourth type of write signal writes data only to the first memory circuit, a second type of read signal reads data only from the second memory circuit, and a third type of read / write signal A fifth type of read / write that receives data from the power supply voltage detection circuit by reading data from the first memory circuit and writing the data into the second memory circuit; In signal only reading data from the second memory circuit, and writes the data to the first memory circuit, readable and writable nonvolatile memory circuit, comprising the read write control circuit. 5. The read / write nonvolatile memory circuit according to claim 4, wherein the second memory circuit comprises a static random access memory circuit. 6. A readable / writable nonvolatile memory circuit, wherein the read / write control circuit according to claim 4 is implemented by a combination of instructions such as a microprocessor, a microcomputer, and a central processing unit.