JPH10308634A - Cascode amplifier circuit and comparator circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain power consumption reduction and operation acceleration by providing an emitter grounded bipolar type transistor and a field effect type transistor specifying the connection of source, drain and gate. SOLUTION: A cascode amplifier circuit 20 is provided with an emitter grounded bipolar type transistor 24 which connects its base to an input terminal 22 and is driven by an input voltage Vi supplied to its base, and a field effect type transistor 29 which connects its source with the collector of bipolar type transistor, connects its drain to an output terminal 26 and connects its gate to a bias power source 28 under cascode connection with the bipolar type transistor 24. Because of high mutual conductance gm at the bipolar type transistor 24, a large current is driven by the slight amplitude of input voltage Vi applied from the input terminal 22. Besides, the bipolar type transistor 24 has parasitic capacitances Ccb and Ccs but lowers the impedance of collector part and reduces the phase delay of collector part.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a high-frequency amplifier circuit. In particular, the present invention relates to a low-power-consumption type, wide-band output amplifier circuit in which two transistors are cascaded, and a comparator circuit using the amplifier circuit.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram of a wideband output circuit described in Japanese Patent Application Laid-Open No. 5-218755. In the figure, the broadband output circuit is constituted by first and second transistors Q17 and Q18, and the collector is the first.
And input voltages V1 and V2 connected to the second output terminals P10 and P11 and supplied to the base, respectively.
Is provided outside the integrated circuit 11 on which the differential amplifier is mounted, and the base is connected to the DC power supply terminal P13, and the first amplifier is connected via the first output terminal P10. A third transistor Q11 cascode-connected to the transistor Q17, and a third transistor Q
11 and a second output terminal P
11, a fourth transistor Q12 cascode-connected to the second transistor Q18, and a collector of the third transistor Q11. The third transistor Q11 is connected to the first transistor Q11 via the first output terminal P11. An external load resistor R11 for converting a collector current I1 supplied to the transistor Q17 into an output voltage Vout;
The load capacitance C1 parasitic on the output terminal P10 is driven by the collector current I1.

In the above-mentioned wideband output circuit, a signal output of the integrated circuit 11 is used as a collector current I1 flowing through the first and third transistors, and a load capacitance C1 parasitic to the first output terminal is output.
, The influence of the load capacitance C1, which had degraded the frequency characteristics, can be neglected, and the frequency characteristics have been extended to a high frequency range.

[0004]

However, the wideband output circuit described above has a drawback that when the current flowing through the load resistor R11 is increased to increase the voltage amplification Av, the power consumption of the entire circuit increases.

Although it is conceivable to increase the value of the load resistor R11, the third transistor Q11
Is an NPN structure, the parasitic capacitance C between the collector and the base
cb and a parasitic capacitance Ccs between the collector and the substrate,
In particular, the junction capacitance Ccs between the collector and the substrate is as large as 3 to 4 pF, and the load resistance R11 and the parasitic capacitance (Ccb + Ccs) of the third transistor Q11 cause a phase delay of a signal, thereby hindering high-speed response.

The present invention has been made in order to solve the above-mentioned drawbacks. Even if the parasitic capacitance at the connection point for outputting the voltage V3 is small and the load resistance R11 is increased to increase the voltage amplification, the output is reduced. It is an object of the present invention to provide a cascode amplifier circuit having a small phase delay at a connection point for outputting a voltage and having excellent high-speed response.

Another object of the present invention is to provide a high-speed comparator circuit with low power consumption and high gain by using a cascode amplifier circuit in a differential amplifier stage constituted by a pair of transistors.

Another object of the present invention is to provide a one-chip IC comparator that operates at a lower speed and consumes less power than a conventional one by using a BiCMOS process in which a bipolar element and a CMOS element are mounted together.

[0009]

According to a first aspect of the present invention, a base-connected bipolar transistor having a base connected to an input terminal and driven by an input voltage supplied to the base is provided. And a field effect transistor having a cascode connection with the bipolar transistor, a source connected to the collector of the bipolar transistor, a drain connected to the output terminal, and a gate connected to the bias power supply.

According to a second aspect of the present invention, in order to solve the above-mentioned problem, an emitter is commonly connected to a reference voltage source via a constant current source, and a pair of bipolar transistors whose gates are respectively connected to input terminals. And a cascode connection to at least one of the pair of bipolar transistors, a source connected to the collector of the bipolar transistor, a drain connected to the output terminal, and a gate connected to the bias power supply. And an effect-type transistor.

[0011]

According to the present invention having the above structure, the field effect transistor having a small parasitic capacitance is cascode-connected to the bipolar transistor having a high transconductance gm to reduce the phase delay at the output portion, thereby increasing the load resistance. Even so, an amplifier circuit with high gain and low power consumption can be obtained.

Further, since the above-mentioned amplifier circuit is used in the differential amplifier stage, the comparator can be operated at high speed.

[0013]

Preferred embodiments of the present invention will be described below with reference to the drawings. This circuit is not particularly limited, but is configured for an input voltage range of 0V to 5V.

FIG. 1 is a block diagram of a cascode amplifier circuit 20 according to an embodiment of the present invention. In the figure, a cascode amplifying circuit 20 has a base connected to an input terminal 22, a bipolar transistor 24 having a common emitter driven by an input voltage Vi supplied to the base, a cascode connection with the bipolar transistor 24, and a source. Are connected to the collector of the bipolar transistor, the drain is connected to the output terminal 26, and the gate is connected to the bias power supply 28.
With the high transconductance gm of the bipolar transistor 24, a large current can be driven with a small amplitude of the input voltage Vi applied from the input terminal 22. The bipolar transistor 24 has a parasitic capacitance Ccb, between the collector and the base and between the collector and the substrate.
Although it has Ccs, it is possible to reduce the impedance of the collector part and reduce the phase delay of the collector part by cascode connection with the field-effect transistor 29.

FIG. 2 is a block diagram showing the parasitic capacitance of the field effect transistor 29. In the figure, an n-channel type field effect transistor 29 has a gate, a drain, and a source, and has a parasitic capacitance between each terminal and a back gate connected to the substrate side. The illustrated parasitic capacitance includes Cgd between the gate and the drain, Cdb between the drain and the back gate, Csb between the back gate and the source, Cgs between the source and the gate, and Cgb between the gate and the back gate. Parasitic capacitance C of the drain of the n-channel type field effect transistor 29
The values of gd and Cdb are smaller by about two digits than the parasitic capacitance Ccb between the collector and the base of the bipolar transistor 24 and the parasitic capacitance Ccs between the substrates. For example, Cgd
Is 0.01 to 0.02 pF, and Cdb is 0.02 to 0.03 pF. That is, the bipolar transistor has a large collector island region for element isolation, a large junction area between the collector and the substrate, and a large parasitic capacitance Ccs between the collector and the substrate. Therefore, the area of the drain region can be made much smaller than the collector of the bipolar transistor, and the parasitic capacitance can be made smaller. Therefore, the parasitic capacitance Cdb between the drain and the back gate is equal to the parasitic capacitance Cdb between the collector of the bipolar transistor and the substrate.
It is orders of magnitude smaller than cs. Further, the parasitic capacitance Cgd between the drain and the gate is only the capacitance of the overlapped portion via the gate oxide film, and can be extremely reduced. If a self-alignment process is used, the parasitic capacitance can be further reduced. Therefore, by reducing the parasitic capacitances Cgd and Cdb between the gate and the drain and between the drain and the back gate, the phase delay of the output terminal 26 of the cascode amplifier circuit 20 can be reduced, and the frequency band of the cascode amplifier circuit 20 can be increased. can do. Furthermore, even if the resistance of the load element that pulls up the output terminal 26 is increased,
An amplifier circuit having a small phase delay at the output terminal 26, high gain, and low power consumption can be provided.

In the above embodiment, at the input terminal 22, the parasitic capacitance Cbe between the base and the emitter and the parasitic capacitance Cbc between the base and the collector exist, and the mutual conductance gm of the n-channel field effect transistor 29
Is small and the current amplification factor of the bipolar transistor 24 is larger than 1, the parasitic capacitance C between the base and the collector
Since bc functions as a mirror capacitance, the phase delay between the base and the collector increases. In order to reduce the phase delay between the base and the collector, an additional bipolar transistor 32 can be connected to the base side of the bipolar transistor 24 and driven by an emitter follower as in the cascode amplifier circuit 30 of FIG. . That is,
An additional bipolar transistor 32 connects the input terminal 22 to the base, connects the collector to the power supply 34, and connects the emitter to the base of the bipolar transistor 24 and the constant current source 36, thereby forming the bipolar transistor 24.
Can reduce the value of the equivalent resistance on the input side, and the phase delay between the base and the collector can be reduced. In the present embodiment, it is needless to say that the constant current source 36 can use an element that forms a current path such as a DC resistance or a MOS transistor.

FIG. 4 is a block diagram of a cascode amplifier circuit 38 according to another embodiment of the present invention. In the figure,
The cascode amplifying circuit 38 includes a common emitter bipolar transistor 24 having a base connected to the input terminal 22.
A cascode connection with the bipolar transistor 24, a source connected to the collector of the bipolar transistor 24, a drain connected to the output terminal 26, and a gate connected to the bias power supply 28. A transistor 29 is provided, and a constant current source 42 can be connected between a connection point 40 between the bipolar transistor 24 and the field effect transistor 29 and a reference voltage source. The constant current source 42 biases the bipolar transistor 24 and the field effect transistor 29, and can drive a large current according to the amplitude of the input voltage applied from the input terminal 22. Note that in this embodiment and the above-described embodiments, the back gate of the field-effect transistor applies a voltage lower than the source and drain voltages of the n-channel MOS transistor and the source and drain of the p-channel MOS transistor. It suffices to apply a voltage higher than the drain voltage, and it goes without saying that a voltage raised or lowered by the pump means can be used in addition to the power supply voltage or the reference voltage. When a metal oxide semiconductor (MOS) field-effect transistor is used as the cascode-connected field-effect transistor 29, the parasitic capacitance Cgs and Csb on the source side are equivalent to the equivalent capacitance Cπ = (Cb + Cbe) on the emitter side of the bipolar transistor. ), The operation speed on the source side can be increased. That is, since the apparent base storage capacitance Cb exists between the base and the emitter of the conventional cascode-connected bipolar transistor due to the delay of the base traveling time of the carrier, for example, 10 to 20 pF, which is 100 times larger than the MOS transistor. From 1
A phase delay due to a 000-fold capacitance occurs, and these phase delays can be significantly reduced only by replacing a bipolar transistor with a MOS transistor.

FIG. 5 is a block diagram of the comparator circuit 44 according to the embodiment of the present invention. In the figure, a comparator circuit 44 includes a bipolar transistor 52 receiving an input voltage −Vi from an input terminal 22 and a bipolar transistor 5 receiving an input voltage + Vi from an input terminal 56.
4. A constant current source 58 connected between the emitter of the bipolar transistor 54 and the negative power supply -V, a constant current source 60 connected between the emitter of the bipolar transistor 52 and the negative power supply -V, a base Is connected to the junction between the emitter of the bipolar transistor 54 and the constant current source 58, and the differential amplification stage 49 is paired with the bipolar transistor 46 and connected to the negative power supply -V through the constant current source 48. A bipolar transistor 24 having a base connected to the contact point between the emitter of the bipolar transistor 52 and the constant current source 60, cascode-connected to the bipolar transistor 24,
A field effect transistor 29 whose source is connected to the collector of the cascode-connected bipolar transistor 24, whose drain is connected to the output terminal 26, and whose gate is connected to the bias power supply 28, is applied to the input terminals 22 and 56. The current flowing through the load element 50 connected to the output terminal 26 can be controlled according to the voltage difference between the +/− input voltage Vi. Bipolar transistor 62 of an emitter follower having a gate connected to output terminal 26
Can control the output voltage of the output terminal 63 connected to the emitter in response to a change in the current of the load element 50, and can increase the current driving force because the output impedance is small. That is, in the differential amplifier stage 49, the output current corresponding to the amplitude of the input voltage Vi
2 can be driven to change the voltage of the output terminal 63 extending from the connection point between the emitter of the bipolar transistor 62 and the constant current source 64 connected between the negative power supply -V. In the present embodiment, the bipolar transistors 24 and 46 have a voltage Vbe between the base and the emitter.
Is small, the compatibility is good, the stability of the differential amplifier stage 49 can be improved, and the accuracy can be improved. Therefore, it is possible to provide the low-drift differential amplifier stage 49 with a low offset voltage at the input. In this embodiment, a comparator circuit having a BiCMOS structure can be used.

FIG. 6 is a block diagram of a comparator circuit 70 according to another embodiment of the present invention. In the figure,
The comparator circuit 70 includes differential amplification stages 85 and 117, and can amplify an input signal into two stages to improve the gain and widen the signal amplitude to guarantee a CMOS level of 0 V to 5 V.

The first differential amplifier stage 85 of the comparator circuit 70 includes two emitters connected between the input terminals 72 and 74 and the power supply + V and the reference voltage source GND via load elements 80 and 82. An input stage including follower bipolar transistors 76 and 78, a pair of bipolar transistors 84 and 86 connecting the bases to the emitters of the bipolar transistors 76 and 78, and a constant current source connected to the emitters of the bipolar transistors 84 and 86. Two n-channel field-effect devices are connected in common to a reference voltage source GND via 88, and connected to a power supply + V via load elements 96 and 98, respectively, and cascode-connected to the bipolar transistors 84 and 86. A bias power supply 94 is connected to the gates of the Le-type field-effect transistor 9
0, 92 and output elements extending between the load elements 96, 98. The bipolar transistors 76, 78 of emitter followers connected to the input terminals 72, 74 can reduce the equivalent resistance on the input side. The influence of the capacitance between the base and the collector of the type transistors 84 and 86 can be minimized. The operating frequency of the first differential amplifier stage 85 can be extended to a higher frequency side by the cascode-connected n-channel type field effect transistors 90 and 92.

Further, the second differential amplifier stage 117 of the comparator circuit 70 receives the output of the first differential amplifier stage 85 and connects the load element 10 between the power supply + V and the reference voltage source GND.
4, an input stage including two emitter-follower bipolar transistors 100 and 102 connected via a pair 106, a pair of bipolar transistors 116 and 118 connecting the bases to the emitters of the bipolar transistors 100 and 102, respectively. The emitters of the bipolar transistors 116 and 118 are commonly connected to a reference voltage source GND via a constant current source 120, and the load elements 112 and 1 each having a collector formed by a MOS transistor.
14 are connected to a power supply + V, and two p-type transistors cascode-connected to the bipolar transistors 116 and 118.
Channel type field effect transistors 122 and 124
A bias power supply 126 is connected to the gate of the n-channel type MOS transistor connected between the p-channel type field effect transistors 122 and 124 and the reference voltage source GND.
Load elements 128 and 130 composed of S transistors, and an output terminal 132 extending between one of the load elements 130 and the cascode-connected field effect transistor 124
And a p-channel field-effect transistor 110 connected in series between a power supply + V and a reference voltage source GND.
And the reference voltage divided by the constant current source 108
By applying a voltage to the gates of the transistors 2 and 114, a constant current equivalent to that of the field-effect transistor 110 can be supplied to the bipolar transistors 116 and 118.
In addition, the n-channel field-effect transistor connected between the cascode-connected p-channel field-effect transistor 124 and the reference voltage source GND can operate as the load element 130 of the differential amplifier 117. . Further, the differential amplifier stages 85 and 117 output a voltage 5V or 0V corresponding to logic "1" or "0" by comparing the voltage between the + and-terminals of the input voltage Vi applied to the input terminals 72 and 74. The signal can be output to the terminal 132.

In the above embodiment, the output voltage of the CMOS level is obtained from 0 V to 5 V. However, a level conversion circuit of 0 V to 3 V can be added in addition to the CMOS level depending on the result of comparison of the input voltage. . Further, the composite cascode amplifier circuit using the BiCMOS technology is applied to a comparator circuit operating at high speed. However, this cascode amplifier circuit can be applied to a high-frequency amplifier circuit, a high-speed pulse circuit, and a high-speed logic operation circuit. is there. Further, since a bipolar transistor having a higher mutual conductance gm and a stable offset voltage and drift voltage than the MOSFET is arranged on the input side, the amplifier circuit can maintain accurate and stable characteristics.

Although the embodiment of the present invention has been described using a MOS field effect transistor (FET),
A junction type FET can be used instead of the S type FET. Other field-effect transistors,
Similar effects can be obtained by using a high-speed and small parasitic capacitance field-effect transistor such as a MESFET, an electrostatic induction transistor (SIT), a vertical V-MOSFET, and a horizontal SOI-MOSFET. In addition to the technique of forming the bipolar transistor forming region and the MOSFET forming region separately, a composite element manufacturing technique in which a MOSFET is incorporated in a diffusion island region for forming a bipolar transistor can also be used. Furthermore, BiCMOS
Since the NPN transistor and the n-channel type MOSFET that constitute the composite cascode amplifier circuit having the structure can be formed in the diffusion region that separates the NPN transistor, a highly integrated semiconductor integrated circuit can be provided, and the chip occupation area can be provided. Can be reduced.

[0024]

As described above, according to the cascode amplifier circuit of the present invention, the influence of the parasitic capacitance existing in the collector region of the bipolar transistor can be minimized, and the amplifier circuit has low power consumption. Operating frequency can be increased.

Further, according to the comparator circuit constituted by the cascode amplifier circuit, high-speed comparison operation can be performed with low power consumption while maintaining the comparison accuracy of the comparator circuit.

Further, if a MOSFET is formed in the element isolation region of a bipolar transistor, a comparator circuit with a small chip occupation area can be expected, and the yield of semiconductor integrated circuits can be drastically improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a cascode amplifier circuit according to an embodiment.

FIG. 2 is a circuit diagram showing a parasitic capacitance of a MOSFET.

FIG. 3 is a circuit diagram of a cascode amplifier circuit according to the embodiment;

FIG. 4 is a circuit diagram of a cascode amplifier circuit according to the embodiment;

FIG. 5 is a circuit diagram of a comparator circuit according to the embodiment.

FIG. 6 is a circuit diagram of a comparator circuit according to the embodiment.

FIG. 7 is a circuit diagram of a conventional output circuit.

[Explanation of symbols]

20, 30, 38 cascode amplifier circuit, 22, 56,
72, 74 input terminals, 24 bipolar transistors, 26 output terminals, 28 bias power supplies, 29 field-effect transistors, 44, 70 comparator circuits,
49, 85, 117 Differential amplification stage.

Claims (2)

[Claims] A base connected to an input terminal; a common-emitter bipolar transistor driven by an input voltage supplied to the base; cascode-connected to the bipolar transistor;
A cascode amplifier circuit comprising: a field-effect transistor having a source connected to a collector of a bipolar transistor, a drain connected to an output terminal, and a gate connected to a bias power supply. 2. A differential amplifier stage having an emitter connected in common to a reference voltage source via a constant current source, and a gate comprising a pair of bipolar transistors each having a gate connected to an input terminal; A field-effect transistor having a cascode connection to at least one of the transistors, a source connected to the collector of the bipolar transistor, a drain connected to the output terminal, and a gate connected to a bias power supply. Comparator circuit.