JPH10307558A - Digital signal transmission circuit and display with digital signal transmission circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce unnecessary radiation generated in a bus line to transmit digital signals therethrough and power consumption generated when its parasitic capacity is charged/discharged. SOLUTION: N-bit signals d(t) sent through a bus line (x) are encoded into m-bit signals e(t) and then serial-parallel converted to be sent out to a bus line (y) consisting of n-pieces signal lines (0<n<m). When the n-bit signals are transmitted at n m-clock, there is an allowance for a bandwidth, so that they can be limited only to a bit pattern with less unnecessary radiation and current consumption in use. At this time, the bandwidth is increased and so a clock frequency is increased but, nevertheless, the unnecessary radiation and current consumption can be held down, compared with the case that the n-bit signals are usually transmitted at n n-clock. As the bit pattern is redundant, errors in transmission are detected to find the signal lines to be malfunctioned in package.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention mainly relates to a digital signal transmission circuit having a sufficiently short transmission distance and a liquid crystal display (LCD) or a plasma display (PDP) for transmitting and displaying a digital video signal as the digital signal. And so on.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing a configuration of a liquid crystal display 71 of a general line sequential scanning system. In the figure, reference numeral 72 denotes a video signal source, which corresponds to a graphic controller for a notebook personal computer and a tuner for a liquid crystal television. 73 is a controller, 74 is a gate driver (row electrode drive circuit), 75 is a source driver (column electrode drive circuit), 76 is a liquid crystal display panel, and 77 is a liquid crystal cell (pixel; dot). VGA (Video Graph)
ics Array) resolution, 640 x 3 (RGB) x 480 = 1920 horizontal
X Consists of 480 vertical dots.

A video signal 78 and a synchronization signal 79 from a video signal source 72 are first input to a controller 73.
The controller 73 transmits the video signal 80 to the source driver 7
5 and the source signal 75 from the synchronization signal 79
And a function of generating a control signal 81 for controlling the gate driver 74. The gate driver 74 selects a row electrode to be scanned next. Source driver 7
5 simultaneously outputs one horizontal cycle of the video signal 80 fetched from the controller 73 to the group of liquid crystal cells 77 of the row electrode selected by the gate driver 74. For this reason,
The source driver 75 has a built-in serial-parallel conversion circuit. Thus, the driving state of the liquid crystal cell group for one row is updated at the same time.

[0004] Many high-resolution liquid crystal displays employ a system in which video signals are input as digital signals. This is to reduce the cost of the source driver and to prevent display noise due to jitter.

The source driver needs to sample and hold the video signal for the same time as one horizontal cycle. V
For a color liquid crystal display with GA resolution, 1920
× 2 sample and hold elements are required. When making many high-speed, high-accuracy, low-cost sample-and-hold devices, it is more advantageous to use latches and flip-flops than to use analog switches, capacitors, and operational amplifiers.

[0006] Unlike a CRT (cathode ray tube), a liquid crystal display has a clear image without a focus problem. For this reason, if the timing of the video signal and the timing of the synchronization signal deviate even slightly, the image quality is significantly deteriorated. However, in an analog circuit, it is difficult to accurately adjust signal timing. This is not a problem when displaying a natural image due to the nature of the image.
This is a big problem when displaying tables, graphs, etc.

[0007] Since the source driver of the digital video signal input system has a built-in DAC (digital-analog converter) or a circuit similar thereto, it is possible to output an analog video signal to the liquid crystal cell. it can.

FIG. 7 is a block diagram showing a configuration of the digital source driver 85. In the figure, 86 is an input terminal, 87 is a serial-parallel conversion circuit, 88 is a digital-analog converter, and 89 is an analog output terminal. For a color liquid crystal display with VGA resolution, 6
40 × 3 (RGB) = 1920 digital-to-analog converters are required.

Since a digital signal must be input to the digital source driver 85, the liquid crystal display itself is often designed to input a digital signal. This is because ADCs in the video band are expensive.

In a notebook personal computer, a video signal is transmitted as a digital signal from a video signal source 72 (FIG. 6), which is a graphic controller, to a controller 73 and from the controller 73 to a source driver 75.
For VGA, the frequency of the dot clock is 25 [MHz]
About. In the case of an 8-bit (256 gradation) × 3 (RGB) liquid crystal display, 24 video signal lines and several synchronization signal lines are required. Therefore, a large number of digital signal lines in the video band are routed in a very short distance.

However, since the notebook personal computer must be designed to be small and lightweight, it is more EMI (Electromagnetic Intenet) than a desktop personal computer.
Countermeasures for unnecessary radiation due to R.F. (electromagnetic interference) tend to be a problem. In addition, since the battery is driven by a battery, a measure for reducing current consumption is a major problem. In most notebook computers, the liquid crystal display also serves as a keyboard lid, so if the harness of the bus line is not made thin and flexible, opening and closing of the lid may be hindered.

In order to solve the problem of unnecessary radiation due to EMI (electromagnetic interference), various systems have been conventionally devised.

As a first conventional example, in a liquid crystal display having a higher resolution than VGA, the number of signal lines is increased,
There is a type that transmits video signals corresponding to a plurality of (usually 2 to 4) pixels (three RGB become one pixel) in parallel. As a result, the frequency of the clock can be significantly reduced, and EMI (electromagnetic interference) can be reduced. However, there is a problem that the harness becomes thicker, so there is a limit to this method.

As a second conventional example, a D-PCM (Dif
ferential PulseCode Modul
), Huffman code, or conversion of RGB signals into luminance and color difference signals. By compressing and transmitting the video signal, the number of signal lines can be reduced. However, in this case, the same video as the original cannot be transmitted due to information compression,
In some cases, the image quality deteriorates. If the number of signal lines is the same and the clock frequency is kept at the same level, it is necessary to increase the compression ratio, which leads to an increase in cost and power consumption.

[0015] As a third conventional example, Japanese Patent Laid-Open No. 7-1047 is disclosed.
As disclosed in Japanese Patent Application Laid-Open No. 15, the video signal is transmitted in a gray code (alternate binary) instead of a binary number. In a natural image, the frequency at which the luminance level of an image changes abruptly is low. Therefore, the gray code is advantageous in terms of EMI (electromagnetic interference) and power consumption. In this method, when an average image is displayed, EMI and power consumption are reduced. However, the maximum value of the power consumption does not decrease at all. Although this is effective for EMI measures and reduction of current consumption, it does not contribute to cost reduction of the power supply circuit at all.

As a fourth conventional example, there is one in which the frequency at which the level of a digital signal changes from High to Low or vice versa is suppressed low. In a digital signal transmission circuit, a large amount of power is consumed when the level of a signal placed on a bus line changes. When there is no change in the signal level, there is no need to charge the parasitic capacitance of the bus line or the input capacitance of the bus receiver, so that little power is consumed. This tendency is prominent in a buffer of a C-MOS (complementary metal oxide semiconductor) process.

A digital signal transmission circuit according to a fourth conventional example will be described with reference to FIG. In the figure, 90 is a digital signal transmission circuit, 91 is an encoder, 92 is a bus transmitter, 93 is a bus line, 94 is a bus receiver, 95 is a decoder, and 96 is a clock line. In this method, the number of signal lines increases, contrary to the information compression. Here, it is assumed that an n-bit signal is transmitted through m signal lines. n and m are integers satisfying 0 <n <m. The encoder 91 converts the n-bit digital signal into m-bits, and sends the converted signal to the bus line 93 from the bus transmitter 92. The encoder 91 monitors the frequency of change in the signal level by feeding back part of the output to the input. In other words, the mode depends on the signal one clock before. The encoder 91 can be configured by a look-up table (LUT) or wired logic (lay-out logic). Bus line 9
3 is transmitted to the bus receiver 94.
The m-bit signal received at (1) is restored by the decoder 95 to the original n-bit signal.

When the number of signal lines is increased from n to m, the bandwidth (capacity of the communication path) increases by m / n times.
It is possible to use only bit patterns with low (electromagnetic interference) and power consumption, and prohibit the use of bit patterns with many problems. For example, when a signal of n = 8 bits is transmitted through m = 10 signal lines, 2 ⁸ = 25 of 2 ¹⁰ = 1024 bit patterns are advantageous in terms of EMI and power consumption.
Only six bit patterns need be used. For this reason, EMI (electromagnetic interference) and power consumption can be reduced by properly designing the encoder. Of course, additional circuits (encoder, decoder, mn bus buffers)
However, if the parasitic capacitance of the bus line is large, the overall current consumption is reduced.

Since the code becomes redundant, the logic of the decoder has a so-called Don't Care term (φ). When n = 8 and m = 10, there are 1024 patterns that can be represented by 10 bits and 256 patterns that can be represented by 8 bits, and 768 bit patterns of the difference are included in the Don't Care term. Become. These 768 bit patterns are never used,
It is configured to be prohibited (ignored).

Here, a specific design example of the encoder will be described. Japanese Patent Application Laid-Open No. Hei 5-334206 is to appropriately switch the logic (positive logic and negative logic) of a signal so as to reduce the high frequency component in the signal waveform. In this scheme,
Since it is necessary to send the current signal logic to the bus receiver, it is necessary to increase the number of signal lines. In addition, since an enormous number of gates are required to realize the encoder,
It is realistic to design the encoder to function only when a bit pattern that significantly increases EMI (electromagnetic interference) or power consumption comes.

FIG. 9 shows a bus line x = (x ₀ , x ₁ , x ₂ ,..., X _n− ) composed of n signal lines in the digital signal transmission circuit according to the fourth conventional example (FIG. 8). ₁ ) n-bit signal d (t) = (d) transmitted to the encoder 91
_{0 (t), d 1 (} t), d 2 (t), ..., d n-1 (t))
Is an m-bit signal e (t) = (e ₀ (t), e ₁ (t),
e ₂ (t),..., em ₋₁ (t)), and a bus line y composed of m signal lines y = (y ₀ , y ₁ , y ₂ ,
, Y _m-1 ). Where n and m
Is a positive integer satisfying n <m. It should be noted that the number m of the bus lines y on the output side is larger than the number n of the bus lines x on the input side to the encoder. t is an integer representing time (clock). d
_i (t) and e _j (t) are information carried on one signal line in one clock, and in the case of a binary digital signal, High
Or Low. x _i and y _j are signal names assigned to the signal lines. i is an integer of 0 to n-1 and j is an integer of 0 to m-1.

In the digital signal transmission circuit according to the fourth conventional example, since the number of signal lines increases from n to m, the bus transmitter 92 and the bus receiver 94 are mechanically compatible with the video signal input connector. In addition, there is a problem that the harness becomes thick and it becomes difficult to bend.

Note that the same modulation technique is employed in both magnetic recording devices and magneto-optical recording devices. However, in a recording apparatus, this technique is mainly used to reduce the DC component of a signal.

In the case of a liquid crystal display for digitally inputting a video signal, there may be a problem in inspection of component mounting.

The digital source driver 85 shown in FIG.
Is an 8-bit (256 gradation) source driver. An input from the input terminal 86 is an 8-bit digital signal, and an output from the output terminal 89 is an 8-bit precision analog video signal.

Now, it is assumed that, of the eight digital signal lines, for example, only the signal line of the least significant bit does not operate normally due to a mounting defect.

At the time of component mounting inspection, the oscilloscope cannot first detect this defect. It is very difficult to find a defect of an 8-bit precision analog video signal using an oscilloscope.

It is also very difficult for a person in the inspection process to find a defect by looking at the display on the liquid crystal display. Human vision is very insensitive to blue. Therefore, it is difficult to find a display defect especially when noise is put on the least significant bit of the blue video signal. However, on the other hand, since the human sensory organs vary from person to person, it is quite possible that the user of the liquid crystal display will notice the abnormality even if the inspector cannot find the abnormality. However, it is impractical to select and hire particularly good inspectors.

In consideration of such circumstances, there is a problem that a product having a mounting defect is not caught in an inspection and there is no possibility that it will flow out to the market as a non-defective product.

[0030]

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital signal transmission circuit capable of reducing unnecessary radiation and current consumption due to EMI (electromagnetic interference) without increasing the number of signal lines. I have. Another object of the present invention is to reliably detect a mounting failure of a signal line constituting a bus line in a manufacturing process of a display including a digital signal transmission circuit for inputting a digital video signal.

[0031]

In the digital signal transmission circuit according to the present invention, when n and m are integers satisfying 0 <n <m, n pieces of m-bit data are used by using m signal lines. Instead of transmitting at n clocks, n data of m bits are transmitted at m clocks using n signal lines. One piece of n-bit data is encoded into serial m bits, and then n pieces of data are simultaneously transmitted in parallel. At this time, each data is serially transmitted using one signal line. When the present invention is compared with the fourth conventional example, the number of signal lines is reduced to n / m times, but the same bandwidth is secured because the clock frequency is increased to m / n times. . That is, by increasing the frequency of the clock, a predetermined bandwidth can be secured without increasing the number of signal lines.
This eliminates the need for using a bit pattern that adversely affects unnecessary radiation and current consumption due to (electromagnetic interference), and can solve the problem of unnecessary radiation and current consumption.

The display according to the present invention inputs a video signal to a source driver in a bit pattern in which an error can be detected. The source driver has a function of outputting a prohibited bit pattern to the outside when it is found. Since the video signal is input to the source driver in a redundant bit pattern in which an error can be detected, the source driver can notify the inspection staff that an error has occurred.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of a digital signal transmission circuit according to the present invention will be described in detail with reference to the drawings.

[First Embodiment] FIG. 1 is a block diagram showing a configuration of a digital signal transmission circuit 10 according to a first embodiment of the present invention. In FIG. 1, 11 is an encoder, 1
2 is a parallel-serial converter, 13 is a bus transmitter, 14 is a bus line, 15 is a bus receiver, 16 is a serial-parallel converter, 17 is a decoder, 18 is a clock line, and 19 and 20 are PLLs (Phase (Phase)).
Locked Loop) circuit. Encoder 11
Is a bus line x = (x ₀ , x ₁ , x ₂ ,..., X _{n -1} ) composed of n signal lines as shown in FIGS.
N-bit signal d (t) sent by
= (D ₀ (t), d ₁ (t), d ₂ (t),..., D
_n-1 (t)) to FIG. 9 in the same manner as in parallel m-bit bit pattern data _{P (t) = (e 0} (t), e 1 (t),
e ₂ (t),..., em _-1 (t)) and output to the parallel-serial converter 12. The PLL circuit 19 converts the clock (1) input from the clock line 18 into a clock (2) having a frequency of m / n times.
And outputs it to the parallel-serial converter 12 as a timing signal. The parallel-serial converter 12 converts the input parallel m-bit bit pattern data P (t) similar to FIG. 9 into m-bit bit pattern data serialized per signal line, for example, as shown in FIG.
And serial m-bit bit pattern data e (t) = (e ₀ ) as shown by the two-dot chain line 100 in FIG.
(T), e ₁ (t), e ₂ (t),..., Em ₋₁ (t)), while increasing the frequency by m / n.
The information e _j (t) enclosed by a two-dot chain line 200 composed of parallel n-bit signal groups having different input timings by changing the order of input and output based on (2).
_q ), a bus line y = (y
₀ , y ₁ , y ₂ ,..., Y _n-1 ). The bus transmitter 13 is configured to transmit and output information e _j (t _q ) consisting of a parallel n-bit signal group having different input timings to the bus line 14. The bus receiver 15 is configured to receive information e _j (t _q ) composed of a parallel n-bit signal group having different input timings input from the bus line 14 and output the information e _j (t _q ) to the serial-parallel converter 16. I have. The PLL circuit 20 is connected to the clock line 18.
Clock (1) input from
ock (2) and convert it to serial-parallel converter 16
Is output as a timing signal. The serial-parallel converter 16 outputs information e _j (t _q) consisting of a parallel n-bit signal group having different input timings.
)), The frequency of the m-bit bit pattern data serial m per signal line, for example, the serial m-bit bit pattern data P (t) surrounded by the two-dot chain line 100 is increased to m / n times. Clock
While changing the order of input and output based on (2),
The same m-bit bit pattern data P (t) = (e ₀ (t), e ₁ (t), e ₂ (t),
, E _m-1 (t)) and output to the decoder 17. The decoder 17 converts the m-bit bit pattern data P (t) into the original parallel n-bit signal d (t) = (d ₀ (t), d ₁ (t), d
₂ (t),..., D _n-1 (t)).

Although FIG. 2 and FIG. 3 are originally one timing chart, they are separately described for convenience of size. The time points a and b in FIG. 2 correspond to the time points a 'and b' in FIG. The end part of FIG. 2 and the start part of FIG. 3 are overlapped.

It is clear from FIGS. 2 and 3 that the frequency of clock (2) is higher than the frequency of clock (1) (m / n times). In addition, the encoder 11 and the parallel-serial converter 12 use a parallel n-bit signal at the same time, for example, a signal d (t) = (d
₀ (t), d ₁ (t), d ₂ (t),..., D _n-1 (t)) are time-series, ie, serial m-bit pattern Data e (t) =
(E ₀ (t), e ₁ (t), e ₂ (t),..., E
It is also apparent that it has been converted to _m-1 (t)).

Although two PLL circuits are used in FIG. 1, since both output the same clock,
You may put them together. In this case, the power consumed by the clock line increases, but the number of components decreases. Also,
Instead of using a PLL circuit, two types of clocks may be created by using a high-frequency oscillator, a circuit that divides the output of the oscillator by 1 / n, and a circuit that divides the output by 1 / m.

By the way, the information to be transmitted is changed from n bits to m.
When the number of bits is increased (n <m), the bandwidth (capacity of the communication path) is insufficient by mn bits. In the fourth conventional example, the number of signal lines is increased from n to m, and transmission is performed in parallel, thereby compensating for the shortage of the bandwidth. On the other hand, in the embodiment of the present invention, the number of clocks is increased from n clocks (for example, 8 clocks) to m clocks (for example, 10 clocks) without increasing the number of signal lines, and instead of transmitting in parallel. In order to compensate for the lack of bandwidth by transmitting serially.

In the digital signal transmission circuit according to the first embodiment, EMI can be performed without increasing the number of signal lines.
(Electromagnetic interference) and current consumption can be reduced.

In the fourth conventional example, as shown in FIG.
It was necessary to monitor the frequency of signal level changes by feeding back part of the output of the encoder 91 to the input. However, in the first embodiment, such a feedback loop is not always necessary for the encoder 11. Absent. In the case of the first embodiment, since the current output signal can be obtained without depending on the output signal one clock before,
Circuit design becomes easier.

Next, the effect of reducing the current consumption of the digital signal transmission circuit according to the first embodiment will be described.
I will try to find it quantitatively. Calculate current consumption per signal line. When n bits of information are serially transmitted at n clocks using one signal line, 2 ⁿ types of bit patterns can be used. During transmission of this information, the signal level is k
There are N (k) = 2 × _n C _k bit patterns that change twice. Here, k is an integer that satisfies 0 ≦ k ≦ n−1, and _n C _k is the number of combinations for extracting k samples from n samples.

Now, it is assumed that n = 8 and m = 10. 2
Assuming that the occurrence probabilities of ⁸ = 256 bit patterns are all equal, the probability that the signal level changes k times is
Pr (k) = N (k) / 256. Signal level is l
Assuming that a current of a certain unit l is consumed every time it changes, the expected value of the consumed current is k × Pr (k), 0 ≦ k ≦
7 is the sum.

Table 1 shows the calculation results when n = 8 bits of information are transmitted serially at eight clocks. This is a comparative example with respect to the first embodiment. H (k) in the table is
It is a histogram of N (k). From this table, it can be seen that this transmission scheme consumes an average of 3.5 currents due to changes in signal level. Actually, after transmitting 8 bits of information in the first 8 clocks, 8 bits of information are transmitted in the next 8 clocks.
Since the signal level changes with a probability of 0.5 before transmitting the bit information, the current consumption per 8 clocks is 3.5 + 0.5 = 4.0.

[0044]

[Table 1]

Similarly, Table 2 shows the calculation results of the current consumption when the information of m = 10 bits is transmitted at 10 clocks. This is also a comparative example with respect to the first embodiment. In this case, 1
An average of 4.5 (+ 0.5 = 5.0) current is consumed per 0 clock.

[0046]

[Table 2]

In the case of the first embodiment, that is, the current consumption when n = 8-bit information is transmitted using m = 10 clocks will be estimated. In Embodiment 1, 10
Of the 24 bit patterns, only 256 patterns with little change in signal level are used. Therefore, it is not necessary to use a bit pattern whose signal level changes four or more times. This corresponds to a “bit pattern with a small amount of high-frequency components and a small amount of unnecessary radiation or current consumption”.
At this time, it can be seen from Table 3 that the average current consumption per 10 clocks is 2.555 (+ 0.5 = 3.055). It can be seen that the current consumption is reduced although the number of clocks required for information transmission is increased by 2 clocks.

[0048]

[Table 3]

In general, 8-bit information is transferred by c clocks (c
Table 8 shows the expected value e of the current consumption due to the change in the signal level when the transmission is performed by using an integer of 8 or more. Even if it is assumed that the information to be transmitted is white (no correlation) and follows a uniform distribution, this effect can be expected. The higher the clock frequency, the lower the current consumption.

[0050]

[Table 4]

In Table 4, the case where c = 8 and the case where c =
The case of 10 corresponds to Tables 1 and 3 respectively (3.5 + 0.5 = 4.0, 2.555 + 0.5 = 3.
055).

Actually, an encoder, a decoder, a PLL
It is necessary to subtract the power consumed by the circuit. But,
If the signal lines are long and the number thereof is large, the parasitic capacitance of the bus line is large. Therefore, even after subtracting the power newly generated in the added circuit, the effect of reducing the current consumption according to the first embodiment can be expected.

When the number of clocks c is extremely large or the number of signal lines n of the bus line 14 is extremely small, the current consumption due to charging and discharging of the clock line 18 cannot be ignored. In this case, it is necessary to take measures such as dividing the clock on the bus transmitter 13 side and transmitting the divided clock, and using the bus receiver 15 by multiplying the clock.

The effect on EMI (electromagnetic interference) is difficult to discuss quantitatively, but can be expected to be reduced.

Next, application examples of the first embodiment will be described for each application.

A liquid crystal television will be described as a first application example.
When a demodulated signal of an analog TV broadcast is displayed on a liquid crystal display, the frequency of a sampling clock of an ADC (analog-digital converter) is different from the frequency of a clock for transmitting a digital video signal to the liquid crystal display. It is necessary to convert the clock frequency.

In a liquid crystal display, vertical and horizontal blanking periods are not required in principle. However, at present, a wait time corresponding to a retrace period is often inserted in consideration of compatibility with a CRT. If this waiting time is used for transmitting a video signal, it is not necessary to greatly increase the clock frequency as compared with the conventional case.

A notebook personal computer will be described as a second application example. Notebook PCs use a digital source driver DAC (digital-
By applying the transmission method of the present embodiment to all the bus lines up to the analog converter, a single clock operation becomes possible, and an additional circuit such as a PLL circuit becomes unnecessary.

[Second Embodiment] The second embodiment relates to a color liquid crystal display 31 provided with the digital signal transmission circuit configured as described above.

FIG. 4 is a block diagram showing a configuration of a color liquid crystal display 31 of the line sequential scanning system according to the second embodiment. In the figure, reference numeral 32 denotes a video signal source, which corresponds to a graphic controller for a notebook personal computer and a tuner for a liquid crystal television. 33a, 33b, 33c are RG
B, a digital signal transmission circuit having the same configuration as that of FIG. 1, 34 is a controller, 35 is a gate driver (row electrode drive circuit), 36 is a digital source driver (column electrode drive circuit), 37 is a liquid crystal display panel, Reference numeral 38 denotes a liquid crystal cell (pixel; dot). VGA (Video
A color liquid crystal display with a resolution of Graphics Array) is 640 × 3 (RGB) × 480 vertically.
= 1920 horizontal × 480 vertical dots.

The video signal 39 and the synchronization signal 40 from the video signal source 32 are supplied to the digital signal transmission circuits 33a, 33
3b and 33c, and the synchronization signal 40 is input to the controller 34. In each of the digital signal transmission circuits 33a, 33b, and 33c, the same processing as that described in the first embodiment is performed, and the processed video signal 41 is output to the controller. The controller 34 converts the processed video signal 42 into a digital source driver 36
And a function of generating a control signal 43 for controlling the digital source driver 36 and the gate driver 35 from the synchronization signal 40. Gate driver 35
Is to select a row electrode to be scanned next. The digital source driver 36 applies the controller 3 to the group of liquid crystal cells 38 of the row electrodes selected by the gate driver 35.
4 are output simultaneously for one horizontal period of the video signal 42 captured. The digital source driver 36 has a built-in serial-parallel conversion circuit as described later. Thus, the driving state of the liquid crystal cell group for one row is updated at the same time.

FIG. 5 is a block diagram showing the internal configuration of the digital source driver 36 in FIG. In the figure, 52 is an input terminal, 53 is a decoder for converting an m-bit digital signal into an n-bit signal, 54 is a serial-parallel conversion circuit for converting an n-bit signal input from the decoder 53 into a parallel signal, 55 Is a digital-analog converter (DAC) for converting each digital signal output from the serial-parallel conversion circuit 54 into an analog video signal with n-bit accuracy, and 56 is a converted n
Output terminal for outputting bit-accurate analog video signal, 5
An error signal output line 7 outputs an error signal when an error occurs in decoding in the decoder 53. For a color liquid crystal display with VGA resolution, 6
40 × 3 (RGB) = 1920 digital-to-analog converters 55 are required. In the case of VGA, the frequency of the dot clock is about 25 [MHz]. 8 bits (2
In the case of a liquid crystal display of (56 gradations) × 3 (RGB), 24 video signal lines and several synchronization signal lines are required. Therefore, a large number of digital signal lines in the video band are routed in a very short distance.

The digital source driver 36 receives a video signal encoded from an n-bit video signal into an m-bit signal from an input terminal 52 in the preceding stage. Here, n and m are integers satisfying 0 <n <m. Therefore, the input signal is redundant by mn bits.

In this digital source driver 36, a parallel m-bit digital video signal is input from an input terminal 52, and is converted from m-bit to n-bit by a decoder 53. Is converted into a parallel signal, converted into an analog video signal with n-bit accuracy by a digital-analog converter 55, and output from an output terminal 56 to the column electrode group of the liquid crystal display panel 37 in FIG.

Assuming that n = 8 and m = 10, 2
^{10-2 8} = bit pattern of types 768 are normally not used. Conventionally, the 768 kinds of bit patterns are Do
n't Care term was completely ignored. In the second embodiment, the Don't Care term is defined as a prohibited bit pattern. Prohibits the use of EMI (electromagnetic interference) and bit patterns that consume a large amount of current,
The bit pattern is used for error detection. Decoder 53
Finds this forbidden bit pattern,
An error signal is output from the error signal output line 57 to the outside. If the implementation of any of the plurality of digital signal lines is good, the prohibited bit pattern is not input to the decoder 53.
However, if any one or more signal lines have a mounting defect, a prohibited bit pattern is input, and an error signal is output from the error signal output line 57 in the decoder 53. By issuing a warning based on the output error signal, a mounting defect can be easily found.

At this time, the decoder 53 does not necessarily
It is not necessary to have the ability to find all 68 bit patterns. It may be designed so that at least only the least significant bit error can be found. As a result, costs can be reduced. When the decoder 53 is placed between the input terminal 52 of the digital source driver 36 and the serial-parallel conversion circuit 54 as shown in FIG. 5, the same number of decoders as the digital-analog converter 55 are prepared. You don't have to. This also leads to cost reduction.

Further, when the decoder 53 finds a prohibited bit pattern, for example, the level of the analog video signal output terminal 56 is set to negative (complementary color) or the screen is flashed (blinks). By doing so, if an error is notified to the inspection personnel, the terminal of the error signal output line 57 becomes unnecessary, and the number of pins of the digital source driver 36 can be reduced by one. Conversely, when an error is found, there is a method of correcting the error so that an incorrect signal is not output from the analog video signal output terminal 56 to make it unsightly. For example, the video signal at the location where the error was found may be replaced with the video signal one clock before.

In the liquid crystal display according to the second embodiment, it is possible to prevent a defective product, which is likely to be overlooked by a visual inspection at a mass production site, from leaking to the market as it is.

The technique of the second embodiment may be applied to a plasma display or a display video.

[0070]

According to the digital signal transmission circuit of the present invention, a predetermined bandwidth can be secured without increasing the number of signal lines, and unnecessary radiation and current consumption due to EMI (electromagnetic interference) are adversely affected. It is not necessary to use a given bit pattern, and the problems of unnecessary radiation and current consumption can be solved.

Further, according to the display of the present invention, since the video signal is input to the source driver in a redundant bit pattern capable of detecting an error, the occurrence of an error in the source driver is detected and an alarm is issued. Can be detected very easily, and it is possible to prevent a defective product from leaking to the market as it is.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a digital signal transmission circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the digital signal transmission circuit according to the first embodiment (continued from FIG. 3);

FIG. 3 is a timing chart for explaining the operation of the digital signal transmission circuit according to the first embodiment (continued from FIG. 2);

FIG. 4 is a block diagram showing a configuration of a color liquid crystal display according to Embodiment 2 of the present invention.

FIG. 5 is a block diagram showing an internal configuration of a digital source driver in FIG. 4;

FIG. 6 is a block diagram showing a configuration of a conventional general liquid crystal display.

FIG. 7 is a block diagram showing an internal configuration of a digital source driver in FIG. 6;

FIG. 8 is a block diagram showing a configuration of a digital signal transmission circuit according to a fourth conventional example.

FIG. 9 is a timing chart for explaining the operation of a digital signal transmission circuit according to a fourth conventional example.

[Description of Signs] 10 ... Digital signal transmission circuit 11 ... Encoder 12 ... Parallel-serial converter 13 ... Bus transmitter 14 ... Bus line 15 ... Bus receiver 16 ... Serial-parallel converter 17 ... Decoder 18 Clock line 19, 20 PLL circuit x Bus line composed of n signal lines y Bus line composed of n signal lines d (t) = (d ₀ (t), d ₁ (t), d ₂ (t), ...,
d _n-1 (t))... parallel n-bit bit pattern data on the bus line x e (t) = (e ₀ (t), e ₁ (t), e ₂ (t),. ,
_{e m-1 (t))} ...... bus line y in riding serial m-bit bit pattern data e _j (t _q) serial riding on each one ...... signal line m-bit bit pattern data , Information as a set of n signal lines having different input timings 31... Liquid crystal displays 33 a, 33 b, 33 c... Digital signal transmission circuit 35... Gate driver 36... Digital source driver 37. Panel 53 Decoder 54 Serial-parallel converter 55 Digital-analog converter

Claims (4)

[Claims] A digital signal transmission circuit comprising a bus line for transmitting a digital signal, a bus transmitter for putting a signal on the bus line, and a bus receiver for receiving a signal from the bus line, wherein a clock frequency of the digital signal is A digital signal transmission characterized by securing a bandwidth larger than the amount of information to be transmitted by raising, and selectively transmitting a digital signal using only a bit pattern having a small amount of high frequency components and unnecessary radiation and a small current consumption. circuit. 2. n and m are integers satisfying 0 <n <m, and the n-bit signal is transmitted to a bus line that transmits n-bit signals in parallel using n signal lines.
2. The bus line according to claim 1, wherein the bus line is replaced with an m-bit bit pattern that reduces unnecessary radiation and current consumption, and converts the n-bit data of n bits into serial transmission with m clocks using n signal lines. A digital signal transmission circuit which takes an interface between two types of bus lines by passing the signal to a bus transmitter. 3. A display comprising a source driver having a terminal for digitally inputting a video signal,
A display, wherein a bit pattern to be prohibited exists in the digital video signal, and the source driver has a function of detecting the prohibited bit pattern. 4. The display according to claim 3, wherein the bit pattern to be prohibited is set to a bit pattern that has a more adverse effect on unnecessary radiation and current consumption than other bit patterns. .