JPH10304294A - Digital magnetic recording and reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize synchronization of an inside reference signal and a color frame phase with an existing circuit by advancing or delaying the phase of a control signal in a state where the lock of a rotary head is held at the time of reproduction, and delaying a reproduced compressed digital signal by first and second ECC(error correction) decoders. SOLUTION: The phase of a control signal CTL' is advanced by 413 fields, and digital reproduction signals PBc and PBd are delayed by 213 fields each by using buffer memories 4 and 8 provided in an inner code correction decoder 125 and an outer code correction decoder 136, and the color frame phase of a finally outputted digital reproduction signal is made coincident with the color frame phase of an inside reference signal. Thus, this processing can be attained without changing the rotational phase of a rotary drum at the time of recording and at the time of reproduction, and a signal can be delayed by using an existing memory without increasing the number of hardware.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital magnetic recording / reproducing apparatus suitable for application to a digital video tape recorder (VTR) and the like. More specifically, the rotational phase of the rotary drum is advanced or delayed by a predetermined field, and the read digital reproduction signal is delayed by a predetermined time by an error correction decoder so that the locked state of the rotary drum is not released. A digital reproduction signal is obtained with the color frame phase locked to the color frame phase of the internal reference signal.

[0002]

2. Description of the Related Art In a magnetic recording / reproducing apparatus such as a digital VTR, for example, a handy type digital VTR,
Based on the internally generated internal reference signal (color framing internal reference signal), a servo signal for the rotating drum, a field frequency control signal (CTL) to be recorded on the tape, and the like are generated. A digital signal (such as a digital video signal or a digital audio signal) is recorded based on the internal reference signal, and a digital reproduction signal is processed based on the internal reference signal.

A case where the present invention is applied to a VTR using a rotating drum having a plurality of magnetic heads as shown in FIG. 6 will be described below. The recording heads Ra to Rh are attached to the rotary drum 20 shown in FIG.
To Ph are attached. In the recording mode, the reproducing heads Pa to Ph are check heads (Con) for simultaneous recording and reproducing.
fi head) in some cases. FIG. 7 shows an example of a tape format when these magnetic heads R and P are used.

FIG. 1 shows an example of a format of a component recording digital video tape recorder, in which four channels of audio data A1 to A4 are recorded between video data V1 and V2. SAT is a servo reference signal, Tca is a cue track for analog audio signals, and TC is a time code track. Ttc is the control signal CT
This is an L track.

Since one field is composed of three segments and one segment is composed of two tracks, one frame is composed of six segments and twelve tracks. Therefore, the relationship between the internal reference signal REF and the segment is as shown in FIG. In this example, when a digital signal is recorded, a case where error correction using an inner code and error correction using an outer code are used together is shown. The video signal to be recorded is an NTSC video signal.

In the case of an NTSC video signal, FIG.
The internal reference signal REF has a signal form of a four-field sequence (color phase unit) in relation to color framing (color frame phase). FIG. 6B shows a signal SC for video servo, and the control signal CTL shown in FIG. C has different pulse duties depending on the fields so that a color frame is completed in four fields. In the figure, the pulse duty is 65
%, 50%, 50%, 50%.

[0007] Further, since five fields are completed between the audio data and the sampling frequency (44.1 KHz) of the audio data and the field frequency (59.94 Hz), the duty of the servo signal is changed every five fields. doing. In the figure, the duty is 35% every five fields.

The internal reference signal REF and the control signal C
The input video signal Din is shifted relative to the TL by the time ta, and in this example, the input video signal Din is delayed by tb with respect to the internal reference signal REF as shown in FIG.

The input video signal Din has a delay of tc (D in the figure) due to digital conversion processing, processing for adding an error correction code (ECC parity code), and the like. If the input digital signal is recorded with a delay of tc, the internal reference signal REF and the field phase do not match at all, so that the actual recording of the signal starts.
This is further delayed by td in synchronization with the internal reference signal REF (E and F in FIG. 4).

An input digital signal of one field and three segments is divided into four heads Ra to Rd (Re to Rd).
h), the data is recorded alternately and sequentially, so that one segment of data is recorded over approximately ２ field time. Therefore, the recording time axis is twice as long as one segment as shown in FIG.

When recording is performed by four heads, the recording timing has a slight time difference between the respective heads. However, FIG. 8 omits this and shows that recording is performed at the same timing. .

FIG. 8G and subsequent figures show timing charts in the confirmation reproduction mode at the time of recording. Since the reproducing head P is shifted by 90 ° with respect to the recording head R, the reproduction is performed with a delay of te (G in the figure).

When the reproduction signal PBa is input to the reproduction processing circuit system, a time series similar to that at the time of the input is obtained (H in FIG. 9). An ECC using an inner code is applied to the reproduced signal PBb.
Correction processing is performed (I in the figure), and the corrected reproduction signal PBc is further subjected to ECC correction processing using an outer code (J in the figure), so that the signal delays tf and tg due to the correction processing time are respectively reduced. Occurs.

When the error correction processing by the inner code and the outer code is completed, the decoding and decompression processing of the digital video signal is performed, and this processing is performed on a field basis. Therefore, the error-corrected digital video signal PB
The digital reproduction signal PBo decompressed for d is output just one field later (K in the figure).

Here, in order to output the digital reproduction signal PBo output with a delay of one field in synchronization with the internal reference signal REF, the timing read from the ECC encoder is adjusted. In the example of the figure, the digital reproduction signal PBo synchronized with the internal reference signal REF can be output by taking the delays tf and tg for 1.5 segments, respectively. Therefore, the finally obtained reproduced signal PBo is outputted with a delay of 2.5 frames with respect to the internal reference signal REF as shown in FIG.

The acknowledgment signal finally output by the above processing is output in a state of being synchronized with the internal reference signal (field synchronization), but is not synchronized with the color frame phase of FIG. 8A. It is shifted by one field.

In the simultaneous recording / reproducing mode, it suffices that the color frame phases match, but it is difficult to match the color frame phases. In the simultaneous recording / reproducing mode, only the recording state is checked. There is no need to match the phases.

However, unlike the simultaneous recording / reproducing mode, in the normal reproducing mode, the color frame phase of the digital reproduction signal needs to match the color frame phase of the internal reference signal REF. When performing an editing process or the like together with another digital video signal using a digital reproduction signal, the color frame phase of the digital reproduction signal matches the color frame phase of the other digital video signal in relation to the color frame phase of the other digital video signal. It is necessary to be.

[0019]

By the way, in order to match the phase of the color frame, as shown in FIGS. 9A, 9B and 9C, the reproduction signal PBo is delayed (delayed) by three fields with respect to the reference synchronization signal REF. , It may be advanced by one field. Since it is necessary to provide a dedicated delay circuit to delay by three fields, it is hard to say that this is a very effective solution.

When the reproduction signal PBo is advanced by one field, the control signal CTL may be advanced by one field, but then the servo lock of the rotary drum 20 is released. This is 1 as described above.
The field is composed of six tracks, and one rotation of the rotary drum 20 is eight tracks.
This corresponds to four rotations. This is because the drum lock is performed in units of one rotation, and thus the servo lock of the rotating drum 20 is released by performing the phase advance processing for one field.

Here, when one rotation is converted into a field, it corresponds to 8/6 = 4/3 field. Therefore, when the control signal CTL is advanced by 4/3 field as shown in FIG. 9E, the delay amount corresponds to one rotation of the rotating drum 20, so that the servo lock of the rotating drum 20 is not released. However, when the advanced control signal CTL 'is used, the reproduced signal PBo is also shifted by 4/3 field.
o is 2/3 as shown in FIG. 9E with respect to the internal reference signal REF.
Color framing can no longer be taken with a shift of the field. This does not meet the initial objectives.

In view of the above, the present invention has been made to solve such a conventional problem, and uses an existing circuit to synchronize the color frame phase with the internal reference signal while maintaining the servo-locked state of the rotating drum. The present invention proposes a digital magnetic recording / reproducing apparatus which can be realized by the above.

[0023]

According to a first aspect of the present invention, there is provided a digital magnetic recording / reproducing apparatus according to the present invention, wherein a digital signal is compressed in synchronization with a control signal generated based on an internal reference signal. In a digital magnetic recording / reproducing apparatus for recording / reproducing a digital signal,
At the time of reproducing the compressed digital signal, the control signal is advanced or retarded in a state where the rotation head is locked, and the reproduced compressed digital signal is supplied to the first ECC decoder to be supplied to the first ECC decoder. The error-corrected compressed digital signal is supplied to the second ECC decoder, and the error-corrected compressed digital signal is supplied to the second ECC decoder.
And the compressed digital signals output from the first and second ECC decoders are respectively delayed so that a reproduced output signal whose color frame phase is synchronized with the internal reference signal is obtained. It is characterized by being done.

According to the present invention, the control signal is set to 4/3.
Advance by the amount of the field. Then, the reproduction signal PBo and the internal reference signal REF are shifted from each other by ／ field due to the relationship with the color frame phase. Therefore, the reproduction signal PBo is delayed by 4/3 field. This delay is performed by the first and second error correction decoders. Since these error correction decoders are provided with a memory as a buffer means for selecting a data reading direction, the reading timing is shifted to delay a time corresponding to a total of 2/3 fields.

Thus, the phase of the expanded processing output (one-field delayed output) of the second error correction decoder is obtained in a state completely synchronized with the color frame phase of the internal reference signal REF. That is, a digital reproduction signal in which color framing is matched can be obtained.

[0026]

Next, an embodiment of a digital magnetic recording / reproducing apparatus according to the present invention will be described in detail with reference to the drawings. Also in the present invention, it is assumed that a digital signal is recorded / reproduced in a tape format as shown in FIG. 7 using a rotating drum 20 constituted by a plurality of magnetic heads as shown in FIG. The reproducing head P provided on the rotating drum 20 is also used as a simultaneous reproducing head during recording. That is, a case where the present invention is applied to a magnetic recording / reproducing apparatus having a recording signal confirmation function will be exemplified as an embodiment.

FIG. 1 shows a main part of a recording / reproducing system provided in the digital video tape recorder 10.
A terminal 101 is supplied with a digital signal to be recorded, for example, a digital video signal, for example, an NTSC digital video signal. The digital video signal is compressed through the input amplifier 103.

In this embodiment, a processing system for compressing and encoding using DCT is employed. Therefore, this digital video signal is converted into DCT coefficients by a DCT conversion circuit 104. Therefore, the digital video signal is first divided into blocks in units of, for example, 8 pixels × 8 lines, and DCT coefficients are obtained in units of blocks. The DCT coefficients are subjected to a shuffling process in units of fields in a field shuffling circuit 105, and thereafter, a compression process and an encoding process are performed in a bit rate reduction circuit 106.

The compression-coded digital video signal is supplied to a first error correction encoder (ECC encoder) 1
At 07, an outer code for error correction is generated in this example.

On the other hand, a digital audio signal is supplied to a terminal 109, and the digital audio signal is subjected to a shuffling process similar to a video signal in a shuffling circuit 112 via an input amplifier 111. Thereafter, an outer code is generated and added by a first error correction encoder (ECC encoder) 113.

The digital video signal and the digital audio signal which have been subjected to the ECC processing are respectively supplied to a multiplexer 1
08 and is subjected to multiplex processing such that a digital video signal and a digital audio signal are output in a time series according to the format shown in FIG.

The multiplexed digital recording signal is provided with identification information ID such as color frame information and segment information in an ID adding circuit 115. After that, an inner code is generated and added by the second error correction encoder 117, and data is added to the digital recording signal to which the outer code and the inner code for error correction are added by the next synchronization adding circuit 118. Synchronous data (sync) for identification is added. The digital recording signal to which the synchronization data has been added is further encoded by the encoder 119 into 1
Encoding processing (channel conversion processing) for alternately outputting digital recording signals for eight tracks of rotation to four recording heads R on one side is performed.
0 (= R) is recorded in a pattern as shown in FIG.

In a reproducing system for reproducing a digital recording signal recorded on the magnetic tape 121, a digital reproduction signal is obtained by performing the reverse signal processing as described above. Therefore, first, the digital reproduction signal reproduced by the reproduction head 122 (= P) is supplied to the decoder 123, and the digital reproduction signal obtained from four reproduction heads P on one side is output as a signal for eight tracks per rotation. Decoding processing (channel conversion processing) is performed. The channel-converted digital reproduction signal is supplied to the synchronization detection circuit 124, where the above-described synchronization data is detected.

Thereafter, the first error correction decoder 125
The digital reproduction signal subjected to the error correction processing is supplied to the ID detection circuit 126, and color frame information and segment information added to the digital reproduction signal are separated and detected. Then, the digital audio signal is separated into a digital video signal and a digital audio signal by the demultiplexer 128, and the separated digital audio signal is supplied to a second error correction decoder 130, where an error correction process using an outer code is executed. The error-corrected digital audio signal is returned to the digital signal before shuffling by the deshuffling circuit 131, and the error correction of the digital signal is performed by the error correction circuit 132. The error-corrected and error-corrected digital audio signal is output to the output terminal 134 via the output amplifier 133.

Similarly, the separated digital video signal is supplied to a second error correction decoder 136, and an error correction process using an outer code is executed. This error-corrected digital audio signal has an inverse bit rate
The decoding process and the decompression process are performed in the reduction circuit 137, and the digital video signal having the original bit length is obtained. After that, the digital signal before shuffling is returned by the deshuffling circuit 138,
39 corrects the error of the digital signal.
Then, an error corrected and error-corrected digital video signal is output to the output terminal 141 via the output amplifier 140.

The control signal CTL generated by the control signal generation circuit 142 is
43 is recorded in the longitudinal direction of the magnetic tape 121.

According to the present invention, as described above, the color frame phase of the digital video signal reproduced by using the pair of error correction decoders 125 and 136 is matched with the phase of the color frame determined by the internal reference signal REF. Processing is performed.

The precondition is that the control signal CTL is phase-adjusted such that it is advanced by 4/3 field in the reproduction mode. This can be achieved by adjusting the output phase of the control signal generation circuit 142 described above, for example, with the intervention of a computer as a control unit.

Further, delay processing of the digital video signal is performed. The delay processing may be performed between the decoder 123 and the output amplifier 140 in the reproduction system of FIG.
It is more convenient to perform it at the signal processing stage where the amount of data to be handled is small. In addition, if existing memory means can be used as a memory means for delaying a signal, processing can be performed without increasing the number of circuit systems, which is more convenient.

With this in mind, the present invention utilizes the memory means provided in the error correction decoders 125 and 136, in particular. FIG. 2 is a conceptual diagram for explaining this, and for convenience of explanation, the decoders 125 and 136 are directly connected, and only peripheral circuits thereof are shown.

The output (digital reproduction signal) of the decoder 123 shown in FIG. 1 is supplied to the terminal 1, and this digital reproduction signal is supplied to the error correction decoder 125 to perform error correction processing using the inner code. The inner code is a correction process in the horizontal direction (horizontal direction), while the outer code process is a process in the vertical direction (vertical direction).
In the subsequent stage, a memory (buffer memory) 4 for changing the reading direction is provided. In order to perform read / write processing on this memory 4, a reproduction control signal CTL 'and a synchronization code are supplied to a synchronization detection and clock generation circuit 14 via a terminal 13, and a clock CLK synchronized with the reproduction control signal CTL' is thereby supplied. , And horizontal and vertical drive pulses HD and VD are output. These signals are supplied to a timing generation circuit 15. The timing generation circuit 15 is also supplied with a pulse signal (FG signal) from a frequency generator 12 attached to the rotary drum 20, and the rotational phase of the rotary drum 20 is changed. It can be detected.

The write pulse WP generated by the timing generation circuit 15 is supplied to the write address generation circuit 5,
The digital video signal that has been subjected to the error correction processing by the inner code with the address data is written. Further, the read pulse RP is supplied to the read address generating circuit 6, and the digital video signal is read based on the read address. Read timing will be described later.

The write direction for the memory 4 is horizontal, while the read direction is vertical. The digital video signal read from the vertical direction is supplied to the second error correction decoder 136. The decoder 136 performs an error correction process using an outer code.

The error-corrected digital reproduction signal is written to a memory (buffer memory) 8 for converting the reading direction from the vertical direction to the horizontal direction. This memory 8 is also provided with a similar write address generation circuit 9 and read address generation circuit 10, so that the written digital video signal is read at a predetermined read timing.

Now, the control signal CTL 'is changed to the state shown in FIG.
As described above, the drum lock of the rotating drum 20 is not released when the phase is advanced by 4/3 field as described above. However, in this case, since the color frame phase of the digital reproduction signal PBo is delayed by one field, the digital reproduction signal PBo is output without matching the color frame phase of the internal reference signal REF as shown in FIGS. 3A and 3D.

When the advanced control signal CTL 'is used, a digital reproduction signal PBa as shown in FIG. 3D is obtained from the reproduction head P. When the channel is converted by the decoder 123, t1 (= 2/3 field) as shown in FIG. 3.) With a delay, a digital reproduction signal PBb having a one-field three-segment configuration is obtained.

This digital reproduction signal PBb is applied to an inner-code decoder 125, subjected to error correction processing, and
2 (the output of the memory 4 described above) (FIG. 3
F). This digital reproduction signal P output with a delay of t2
Bc is supplied to the outer code decoder 136, where it is subjected to error correction processing again, so that it is output after being further delayed by t3 (FIG. 3G). The digital reproduction signal PBd output with a delay of t3 is supplied to an inverse bit rate reduction circuit 137, and after t4, a digital reproduction signal PBo expanded by one field delay is output (FIG. 3H).

In order that the color frame phase of the digital reproduction signal PBo finally obtained is the same as the color frame phase of the internal reference signal REF, the digital reproduction signal PBo is reproduced by the reproduction head P as is clear from FIGS. It is sufficient that the total delay from the end to the inverse bit rate reduction circuit 137 is 1.5 frames. Since the delay amount of the decoder 123 is 2/3 fields and the delay amount of the inverse bit rate reduction circuit 137 is 1 field, the total delay amount of the decoders 125 and 136 is 4/3 fields = 4 segments. You can choose. When the same delay amount is selected for both the decoders 125 and 136,
The delay may be 2/3 fields (= t2 = t3 = 2 segments).

Therefore, the read pulse RP shown in FIG. 2 applied to each of the decoders 125 and 136 has a time difference of 2/3 field from the write start timing. That is, the digital reproduction signals PBc and PBd are read from the memories 4 and 7 with a delay of 2/3 field.

As described above, the phase of the control signal CTL 'is advanced by 4/3 field, and digital reproduction is performed by using the memories 4 and 7 provided in the first and second error correction decoders 125 and 136. The signal PBc,
By delaying PBd by 2/3 field, the color frame phase of the finally output digital reproduction signal PBo can be matched with the color frame phase of the internal reference signal REF.

The capacity of the above memory 4 is 525 lines / 6
In the case of a video signal according to the NTSC system at 0 Hz, 1
Since the track has a 2-ECC block configuration and a 1-ECC block has a 180 × 106-byte configuration, a 4-Mbyte memory is sufficient. The capacity of the other memory 7 is almost 2
M bytes of memory is sufficient, but NT
Considering that a video signal of a television format different from the SC system is handled at the same time, a memory having a capacity of 4 Mbytes is used.

In the above-described example, the input video signal is a color frame sequence and is a two-frame complete type NT.
Although the video signal of the SC system has been exemplified, the present invention can handle video signals of other television systems.

For example, as is well known, the color frame of a PAL system television signal has a sequence of 4 frames = 8 fields, so that the color frame phase makes one cycle in 4 frames. Therefore, the servo signal SC has an 8-field sequence as shown in FIG.
The control signal CTL at that time has a duty as shown in FIG.

When a digital recording signal, which is an input video signal, is recorded using such a servo signal SC and control signal CTL, the timing chart shown in FIG. This figure is almost the same as FIG. 8, and the corresponding parts are denoted by the same reference numerals and description thereof will be omitted. However, FIG. 4 does not show the digital reproduction signal PBa reproduced by the reproduction head P.

If the details are omitted, in the reproduction mode, if the control signal CTL is delayed (slowed) by 8/3 fields, the drum lock can be obtained without changing the rotation phase of the rotating drum 20. In such a case, as shown in FIG. 4 and FIG. 5, the time point exactly 1.5 frames behind the digital reproduction signal PBa becomes the zero phase (first field) of the color frame.
The delay time (read start time) of the memories 4 and 7 described above so that the color frame can be adjusted to the zero phase.
Is determined. In the figure, 2/3 fields (= 2
Segment) and the digital reproduction signal PB
By reading c and PBd (FIGS. 5F, 5G and 5H), a digital reproduction signal PBo synchronized with the color frame phase of the internal reference signal REF is obtained from the inverse bit rate reduction circuit 137 as shown in FIG. Can be

[0056]

As described above, according to the present invention, the control signal for the drum servo is advanced or delayed, and the readout delay time of the two ECC decoders is selected to change the color frame phase of the internal reference signal. A synchronized digital reproduction signal is obtained.

Therefore, according to the present invention, in addition to being able to perform processing without changing the rotation phase of the rotating drum between recording and reproduction, the signal can be delayed using an existing memory without increasing the hardware. Having.

Therefore, in the digital magnetic recording / reproducing apparatus according to the present invention, a handy digital VT
It is suitable for application to R and the like.

[Brief description of the drawings]

FIG. 1 is a system diagram showing an embodiment of a digital magnetic recording / reproducing apparatus according to the present invention.

FIG. 2 is a system diagram of a main part of FIG.

FIG. 3 is a timing chart illustrating synchronization of a color frame phase in the NTSC system.

FIG. 4 is a diagram showing a timing chart for explaining color frame phase synchronization in the PAL system.

FIG. 5 is a timing chart for explaining the synchronization of the color frame phase in the PAL system.

FIG. 6 is a configuration diagram showing an example of a rotating drum applied to a digital magnetic recording / reproducing apparatus.

FIG. 7 is a diagram showing a tape pattern at that time.

FIG. 8 is a diagram showing a timing chart for explaining color frame phase synchronization in the NTSC system.

FIG. 9 is a timing chart illustrating the synchronization of the color frame phases.

[Explanation of symbols]

10, digital VTR, 106, bit rate reduction circuit, 107, 113, 117,.
. Encoders for error correction, 125, 130, 136
..Error correction decoder, 137 ... reverse bit rate reduction circuit, 142 ... control signal generation circuit, 121 ... magnetic tape

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H04N 5/92 H04N 5/92 H 9/79 9/79 K (72) Inventor Hiroaki Kikuchi 6-7 Kita Shinagawa, Shinagawa-ku, Tokyo No. 35 Inside Sony Corporation (72) Inventor Hiroshi Kiriyama 6-35 Kita Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation

Claims (3)

[Claims] 1. A digital magnetic recording / reproducing apparatus for recording / reproducing a compressed digital signal in synchronization with a control signal generated based on an internal reference signal, wherein a lock of a rotary head is maintained during reproduction of the compressed digital signal. In this state, the phase of the control signal is advanced or delayed, and the reproduced compressed digital signal is supplied to a first ECC decoder, where a first error correction process is performed, and the compressed error-corrected compressed signal is processed. The digital signal is supplied to a second ECC decoder to perform a second error correction process, and the compressed digital signals output from the first and second ECC decoders are respectively delayed so that the internal reference signal and the A reproduction output signal synchronized with the color frame phase is obtained. Digital magnetic recording and reproducing apparatus. 2. The read timing of a memory provided in each of a first and second ECC decoders is adjusted,
2. A digital magnetic recording / reproducing apparatus according to claim 1, wherein a reproduction output signal having a color frame phase is output by delaying said compressed digital signal by a predetermined time. 3. The digital magnetic recording / reproducing apparatus according to claim 1, wherein said compressed digital signal is an NTSC or PAL television signal.