JPH10303411A - Fabrication of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for fabricating a semiconductor device in which the threshold voltage VTH can be sustained at a substantially constant level among various kinds of MOSFETs having different channel length when they are mixed while keeping such effects as suppression of short channel effect through pocket ion implantation of MOSFET, and the like. SOLUTION: N type impurity ions are implanted into the vicinity of a P type buried channel region 14 using a gate electrode 11 as a mask to form a pocket ion implantation region 15. The fabrication process comprises a step for compensating the concentration distribution on the surface of the pocket ion implantation region 15 by implanting P type impurities into a same region as the N type impurity ions at a low acceleration energy and bringing the concentration distribution close to the impurity concentration in the P type buried channel region 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a short channel MOSF.
The present invention relates to a method of manufacturing a semiconductor device including an ET, and more particularly to a method of manufacturing a P-channel MOSFET in which an N-type impurity is ion-implanted into a P- type buried channel near a gate electrode to form a pocket ion-implanted region.

FIG. 5 is a sectional view showing the vicinity of a gate electrode of a P-channel MOSFET having a pocket ion implantation region. This P-channel MOSFET is a device having an extremely fine structure with a channel length of submicron or less, and is formed, for example, in an N-type well of a CMOS-LSI. The gate electrode 11 includes a polysilicon layer 11a, a tungsten silicide (WSi) layer 11b, an oxide film layer 11
c. An oxide film 12 is formed on both sides of the gate electrode 11 in a sidewall shape, and a P + type source / drain diffusion region 13 is formed on the oxide film 12 by self-alignment. Immediately below the gate electrode 11 of the semiconductor substrate 10,
A P-type channel ion implantation layer 14 is formed.
Then, immediately below both ends of the gate electrode 11, a source
An N-type pocket ion implantation region 15 is formed adjacent to the drain region 13.

The buried channel region 14 is a shallow P− type diffusion region of, for example, about 0.15 μm from the surface of the semiconductor substrate.
It is provided to adjust the threshold voltage (VTH) of the FET.

The pocket ion implanted region 15 has a problem of a so-called short channel effect in which the channel length becomes narrow, punch-through occurs between the source and the drain, and the breakdown voltage is reduced. By providing such a diffusion region, such a short channel effect can be prevented. The substrate bias effect that the threshold voltage (VTH) of the MOSFET changes due to the fluctuation of the substrate bias can be suppressed. The junction capacitance between the P + type source / drain region and the N type semiconductor substrate can be reduced. It is provided for the purpose such as.

[0005]

However, when the pocket ion-implanted region 15 is formed, this region is an N-type region having a relatively high impurity concentration, so that the P-type buried channel region 14 is formed on the surface of the semiconductor substrate. The concentration of the portion overlapping the pocket ion implantation region is further reduced, and a P-type region 14a is formed. As a result, the average impurity concentration of the channel differs depending on the channel length, and the MOSFET
, The threshold voltage (VTH) decreases, and the leakage current increases.

FIG. 6 shows how threshold voltage (VTH) changes with channel length. As shown in the drawing, for example, in a 0.6 μm process, the threshold voltage of a MOSFET having a channel length of 0.65 μm is about 0.8 V, whereas the threshold voltage of a MOSFET having a channel length of 20 μm is about 0.55 V. The threshold voltage decreases to about 68%.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and maintains various effects such as suppression of a short channel effect due to pocket ion implantation of a MOSFET, and can mix various MOSFETs having different channel lengths. It is another object of the present invention to provide a method of manufacturing a semiconductor device which can keep a threshold voltage (VTH) substantially constant between them.

[0008]

According to the method of manufacturing a semiconductor device of the present invention, a pocket ion-implanted region is formed by ion-implanting an N-type impurity in the vicinity of a P-type buried channel region using a gate electrode as a mask. P-channel MOSFET
In the manufacturing method, the P-type impurity is ion-implanted at a low acceleration energy into the same region as the N-type impurity ion-implanted region, and the concentration distribution on the surface of the pocket ion-implanted region is compensated. A step of approaching the impurity concentration of the channel region.

According to the present invention, the P-type impurity is diffused shallowly into the same region as the pocket ion-implanted region. Buried channel concentration of the mold. As a result, the average impurity concentration of the channel can be kept uniform over the entire surface.
The threshold voltage of a long channel transistor or the like can be made substantially equal to the threshold voltage of a short channel transistor. This makes it possible to prevent the threshold voltage from fluctuating depending on the channel length, and to suppress variations in the threshold voltage (VTH) of an LSI or the like in which MOSFETs of various channel lengths are mixed, regardless of the length of the channel length. It becomes possible.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to FIGS.

Hereinafter, a manufacturing process of a P-channel MOSFET according to an embodiment of the present invention will be described. First, a P- type buried channel region 1 is formed on the surface of an N type semiconductor substrate 10.
4 is formed, a thin insulating film 20 serving as a gate oxide film is formed on the semiconductor substrate, and a gate electrode 11 is formed. Here, the gate electrode 11 includes a polysilicon layer 11a, a tungsten silicide layer 11b, and an oxide film layer 11c as in the conventional technique.

After the formation of the gate electrode, a resist film 20 is applied on the entire surface, and an opening 20a of the resist film is formed by photolithography. Then, using the resist film 22 and the gate electrode 11 as a mask, the pocket ion implantation region 15 is formed by ion implantation. This ion implantation
For example, an acceleration voltage of 100 keV and a dose of 6 × 10 12 /
This is performed by implanting phosphorus, which is an N-type impurity, using cm 2. N-type impurities are implanted around the gate electrode 11 in a self-aligned manner, and an impurity diffusion region 15 is formed by annealing. This stage is shown in FIG.

Next, using the opening 20a of the same resist film and the gate electrode 11 as a mask, that is, using the same mask as the pocket ion implantation, a P-type impurity (boron) is implanted into the same region at a low acceleration energy. This is performed, for example, at an acceleration voltage of 40 keV and a dose of 1 × 10 11 / cm 2. Then, a P-type impurity diffusion region 14b having a high concentration is formed in the N-type pocket ion implantation region by annealing. As a result, the surface portion of the N-type pocket ion implantation region is converted to P-type.

Next, as shown in FIG. 3, oxide films 12 are formed on both side surfaces of the gate electrode 11, and source / drain regions are formed by ion implantation by self-alignment. This is performed by ion-implanting boron, which is a P-type impurity, under the conditions of, for example, an acceleration voltage of 60 keV and a dose of 3 × 10 15 / cm 2. Then, P + type source / drain diffusion regions 13 are formed by annealing. Since this ion-implanted region has a higher concentration than the N-type pocket ion-implanted region, as shown in the figure, except for the pocket ion-implanted region 15a immediately below the gate electrode and the P- type buried channel region 14, the P + type is implanted. Is formed.

FIG. 4 shows a P-channel MO having the structure shown in FIG.
The threshold voltage (V
TH). As shown in FIG.
The threshold voltage (VTH) of a short-channel MOSFET of about 6 μm and a long-channel MOSFET of about 20 μm are almost the same. Therefore,
Even when P-channel MOSFETs having various types of channel lengths are mixed in a CMOS-LSI or a PMOS-LSI, these threshold voltages (VT
H) can be formed to a uniform value.

[0016]

As described above, according to the present invention, the impurity distribution of the opposite conductivity type is implanted into the pocket ion implantation region at a low acceleration energy using the same mask pattern, thereby compensating the concentration distribution on the surface. Thus, a P- type diffusion layer is formed. Thus, the concentration of the channel region at the end of the source / drain region can be made close to the concentration of the original P- type buried channel region which is not affected by the pocket ion implantation region. Therefore, P- at the channel length immediately below the gate electrode
Since the negative type region is eliminated, the dependency of the threshold voltage on the channel length can be eliminated.

On the other hand, since the N-type pocket ion implantation region exists immediately below both ends of the gate electrode, effects such as suppression of a short channel effect and a substrate bias effect can be obtained. Therefore, LS in which MOSFETs of various channel lengths coexist
In I and the like, the threshold voltage of each MOSFET can be made uniform while suppressing the short channel effect, the substrate bias effect, and the like, whereby the characteristics and the yield can be improved.

[Brief description of the drawings]

FIG. 1 is a first sectional view showing a manufacturing process of a PMOSFET according to an embodiment of the present invention.

FIG. 2 is a second cross-sectional view illustrating a manufacturing step of the PMOSFET according to the embodiment of the present invention;

FIG. 3 is a third sectional view showing a manufacturing process of the PMOSFET according to the embodiment of the present invention;

FIG. 4 is an explanatory diagram showing a relationship between a channel length and a threshold voltage according to a manufacturing method of one embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating a PMOSFET according to a conventional embodiment.

FIG. 6 is an explanatory diagram showing a relationship between a channel length and a threshold voltage according to a conventional manufacturing method.

Claims (1)

[Claims] An N-type impurity is ion-implanted in the vicinity of a P-type buried channel region using a gate electrode as a mask,
P-channel MOSF forming pocket ion implantation region
In the method for manufacturing an ET, a P-type impurity is ion-implanted at a low acceleration energy into the same region as the ion-implanted region of the N-type impurity to compensate for a concentration distribution on the surface of the pocket ion-implanted region, and And a step of approaching the impurity concentration of the embedded channel region.