JPH10294660A - Differential amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a differential amplifier which can improve the slew rate without increasing current consumption. SOLUTION: This device is equipped with a differential circuit 1, 2 level shift circuit 11 composed of the serial circuit of a constant current source transistor 5 and a level control transistor 13 to control a current corresponding to the output voltage of the differential circuit 1, a current source circuit 12 serially connecting a current control transistor 15 connecting the node of the constant current source transistor 5 and the level control transistor 13 to its gate and a voltage source transistor 26 mutually connecting its gate and drain, and an output circuit 2 which is composed of the serial circuit of a current mirror transistor 18 connecting the drain voltage of the voltage source transistor 16 to its gate and a control transistor 6 to control a current iB corresponding to an output voltage Vd of the differential circuit 1 and has an output terminal 8 at the node of the current mirror transistor 18 and the control transistor 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential amplifier for use in a digital-to-analog converter for converting a digital color image signal into an analog voltage, for example, incorporated in a liquid crystal driver for driving a TFT matrix color liquid crystal panel. It is about. When this differential amplifying device is integrated into a circuit, a TFT is formed on one semiconductor substrate.
Many are arranged in parallel corresponding to the columns of the matrix color liquid crystal panel.

[0002]

2. Description of the Related Art A conventional differential amplifying apparatus comprises a differential circuit 1 and an output circuit 2, as shown in FIG. Differential circuit 1 receives the input voltage V _in from the input terminal 7 to the non-inverting input terminal 3, which receives the output voltage V _out to the inverting input terminal 4. The output circuit 2 applies the power supply voltage V _DD to the source of the P-channel MOS transistor 5,
A constant bias voltage _Vb is applied to the gate of the OS transistor 5 from the bias terminal 9 so that the P-channel MOS transistor 5 functions as the constant current source transistor 5. The drain of the constant current source transistor 5 is connected to the drain of a control transistor 6 composed of an N-channel MOS transistor, the source of the control transistor 6 is grounded, and the differential circuit 1 is connected to the gate of the control transistor 6.
It has given the output voltage V _d.

An output terminal 8 is provided at a connection point (common drain) between the constant current source transistor 5 and the control transistor 6, and an output voltage _Vout is taken _out therefrom. Next, the operation of the differential amplifier will be described.
In the differential amplifier, the differential circuit 1 outputs an output voltage V _d corresponding to the difference between the output voltage V _out of the input voltage V _in applied to the non-inverting input terminal 3 is applied to the inverting input terminal 4 . In the output circuit 2, the constant current source transistor 5 causes a constant current (sweeping current) i _A to flow, and this current i _A flows toward the output terminal 8 or flows through the control transistor 6 as a through current.

The current flowing through the control transistor 6 (the
Current) i_BFlows through the constant current source transistor 5.
Current i_A(Through current) and the electric current flowing from the output terminal 8
Flow i _OAnd therefore the control transistor 6
Current i flowing through_BBy controlling the output terminal 8
Current i flowing from_O(Or the electric current flowing to the output terminal 8)
Flow-i_O) Can be controlled.

In this differential amplifying device, when used, a capacitive load (not shown) is connected to the output terminal 8, and the voltage _Vout of the output terminal 8 is directly _supplied to the inverting input terminal 4 or a MOS transistor, a capacitor, a resistor, or the like. (Not shown), and considering that there is no leakage current in the capacitive load, the absolute value of the current i _A flowing through the constant current source transistor 5 and the absolute value of the current i _B flowing through the control transistor 6 are considered. The value becomes equal, and the current i _O flowing from the output terminal 8 or the current −i _O flowing out of the output terminal 8 becomes stable in a state where it becomes zero. This state is called a steady state.

Further, every time the voltage V _out applied to the non-inverting voltage V _in applied to the input terminal 3 inverting input terminal 4 is changed, the output voltage V _d is changed in the differential circuit 1, control by this The current i _B flowing through the transistor 6 changes,
By discharging all or a part of the current i _A flowing through the constant current source transistor 5 toward the output terminal 8, the capacitive load connected to the output terminal 8 is charged to increase the output voltage V _out of the output terminal 8. Or output terminal 8
To discharge a capacitive load connected to the output terminal 8 by flowing a current through the control transistor 6 to lower the output voltage _Vout of the output terminal 8. Then, by lifting or lowering of the output voltage V _out, the output voltage V _d of the differential circuit 1 returns to the normal state back to the original.

[0007] Here, in FIG. 7, the current i _A flowing output voltage V _d of the differential circuit 1 to the output circuit 2, illustrating the relationship between i _B. The current i _B increases as the output voltage V _d of the differential circuit 1 increases, and serves as a draw current that causes a current to flow from the output terminal 8 to the connection point between the constant current source transistor 5 and the control transistor 6. Also, the current i
_A is constant irrespective of the output voltage V _out of the differential circuit 1 and is a sweep current flowing out to the output terminal 8 from a connection point between the constant current source transistor 5 and the control transistor 6.

[0008] When the low output voltage V _d of the differential circuit 1,
The current i _B flows zero or very little, the current i _A is larger than the current i _B , and the difference current between the two currents i _A and i _B is from the connection point of the constant current source transistor 5 and the control transistor 6. It flows out to the output terminal 8 and charges the capacitive load connected to the output terminal 8 to increase the output voltage _Vout of the output terminal 8.

The output voltage V of the differential circuit 1_dIs high
The current i_BFlows a lot and the current i _BIs the current i_AYo
And both currents i_A, I_BOutput terminal 8
To constant current source transistor 5 and control transistor
6 and the capacitive load connected to the output terminal 8
Is discharged, and the output voltage V of the output terminal 8 is_outDescend.

[0010] Then, the differential amplifying device, as described above,
Since negative feedback is performed during use, the current i_AThe absolute value of
Flow i_BStabilizes at the point where the absolute values of are equal (stable point).
Here, the operation of the differential amplifier shown in FIG.
This will be described with reference to the imchart. Non-inverting input terminal
3 input voltage V_inHowever, as shown in FIG._A→
V_B→ V_A(V_A> V_B) And a rectangular wave
Think. Input voltage V_inIs V_A→ V_BFall to the difference
Output voltage V of the driving circuit 1_dIs, as shown in FIG.
Current i_AAnd the current i_BThe absolute value of
Stable point voltage V_d0From the voltage V_d1It rises rapidly until.
Thereby, the current i of the control transistor 6_BThe figure
8 (d), the current i at the stable point_B0From the current i_B1
The current i_BRapid discharge of capacitive load
Output voltage V_outIs as shown in FIG.
And the voltage V_o1From the voltage V_o2It descends sharply until. Soshi
And the output voltage V _outIs the voltage V_o2V as approaching
_dFalls and the current i_BDecreases, and the output voltage V_outIs the voltage
V_o2And the current i_BIs the current i_B0Stable in the state
(Steady state).

When the output voltage V _out rises from V _B → V _A as shown in FIG. 8A, the output voltage V _d of the differential circuit 1 becomes as shown in FIG. , The voltage V _{d0 at the} stable point where the absolute value of the current i _A equals the absolute value of the current i _B
From 0 to zero. As a result, as shown in FIG. 8D, the current i _B of the control transistor 6 decreases from the current i _B0 at the stable point to zero, and the charging of the capacitive load is moderated by the current i _A of the constant current source transistor 5. Done in
The output voltage V _out, as shown in FIG. 8 (b), voltage V _o2
Gradually rises to a voltage _Vo1 . And the output voltage V
_out gradually rises to approximately the voltage V _o1, stabilized in a state in which a current i _B becomes current i _B0 (steady state).

As described above, the output voltage V _out of the output terminal 8
Are fast and slow to rise because the current capacity of the control transistor 6 is increased and the current of the constant current source transistor 5 is suppressed to flow through the constant current source transistor 5 and the control transistor 6 in a steady state. This is because the through current is reduced to reduce the power consumption.

[0013]

SUMMARY OF THE INVENTION As described above, the conventional technology
In the dynamic amplifier circuit, the current capacity of the control transistor 6 is large.
However, in order to reduce power consumption,
Through the constant current source transistor 5 and the control transistor 6
To reduce the shoot-through current, that is, the constant current source
Current i_AWas kept low. As a result, the output end
Output voltage V of child 8 _outShut down the machine relatively quickly
Output voltage V_outOf the constant current source
Current i of transistor 5_ATo do faster because there is less
Can not be obtained, only those with low slew rate can be obtained
Was.

On the other hand, in order to obtain a high slew rate, it is necessary to increase the current of the constant current source transistor 5, and as a result, in a steady state, the constant current source transistor 5 and the control transistor 6 Therefore, there is a problem that a through current flowing through the semiconductor device increases and power consumption increases. Accordingly, an object of the present invention is to provide a differential amplifying device capable of increasing a slew rate and reducing power consumption.

[0015]

According to a first aspect of the present invention, there is provided a differential amplifier which outputs a voltage corresponding to a difference between a voltage applied to a non-inverting input terminal and a voltage applied to an inverting input terminal. A level shift circuit consisting of a series circuit of a constant current source transistor that flows a constant current and a level control transistor whose current is controlled according to the output voltage of the differential circuit;
A current source circuit in which a current control transistor in which a connection point between a constant current source transistor and a level control transistor is connected to a gate, a voltage source transistor in which a gate and a drain are connected to each other are connected in series, and a drain of the voltage source transistor is gated An output circuit, comprising a series circuit of a current mirror transistor connected to the control circuit and a control transistor whose current is controlled according to the output voltage of the differential circuit, and having an output terminal provided at a connection point between the current mirror transistor and the control transistor. Have.

According to the configuration of the first aspect, when the output voltage of the differential circuit is high, the current of the current mirror transistor decreases and the current of the control transistor increases. When the output voltage of the circuit is low, the current of the current mirror transistor increases and the current of the control transistor decreases. In addition, in a steady state, the current can be stabilized at an arbitrary constant value. As a result, the current flowing from the current mirror transistor to the output terminal and the current flowing from the output terminal to the control transistor can be increased while reducing the shoot-through current, and the slew rate of the output voltage can be increased, and the power consumption can be increased. Electric power can be reduced.

The differential amplifier according to the second aspect is the first aspect of the invention.
In the differential amplifying device described above, between two transistors of a level shift circuit composed of a series circuit of a constant current source transistor that flows a constant current and a level control transistor whose current is controlled according to the output voltage of the differential circuit Is connected to a constant voltage transistor whose gate and drain are connected to each other, and the connection point between the constant current source transistor and the constant voltage transistor is used as the output of the level shift circuit.

According to the configuration of the second aspect, the response of the operation can be improved by limiting the output voltage range of the level shift circuit by the constant voltage transistor. According to a third aspect of the present invention, in the differential amplifying apparatus according to the first aspect, the differential amplifier is fixed to a current control transistor side of a current source circuit including a current control transistor and a voltage source transistor whose gate and drain are connected to each other. Are connected in series.

According to the third aspect of the present invention, when the output voltage is close to the power supply voltage and the output voltage is smaller than the input voltage even in a steady state, the current flows through the current source circuit by the current limiting constant current source transistor. The current consumption can be reduced by suppressing an increase in the excessive current. According to a fourth aspect of the present invention, in the differential amplifying device according to the second aspect, the differential amplifying device is fixed to a current control transistor side of a current source circuit including a current control transistor and a voltage source transistor having a gate and a drain connected to each other. Are connected in series.

According to the present invention, when the output voltage is close to the power supply voltage and the output voltage is smaller than the input voltage even in the steady state, the current flows through the current source circuit by the current limiting constant current source transistor. The current consumption can be reduced by suppressing an increase in the excessive current.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment; Corresponding to Claim 1] FIG. 1 is a circuit diagram of a differential amplifier according to a first embodiment of the present invention. As shown in FIG. 1, the differential amplifier includes a differential circuit 1 and
Output circuit 2, level shift circuit 11, current source circuit 1
And 2.

The differential circuit 1 is a conventional example similar to the arrangement of FIG. 7, the input voltage V _in from the input terminal 7 to the non-inverting input terminal 3
, And the output voltage V _out is input to the inverting input terminal 4. The level shift circuit 11 applies the power supply voltage V _DD to the source of the P-channel MOS transistor 5, applies a constant bias voltage _Vb to the gate of the P-channel MOS transistor 5 from the bias terminal 9, and switches the P-channel MOS transistor 5. It functions as a constant current source transistor 5. The drain of the constant current source transistor 5 has
The drain of the level control transistor 13 composed of an N-channel MOS transistor is connected, the source of the level control transistor 13 is grounded, and the level control transistor 1
The third gate has applied the output voltage V _d of the differential circuit 1. Then, a voltage _VL is output from a connection point (common drain) between the constant current source transistor 5 and the level control transistor 13.

The current source circuit 12 includes a level shift circuit 11
The output voltage V _L is applied to the gate of the current control transistor 15 of N-channel MOS transistor, and grounding the source of the current control transistor 15, a current control transistor 15 voltage source transistor comprising a P-channel MOS transistor to the drain of 16 And the source of the voltage source transistor 16 is applied with the power supply voltage V _DD .

The output circuit 2 applies a gate voltage V _c of the voltage source transistor 16 to the gate of the current mirror transistors 18 consisting of P-channel MOS transistor,
The power supply voltage V is applied to the source of the current mirror transistor 18.
_DD is applied, the drain of the current mirror transistor 18 is connected to the drain of the control transistor 6 composed of an N-channel MOS transistor, and the control transistor 6
Grounding the source, and applies the output voltage V _d of the differential circuit 1 to the gate of the control transistor 6. An output terminal 8 is provided at a connection point between the drain of the current mirror transistor 18 and the drain of the control transistor 6, and an output voltage _Vout is extracted therefrom.

Next, the operation of the differential amplifier according to the first embodiment will be described. In this differential amplifier,
Differential circuit 1 outputs the voltage V _d corresponding to the difference between the output voltage V _out of the input voltage V _in applied to the non-inverting input terminal 3 is applied to the inverting input terminal 4. Output voltage V _d of the differential circuit 1 is lowered when V _in> V _out, increases when V _in <V _out, is stabilized when V _in = V _out.

The output circuit 2 supplies a current to a load by using the current mirror transistor 18 and the control transistor 6 connected to the output terminal 8 so that the output voltage V
_out is controlled. When the output voltage V _d of the differential circuit 1 is lowered, the current i _N1 of the level control transistor 13 is decreased, the voltage V _L rises. When the voltage V _L increases, the current i ₂ is increased lower the voltage V _c, the current i _A of the current mirror transistor 18 is increased. At this time, the output voltage V _d of the differential circuit 1 is lowered, the current i _B of control transistor 6 decreases.

[0027] Conversely, when the output voltage V _d of the differential circuit 1 is increased, the current i _A of the current mirror transistor 18 is decreased, the current i _B of control transistor 6 is increased. Hereinafter, the operation of each circuit will be described in detail. First, the level shift circuit 11 includes a constant current source transistor 5 flowing a constant current (sweeping current) i _P1, level control transistor 13 in accordance with the output voltage V _d of the differential circuit 1,
The current i _N1 flows and the current difference i ₁ is

[0028]

[Equation 1] i₁= I_N1−i_P1 But the output voltage V of the differential circuit 1_dIs high, the current i
_N1Increases, and the current i ₁Becomes positive and level shift
Output voltage V of circuit 11_LDescends. Also, the differential circuit 1
Output voltage V_dIs low, the current i_N1Is smaller and the current
i₁Becomes negative, and the output voltage V of the level shift circuit 11 becomes
_LRises. Output voltage V_LFalls, the current control
Current i of transistor 15_TwoDecreases and the current mirror
Current i of transistor 18_AAlso decreases. Output voltage V_Lof
When rising, the current i of the current control transistor 15_TwoIs increasing
And the current i of the current mirror transistor 18_AAlso increase
I do. Voltage V_LWhen is stable, i₁= 0,

[0029]

[Number 2] to become a i _N1 = i _P1, current i _N1 flowing through the level control transistor 13, wherein the drain current i _d in the saturation operation, the current amplification factor beta, between the gate and source V _gs Voltage and V _t
Is the threshold voltage,

[0030]

## EQU3 ## where _id = (β / 2) × (V _gs −V _t ) ² and the level control transistor 13 is β / 2 = β
When _{n13 / 2, V t = V} tn, since equal to current i _N1 and the current i _P1 as expression (2), the current i _P1 is

[0031]

## EQU4 ## i _P1 = (β _n13 / 2) × (V _d −V _tn ) ² , and the voltage V _d is determined. In the following description,
Subscripts n _and p added to β mean n-channel _and p-channel _, respectively, and the numbers correspond to the signs of the transistors.

Further, since the voltage V _d is determined, the current i _B flowing through the control transistor 6 is given by: β 2 = β _n6 / 2, V _t = V _tn

[0033]

## _EQU5 ## i _B = (β _n6 / 2) × (V _d −V _tn ) ² When the output voltage _VL of the level shift circuit 11 is stable, the current i _{B in the} steady state is expressed as i _N1 =
i _P1 , and the current value becomes stable, so that [Equation 4] and [Equation 5]

[0034]

## _EQU6 ## It is stable at i _B = (β _n6 / β _n13 ) × i _P1 . Therefore, the output current i _B is determined by the current i _P1 of the constant current source transistor 5 and the size ratio of the level control transistor 13 and the control transistor 6, and the output current is stabilized at a current according to [Equation 6]. Thus, the output current can be determined without using the constant current source transistor conventionally provided for determining the output circuit current.

Next, in a steady state,

[0036]

## EQU7 ## Since i _A = i _B , the voltage V _c is given by the following equation: β / 2 = β _p18 / 2 and V _t = V _tp of the current mirror transistor 18.

[0037]

[ _Expression 8] i _A = (β _p18 / 2) × (V _c −V _DD −V _tp ) ² By the voltage V _c determined, current i ₂
Is that the voltage source transistor 16 is β / 2 = β _p16 / 2,
V _t = V _tp , and the current control transistor 15 is β / 2 = β
When _{n15 / 2, V t = V} tn,

[0038]

I ₂ = (β _p16 / 2) × (V _c −V _DD −V _tp ) ²

[0039]

I ₂ = β _n15 / 2 × (V _L −V _tn ) ² , and the voltage V _L is determined. Here, the operation of the differential amplifier of FIG. 1 will be described with reference to a time chart of FIG.

The input voltage Vin of the non-inverting input terminal 3 is shown _in FIG.
As shown in _{(a), V A → V} B → V A (V A> V B)
And a case where the shape changes into a rectangular wave. Voltage V _in V _A →
When the voltage falls to V _B , the output voltage V _d of the differential circuit 1 becomes a stable point voltage V _{d0 at which} the absolute value of the current i _{A and} the absolute value of the current i _B become equal, as shown in FIG. _Rapidly rises up to the voltage V _d1 . Thereby, the level shift circuit 11
Output voltage V _L falls to zero as shown in FIG. 3D, and the current i ₂ decreases. As a result, the current i _A of the current mirror transistor 18 decreases to zero as shown in FIG.
_B rapidly increases from the current i _B0 at the stable point to the current i _B1 as shown in FIG. 3 (f), and the capacitive load is discharged by the current i _B , and the output voltage V _out becomes As shown in b), the voltage drops sharply from the voltage _Vo1 to the voltage _Vo2 . Then, as the output voltage V _out approaches the voltage V _o2 , the voltage V
_d is lowered, reduces the current i _B, the output voltage V _out becomes voltage V _o2, stabilized in a state in which a current i _B becomes current i _B0 (steady state).

Further, the voltage V _in, as shown in FIG. 3 (a), rises to V _B → V _A, the output voltage V _d of the differential circuit 1, as shown in FIG. 3 (c), The voltage V _{d0 at the} stable point where the absolute value of the current i _{A and} the absolute value of the current i _B are equal falls from zero. Thus, the output voltage V _L of the level shift circuit 11 is increased to V _L1 as shown in FIG. 3 (d), the current i ₂ is increased. As a result, the current i _A of the current mirror transistor 18 increases to the current i _{A1 as} shown in FIG. 3E, and the current i _B of the control transistor 6 conversely increases as shown in FIG. Since the current i _{B0 at the} stable point decreases from zero to zero, the current i _A flows out of the current mirror transistor 18 to the output terminal 8, and the capacitive load is quickly charged, and the output voltage V _out becomes the output voltage V _out shown in FIG. As shown in the _figure , the voltage rises from the voltage _Vo2 to the voltage _Vo1 . Then, the output voltage V _out rises to the voltage V _o1 , the current i _A returns to i _A0 , and the current i _B stabilizes in a state where the current i _B has become the current i _B0 (steady state).

The differential amplifier according to the first embodiment has
Constant current i_P1Current source transistor 5 and differential circuit
Output voltage V of path 1_dCurrent i depending on_N1Level controlled
Level control circuit composed of a series circuit with the
Shift circuit 11, constant current source transistor 5, and level control
Current control with the connection point of transistor 13 connected to the gate
Transistor 15 and gate and drain connected to each other
And the voltage source transistor 16 connected in series.
The current source circuit 12 and the drain of the voltage source transistor 16
Difference from the current mirror transistor 18 connected to the gate
Output voltage V of the driving circuit 1_dCurrent i depending on_BIs controlled
It consists of a series circuit with the control transistor 6,
At the connection point between the color transistor 18 and the control transistor 6.
Since the output circuit 2 having the output terminal 8 is provided,
Output voltage V of circuit 1_dCurrent mirror when
Current i of transistor 18_AIncrease the control transistor
Current i_BDecreases, and conversely, the output voltage of the differential circuit 1
V_dRises when the current mirror transistor 18
Current i_ADecrease, and the current i of the control transistor 6 _BBut
It can be controlled to increase. As a result, penetration
While reducing the current, the current mirror transistor 18
From the output terminal 8 to the output terminal 8
To increase the current flowing into the control transistor 6
Output voltage V_outCan increase the slew rate of
Power consumption can also be reduced.

[Second Embodiment: Corresponding to Claim 2] FIG. 2 is a circuit diagram of a differential amplifier according to a second embodiment of the present invention. As shown in FIG. 2, the differential amplifier includes a differential circuit 1, an output circuit 2, and a level shift circuit 11 '.
And a current source circuit 12. Differential circuit 1
Has a configuration similar to that of FIG. 7, _in which the input voltage Vin is input from the input terminal 7 to the non-inverting input terminal 3 and the output voltage _Vout is input to the inverting input terminal 4.

The level shift circuit 11 'includes a P-channel M
A power supply voltage V _DD is applied to the source of the OS transistor 5,
A constant bias voltage _Vb is applied to the gate of the P-channel MOS transistor 5 from the bias terminal 7 so that the P-channel MOS transistor 5 functions as a constant current source transistor 5. A constant voltage transistor 1 comprising a drain of the constant current source transistor 5 and an N channel MOS transistor having a gate and a drain connected to each other.
9 are connected in series with each other, and the source of the constant voltage transistor 19 and the drain of the level control transistor 13 composed of an N-channel MOS transistor whose current is controlled according to the output voltage of the differential circuit 1 are connected. grounding the source of the level control transistor 13, and applies the output voltage V _d of the differential circuit 1 to the gate of the level control transistor 13. Then, a voltage _VL is output from a connection point (common drain) between the constant current source transistor 5 and the constant voltage transistor 19.

The current source circuit 12 includes the level shift circuit 1
The output voltage V _L 1 'is supplied to the gate of the current control transistor 15 of N-channel MOS transistor, and grounding the source of the current control transistor 15, the voltage source comprising a P-channel MOS transistor to the drain of the current control transistor 15 The drain and the gate of the transistor 16 are connected. The power supply voltage V _DD is applied to the source of the voltage source transistor 16.

The output circuit 2 applies a gate voltage V _c of the voltage source transistor 16 to the gate of the current mirror transistors 18 consisting of P-channel MOS transistor,
The power supply voltage V is applied to the source of the current mirror transistor 18.
_DD is applied, the drain of the current mirror transistor 18 is connected to the drain of the control transistor 6 composed of an N-channel MOS transistor, and the control transistor 6
Grounding the source, and applies the output voltage V _d of the differential circuit 1 to the gate of the control transistor 6. An output terminal 8 is provided at a connection point between the drain of the current mirror transistor 18 and the drain of the control transistor 6, and an output voltage _Vout is taken _out therefrom.

Next, the operation of the differential amplifier according to the second embodiment will be described. In this differential amplifier,
Differential circuit 1 outputs the voltage V _d corresponding to the difference between the output voltage V _out of the input voltage V _in applied to the non-inverting input terminal 3 is applied to the inverting input terminal 4. Output voltage V _d of the differential circuit 1 is lowered when V _in> V _out, increases when V _in <V _out, is stabilized when V _in = V _out.

The output terminal 8 of the output circuit 2 is connected to the output terminal 8.
Control with connected current mirror transistor 18
Supply current to the load by the transistor 6
Output voltage V_outIs controlling. Output voltage of differential circuit 1
V_dDecreases, the current i_N1Decreases and the voltage V_LRise
You. Voltage V_LRises, the current i_TwoIncreases the voltage V _c
Decrease, and the current i of the current mirror transistor 18_A
Increase. At this time, the current i of the control transistor 6
_BDecreases.

[0049] Conversely, when the output voltage V _d of the differential circuit 1 is increased, the current i _A is reduced in the current mirror transistor 18, the current i _B of control transistor 6 is increased. Hereinafter, the operation of each circuit will be described in detail. First, in the level shift circuit 11 ′, the constant current source transistor 5 flows a constant current (sweep current) i _P1 , the level control transistor 13 flows the current i _N1 according to the output voltage V _d of the differential circuit 1, The current difference i ₁ is

[0050]

[Equation 11]₁= I_N1−i_P1 But the output voltage V of the differential circuit 1_dIs high, the current i
_N1Increases, and the current i ₁Becomes positive and level shift
Output voltage V of circuit 11 '_LDescends. Output of differential circuit 1
When the force voltage is low, the current i_N1Becomes smaller and the current i₁Is negative
And the output voltage V of the level shift circuit 11 '_LIs above
Ascend. Output voltage V_LFalls, the current control transistor
The current i of the star 15_TwoDecrease and the current mirror transition
The current i of the star 18_AAlso decreases. When rising, the current control
Current i of transistor 15_TwoIncreases and the current mirror tiger
Current i of transistor 18_AAlso increase. Voltage V_LWhen stable
Is i₁= 0,

[0051]

Since i _N1 = i _P1 , the current i _N1 flowing through the level control transistor 13 is calculated from [Equation 3].

[0052]

Equation 13] _{i P1 = (β n13 / 2} ) × (V d -V tn) 2 to be V _d is determined. Since V _d is determined, the current i _B flowing through the control transistor 6 becomes

[0053]

I _B = (β _n6 / 2) × (V _d −V _tn ) ² The output current i _{B in the} steady state is determined by the level shift circuit 1
When the output voltage V _L of 1 ′ is stable, as shown in [Equation 11], i _N1 = i _P1 and the current value is stabilized.
3] and [Equation 14]

[0054]

## _EQU15 ## It is stable at i _B = (β _n6 / β _n13 ) × i _P1 . Therefore, the output current i _B is determined by the current i _P1 of the constant current source transistor 5 and the size ratio of the level control transistor 13 and the control transistor 6. Thus, it is not necessary to provide a constant current source transistor exclusively as a transistor for outputting a current to a load.

Next, in a steady state,

[0056]

Since i _A = i _B , the voltage V _c becomes

[0057]

I _A = (β _p18 / 2) × (V _c −V _DD −V _tp ) ² By the voltage V _c determined, current i ₂
Is

[0058]

I ₂ = (β _p16 / 2) × (V _c −V _DD −V _tp ) ²

[0059]

[Number 19] _{i 2 = (β n15 / 2} ) × (V L -V tn) becomes ^2, voltage V _L is determined. By providing the constant voltage transistor 19, the voltage V _{L
Lm in}

[0060]

## _EQU20 ## V _Lmin = V _tn + {i _N1 / (β _n4 / 2)}, and when the constant voltage transistor 19 is not provided, the voltage _VL is lower than the ground voltage, The response of the current control transistor 15 can be accelerated by the time until the voltage V _Lmin is reached.

Here, the operation of the differential amplifier shown in FIG.
Will be described with reference to the time chart of FIG. Non
Input voltage V of inverting input terminal 3_inHowever, as shown in FIG.
U, V_A→ V_B→ V_A(V_A> V_B) And a rectangular wave
Let's consider the case. Voltage V_inIs V_A→ V_BFall to
Then, the output voltage V of the differential circuit 1_dIs shown in FIG.
Thus, the current i_AAnd the current i_BThe absolute value of
Voltage V at a stable point_d0From the voltage V_d1Rise rapidly until
You. Thus, the output voltage of the level shift circuit 11 '
V_LIs the lowest voltage V as shown in FIG._LminDown to
And the current i_TwoDecrease. As a result, the current mirror
The current i of the transistor 18_AIs as shown in FIG.
Current i_A2, And conversely, the current of the control transistor 6
i_BIs the current i at the stable point, as shown in FIG._B0Or
Current i_B1And the current i_BDue to capacity negative
The load is rapidly discharged, and the output voltage V_outFigure 4
As shown in FIG._o1From the voltage V_o2Rapidly
Descend. And the output voltage V_outIs the voltage V_o2Approach
According to the voltage V_dFalls and the current i_BOutput power
Pressure V_outIs the voltage V _o2And the current i_BIs the current i_B0Becomes
(Steady state).

[0062] Further, the voltage V _in, as shown in FIG. 4 (a), rises to V _B → V _A, the output voltage V _d of the differential circuit 1, as shown in FIG. 4 (c), The voltage V _{d0 at the} stable point where the absolute value of the current i _A becomes equal to the absolute value of the current i _B rapidly drops from zero. As a result, the output voltage _VL of the level shift circuit 11 'becomes the voltage V _L as shown in FIG.
Increased to _L1, current i ₂ is increased. As a result, the current i _A of the current mirror transistor 18 increases to the current i _{A1 as} shown in FIG. 4E, and the current i _B of the control transistor 6 conversely increases as shown in FIG. reduced from the current i _B0 stable point to zero, and drain current i _a of the constant current source transistor to the output terminal 8, and so that the current i _a flowing through the current mirror transistor 18 is shown in FIG. 4 (e) ( In fact, the polarity is reversed), the current rapidly increases to the current i _A1 , and this current i _A flows out of the control transistor 6 to the output terminal 8, and the capacitive load is quickly charged, and the output voltage V _out becomes As shown in FIG. 4B, the voltage rapidly rises from the voltage _Vo2 to the voltage _Vo1 . And the output voltage V
_out rises to approximately the voltage V _o1, current i _A is returned to the current i _A0, stabilized in a state a state in which current i _B becomes current i _B0 (steady state).

The differential amplifier according to the second embodiment has
A constant current source transistor 5 for flowing a constant current and a constant voltage transistor 19 having a gate and a drain connected to each other.
Bets are connected in series to each other, the level shift circuit 11 further comprises a serial circuit in which the level control transistor 13 current is controlled is connected in series in accordance with the output voltage V _d of the constant voltage transistor 19 and the differential circuit 1 ', A current control transistor 15 having a gate connected to a connection point of the constant current source transistor 5 and a constant voltage transistor 19, and a voltage source transistor 16 having a gate and a drain connected to each other.
Control transistor 6 but the current source circuit 12 connected in series, the current i _B in accordance with the output voltage V _d of the current mirror transistor 18 and the differential circuit 1 and the drain connected to the gate of the voltage source transistor 16 is controlled made a series circuit of a, so that an output circuit having a output terminal 8 to the connecting point of the current mirror transistor 18 and control transistor 6, the current mirror transistors when lowered output voltage V _d of the differential circuit 1 18 current i _a of the increases, the current i _B decreases of the control transistor 6, conversely,
When the voltage _Vd rises, the current mirror transistor 1
8, the current i _A of the control transistor 6 decreases.
_B can be controlled to increase. As a result, the current flowing from the current mirror transistor 18 to the output terminal 8 and the current flowing from the output terminal 8 to the control transistor 6 can be increased while reducing the through current.
The slew rate of the output voltage _Vout can be increased, and the power consumption can be reduced.

Further, in this embodiment, since the constant voltage transistor 19 is provided, the level shift circuit 1
1 'can be limited, and the response of the current control transistor 15 can be improved. [Third Embodiment: Corresponding to Claims 3 and 4] Next, a third embodiment of the present invention will be described. Here, the input in the description of the first and second embodiments will be described. voltage V _in
Operation when the power supply voltage V _DD is supplied to the power supply.

In the description of the first embodiment, V
_out = V _DD near the current mirror transistor 18
A constant voltage drop ΔV is generated between the source and the drain of the transistor, so that V _out = V _DD −ΔV, and V _in > V _out even in a steady state. At this time, the output V _d of the differential circuit 1 falls from V _d0 as shown _in FIG. 3C when Vin rises from V _B → V _A, and the output V _{L of the} level shift circuit 11 Rises to V _L1 . As a result, the current i ₂ flowing through the current source circuit 12 increases.

That is, the output voltage V_outAs power supply voltage
V_DDInput voltage V _inPower supply voltage V_DDNearby
When a potential is supplied near, even in a steady state, V_in> V
_OUTAnd the output potential V of the differential circuit 1_dFalls,
Current i of the control transistor 13_N1Decreases and the level
Output potential V of the shift circuit 11_LRises,
Gate potential of current control transistor 15 of flow source circuit 12
Rises, an excess current flows through the current source circuit 12 and the
In some cases, the current consumption increases. Below, such as
An embodiment that can solve the problem will be described.

FIG. 5 shows a circuit diagram of a differential amplifier according to a third embodiment of the present invention. This differential amplifying device is an embodiment corresponding to the embodiment of FIG. 1, and includes a differential circuit 1, an output circuit 2, and a level shift circuit 11 as shown in FIG.
And a current source circuit 12 '. Differential circuit 1, the input voltage V _in from the input terminal 7 to the non-inverting input terminal 3
, And the output voltage V _out is input to the inverting input terminal 4.

[0068] In the level shift circuit 11, a power supply voltage V _DD is applied to the source of P-channel MOS transistor 5, giving a constant bias voltage V _b from the bias terminal 9 to the gate of the P-channel MOS transistor 5, P-channel MOS The transistor 5 is operated as the constant current source transistor 5. The above constant current source transistor 5
Is connected to the drain of a level control transistor 13 composed of an N-channel MOS transistor,
Grounding the source of the level control transistor 13, and applies the output voltage V _d of the differential circuit 1 to the gate. And
Constant current source transistor 5 and level control transistor 13
The voltage _VL is output from the connection point (common drain).

In the current source circuit 12 ', the N-channel MO
The source of the S transistor 20 is grounded, and the N channel M
By _{applying a} constant bias voltage V _bn to the gate of the OS transistor 20 from the bias terminal 21, an N-channel MOS
Transistor 20 is a constant current source transistor 2 for limiting current.
It functions as 0. The output voltage _VL of the level shift circuit 11 is applied to the gate of a current control transistor 15 composed of an N-channel MOS transistor, and the drain of the current control transistor 15 is connected to the drain and gate of a voltage source transistor 16 composed of a P-channel MOS transistor. And the power supply voltage V _DD is applied to the source of the voltage source transistor 16. Also,
The drain of the current limiting constant current source transistor 20 is connected to the source of the current control transistor 15.

The output circuit 2 is connected to the
Gate potential V_cFrom the P-channel MOS transistor
Applied to the gate of the current mirror transistor 18
Power supply to the source of the current mirror transistor 18.
Pressure V_DDAnd apply a drain to the N-channel MOS transistor.
Connected to the drain of a control transistor 6 composed of a transistor
Then, the source of the control transistor 6 is grounded and
Output voltage V of differential circuit 1 _dIs applied. This Karen
Connection between the trimer transistor 18 and the control transistor 6
An output terminal 8 is provided at the connection point, and the output voltage V_outTake
I am trying to start.

Next, the operation of the differential amplifier will be described. In the differential amplifier, the differential circuit 1 outputs the voltage V _d corresponding to the difference between the output voltage V _out of the input voltage V _in applied to the non-inverting input terminal 3 is applied to the inverting input terminal 4. Output voltage V _d of the differential circuit 1 is lowered when V _in> V _out, increases when V _in <V _out, is stabilized when V _in = V _out.

The output circuit 2 is connected to the output terminal 8.
Current mirror transistor 18 and control transistor
And the output voltage V
_outIs controlling. Output voltage V of differential circuit 1_dIs below
Then, the current i of the level control transistor 13_N1Decreases
And the voltage V_LRises. Voltage V_LRises and the current i
_TwoIncreases the voltage V_cFalls, the current mirror transition
The current i of the star 18_AIncrease. At this time, the differential circuit 1
Output voltage V_dIs reduced, the control transistor 6
Current i_BDecreases.

[0073] Conversely, when the output voltage V _d of the differential circuit 1 is increased, the current i _A is reduced in the current mirror transistor 18, the current i _B of control transistor 6 is increased. When V _in = V _{out in the} steady state, the operation is the same as that of the first embodiment as described below. Input voltage V
_{When in} rises (V _in > V _out ), the output V _{d of the} differential circuit 1
Falls, the current i _N1 of the control transistor 13 decreases, and the output potential _VL of the level shift circuit 11 increases. Then, 'the gate potential of the current control transistor 15 rises, the current source circuit 12' the current source circuit 12 increases the current i ₂ flowing through the results flowing electric i _A current mirror transistor 18 is increased as. On the other hand, the differential circuit 1
When the output V _d of descends, the control transistor 6
It reduces the current i _B flowing to the output voltage V _out current flows out to an external load from the output terminal 8 rises, V _i
= V _out, it becomes a steady state.

On the contrary, V_inFalls (V_in<V_out)When
Output V of differential circuit 1_dRises and the level shift circuit 11
Output potential V_LFlow to the current source circuit 12 '.
Current i_TwoDecrease, and as a result
Current i flowing through transistor 18 _ADecreases and the difference
Output V of dynamic circuit 1_dRises, the control transformer
The current i flowing through the transistor 6_BIncrease and output terminal 8
Current flows from the load and the output voltage V_outFalls and V_in
= V_outAt the steady state.

In the steady state, the potential of each node and the current flowing therethrough are also determined as follows, as in the first embodiment. The output potential V _d of the differential circuit 1 is, as in [Equation 4],

[0076]

I _P1 = (β _n13 / 2) × (V _d −V _tn ) ² = (β _p5 / 2) × (V _b −V _DD −V _tp ) ² Current i flowing through current mirror transistor 18 and control transistor 6 of output circuit 2
_A and i _B are the same as in [Equation 6].

[0077]

## _EQU22 ## It is stable at i _A = i _B = (β _n6 / β _n13 ) × i _P1 . The gate potential V _c of the current mirror transistor 18 is, as in [Equation 8],

[0078]

I _A = (β _p18 / 2) × (V _c −V _DD −V _tp ) ² Current i ₂ flowing through current source circuit 12 ′
Is, like [Equation 9],

[0079]

I ₂ = (β _p16 / 2) × (V _c −V _DD −V _tp ) ² Hereafter, i ₂ is called i _2const . Here, by applying an appropriate bias potential V _bn to the current limiting constant current source transistor 20, the current limiting constant current source transistor 20
Constant current value i _{2l mt}

[0080]

[ _Formula 25] i _lmt = (β _p20 / 2) × (V _bn −V _DD −V
_tp ) ² Set so that ² > _i2const . The output voltage _VL of the level shift circuit 11 is, like [Equation 10],

[0081]

(26) i_Two= (Β_n15/ 2) × (V_L-V_tn)^Two= I_2const Is determined by Next, the output voltage V_outAs power
Voltage V_DDThe input voltage V _inPower supply voltage
V_DDIs supplied, and even in a steady state, V_in> V
_outThe circuit operation in the case of
This will be described with reference to FIG.

The input voltage V of the non-inverting input terminal 3_inFigure 6
As shown in FIG._B→ V_A(V _B<V_A= V_DDWhen
To rise). Output voltage of differential circuit 1
V_dDescends as shown in FIG. 6 (c),
Output voltage V of level shift circuit 11_LIs shown in FIG.
V_L1And the current i_TwoIs shown in FIG.
To increase. However, at this time, the current i_TwoIs current control
Current limited by the constant current source transistor 20
Value i_2lmtNo more flows.

As a result, the current i _A of the current mirror transistor 18 increases, and the output voltage V _out changes as shown in FIG.
As shown above, the voltage rises to V _o1, but as described above, V _o1 =
Since the voltage rises only up to V _DD -ΔV <V _DD , even in the steady state, V _in > V _out remains, and V _L also becomes V
Since the current i ₂ does not decrease until an input potential _{satisfying in} <V _out is supplied, the current i ₂ remains increased, but the current value i is limited by the current limiting constant current source transistor 20.
_It does not flow for more than _2lmt . Note that in FIG.
_2max is

[0084]

I _2max = (β _n15 / 2) × (V _L1 −V _tn ) ² As described above, according to the differential amplifying device of the third embodiment, the current i _N1 is changed according to the constant current source transistor 5 for flowing the constant current i _P1 and the output voltage V _d of the differential circuit 1. A level shift circuit 11 composed of a series circuit of a level control transistor 13 to be controlled, a current control transistor 15 having a gate connecting a connection point of the current source transistor 5 and the level control transistor 13 to a gate, and a voltage having a gate and a drain connected to each other. Source transistor 1
6 are connected in series, and the current control transistor 1
A current source circuit 12 'comprising a series circuit in which a current limiting constant current source transistor 20 for flowing a constant current to the fifth side is connected in series, and a voltage source transistor 16 of the current source circuit 12'
A series circuit of a current mirror transistor having a drain connected to its gate and a control transistor 6 whose current i _B is controlled in accordance with the output voltage V _d of the differential circuit 1,
Current mirror transistor 18 and control transistor 6
Because of and an output circuit 2 provided with an output terminal 8 to the connection point, when the lowered output voltage V _d of the differential circuit 1, current i _A of the current mirror transistor 18 is increased, the control transistor 6 Current i _B decreases, and conversely, when the output voltage V _d of the differential circuit 1 rises, the current i _A of the current mirror transistor 18 decreases and the current i _B of the control transistor 6 increases. Can be controlled. as a result,
The current flowing from the current mirror transistor 18 to the output terminal 8 and the current flowing from the output terminal 8 to the control transistor 6 can be increased while _reducing the through current, and the slew rate of the output voltage V _out can be increased. ,
Moreover, power consumption can be reduced.

Further, a current limiting constant current source transistor
20, the output voltage V _outIs the power supply voltage V_DD
And V in the steady state_in> V_outNext differential
Output potential V of circuit 1_dDescends, resulting in a level shift
Output voltage V of the gate circuit 11_LCaused by rising
Current i flowing through the current source circuit 12 '_TwoTo i_2maxTo
And the current consumption can be reduced.

In this embodiment, the current limiting constant current source transistor 20 is added to the configuration of the first embodiment. Similarly, the current limiting constant current transistor 20 is added to the configuration of the second embodiment. Needless to say, the same effect as described above can be obtained even when the limiting constant current source transistor 20 is provided.

[0087]

According to the differential amplifier of the first aspect,
A level shift circuit consisting of a series circuit of a constant current source transistor that flows a constant current and a level control transistor whose current is controlled according to the output voltage of the differential circuit, and a connection point between the constant current source transistor and the level control transistor A current source circuit in which a current control transistor connected to the gate and a voltage source transistor whose gate and drain are connected to each other are connected in series; a current mirror transistor in which the drain voltage of the voltage source transistor is connected to the gate and an output of the differential circuit It consists of a series circuit of a control transistor whose current is controlled according to the voltage, and has an output circuit provided with an output terminal at a connection point between the current mirror transistor and the control transistor, so that the output voltage of the differential circuit decreases. Current, the current of the current mirror transistor increases, Other current decreases, conversely, the current of the current mirror transistor is reduced when the increased output voltage of the differential circuit, the current of the control transistor can be controlled to increase. As a result, the current flowing from the current mirror transistor to the output terminal and the current flowing from the output terminal to the control transistor can be increased while reducing the through current, and the slew rate of the output voltage of the output circuit can be increased. In addition, power consumption can be reduced.

According to the differential amplifier of the second aspect, the constant voltage transistor is provided between the constant current source transistor and the level control transistor, and the minimum voltage of the output voltage of the level shift circuit is increased, so that the level shift circuit is provided. Can be limited to increase the response of the current control transistor. According to the differential amplifying device of the third or fourth aspect, a current limiting circuit for flowing a constant current to a current control transistor side of a current source circuit including a current control transistor and a voltage source transistor having a gate and a drain connected to each other. Since the constant current source transistor is provided in series, the input voltage becomes close to the power supply voltage, and the output voltage does not rise following the input voltage in the vicinity of the power supply voltage. Even if the output voltage of the differential circuit remains falling and the gate potential to the current control transistor of the current source circuit rises, the excessive current flowing through the current source circuit is suppressed from increasing and the current consumption is reduced. can do.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a differential amplifier according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a differential amplifier according to a second embodiment of the present invention.

FIG. 3 is a timing chart of each part showing the operation of the differential amplifier according to the first embodiment of the present invention.

FIG. 4 is a timing chart of each part showing the operation of the differential amplifier according to the second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a differential amplifier according to a third embodiment of the present invention.

FIG. 6 is a timing chart showing an operation of the differential amplifier according to the third embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration of an example of a conventional differential amplifier.

8 is a timing chart of each part showing the operation of the differential amplifier in FIG. 7;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Differential circuit 2 Output circuit 3 Non-inverting input terminal 4 Inverting input terminal 5 Constant current source transistor 6 Control transistor 7 Input terminal 8 Output terminal 9 Bias terminal 11, 11 'Level shift circuit 12, 12' Current source circuit 13 level Control transistor 15 Current control transistor 16 Voltage source transistor 18 Current mirror transistor 19 Constant voltage transistor 20 Current limiting constant current transistor 21 Bias terminal

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yumiko Kataoka 1006 Ojidoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (4)

[Claims] A differential circuit for outputting a voltage corresponding to a difference between a voltage applied to a non-inverting input terminal and a voltage applied to an inverting input terminal; a constant current source transistor for flowing a constant current; A level shift circuit comprising a series circuit of a level control transistor whose current is controlled in accordance with the output voltage of the current control transistor, a current control transistor having a gate connecting a connection point of the constant current source transistor and the level control transistor, and a gate and a drain A current source circuit in which voltage source transistors connected to each other are connected in series; a current mirror transistor in which the drain of the voltage source transistor is connected to the gate; and a current controlled in accordance with an output voltage of the differential circuit. The current mirror transistor and the control transistor. A differential amplifier comprising: an output circuit having an output terminal at a connection point. 2. A differential circuit for outputting a voltage corresponding to a difference between a voltage applied to a non-inverting input terminal and a voltage applied to an inverting input terminal, a constant current source transistor flowing a constant current, and a gate and a drain. A constant voltage transistor connected to each other is connected in series with each other, and furthermore, a series circuit is formed in which the constant voltage transistor and a level control transistor whose current is controlled according to the output voltage of the differential circuit are connected in series. A level shift circuit, a current source circuit in which a current control transistor in which a connection point between the constant current source transistor and the constant voltage transistor is connected to a gate and a voltage source transistor in which a gate and a drain are connected to each other are connected in series; A current mirror transistor in which the drain of the voltage source transistor is connected to the gate and the output of the differential circuit A differential amplifying device comprising a series circuit of a control transistor whose current is controlled according to a force voltage, and comprising an output circuit provided with an output terminal at a connection point between the current mirror transistor and the control transistor. 3. A differential circuit for outputting a voltage corresponding to a difference between a voltage applied to a non-inverting input terminal and a voltage applied to an inverting input terminal, a constant current source transistor for flowing a constant current, and the differential circuit. A level shift circuit comprising a series circuit of a level control transistor whose current is controlled according to the output voltage of the current control transistor; a current control transistor having a gate connected to a connection point between the constant current source transistor and the level control transistor; and a gate and a drain. A current source circuit comprising a series circuit in which a voltage source transistor connected to each other is connected in series, and a current limiting constant current source transistor for flowing a constant current to the current control transistor side is further connected in series; A current mirror transistor in which the drain of the voltage source transistor is connected to the gate and the output voltage of the differential circuit Flip to become a series circuit of a control transistor current is controlled, the differential amplifier having an output circuit having a output terminal to the connection point of the control transistor and the current mirror transistors. 4. A differential circuit that outputs a voltage corresponding to a difference between a voltage applied to a non-inverting input terminal and a voltage applied to an inverting input terminal, a constant current source transistor that flows a constant current, and a gate and a drain. A constant voltage transistor connected to each other is connected in series with each other, and a constant voltage transistor and a level control transistor whose current is controlled according to an output voltage of the differential circuit are connected in series. A level shift circuit, a current control transistor having a gate connecting a connection point of the constant current source transistor and the constant voltage transistor, and a voltage source transistor having a gate and a drain connected to each other are connected in series; Series circuit in which constant current source transistors for current limiting that allow a constant current to flow through A current source circuit, and a series circuit of a current mirror transistor having a drain connected to the gate of the voltage source transistor and a control transistor whose current is controlled according to the output voltage of the differential circuit. An output circuit having an output terminal at a connection point of the control transistor.