JPH10294386A - Mask rom and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a mask ROM and a method for manufacturing the same which enable reduction in the numbers of steps by programming concurrently with formation of a source region and a drain region. SOLUTION: After a first gate 35 and a second gate 36 are formed on a P type semiconductor substrate 31, side walls 37 are formed respectively on the sides of the first gate 35 and the second gate 36. And the side wall 37 formed on the side of the second gate 36 is removed, N type impurity ions are then implanted into an exposed portion of the semiconductor substrate 31 to form an impurity region 41, thus forming a first channel 43 and a second channel 45 having a different effective channel length from each other. Therefore ON transistors and OFF transistors having different effective channel lengths are formed concurrently with formation of a source region and a drain region in one ion implantation step to program data, thus simplifying the steps.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mask ROM (Ma
More particularly, the present invention relates to a mask ROM for performing ion implantation and programming using a mask and a method of manufacturing the same.

[0002]

2. Description of the Related Art A ROM is a nonvolatile memory (non-volatile memory) configured so that stored data is not erased even when the power is turned off.
A mask ROM, a PROM (Programmable ROM), and an EPROM (E
electrically programmable ROM) or EEPROM (E
rasable and Electrically Programmable ROM).

In the mask ROM, data desired by a user is incorporated as data into a mask used during a manufacturing process of the ROM, and is programmed (written) during a wafer process. Is impossible, and is a read-only memory for data written during the manufacturing process. As a method of writing data in the mask ROM, an impurity is ion-implanted so that the threshold voltage Vth (thresh
An ion implantation process system for changing the ld voltage is widely used.

FIGS. 5 to 8 are views showing a process of manufacturing a conventional mask ROM. First, as shown in FIG. 5, a depletion layer 13 doped with an N-type (second conductivity type) impurity is formed on a semiconductor substrate 11 made of P-type (first conductivity type) silicon. I do.
The depletion layer 13 is formed by depositing N-type impurity ions such as arsenic As or phosphorus P into 5 × 10 ¹² to 1 × 10 ¹³ / cm ^2.
Implanted ion dose (dose dose) and 80-120K
It is formed by injecting at an acceleration voltage (energy) of about eV. The depletion layer 13 has a threshold voltage Vth (threshold) of a transistor formed later.
voltage) is set to about -3 to -4 so that this transistor becomes an ON transistor (depletion type transistor). Here, the semiconductor substrate 1
1 was formed from a P-type silicon substrate,
It may be a P-type wale region formed on a silicon substrate of the type.

[0005] Next, as shown in FIG.
The surface of the depletion layer 13 formed by thermal oxidation is thermally oxidized to form an oxide film, and polycrystalline silicon doped with impurities is formed on the oxide film by chemical vapor deposition (Chemical Vapor Deposition).
(r Deposition: hereinafter referred to as a CVD method) to form a polycrystalline silicon layer. Then, the polycrystalline silicon layer and the oxide film are sequentially patterned by a photolithography method to form a gate oxide film 1.
5 and a gate 17 are formed. Then, the semiconductor substrate 11
A silicon oxide film is deposited thereon so as to cover the gate 17 by a CVD method. Then, the silicon oxide is etched back by a reactive ion etching (hereinafter, referred to as RIE) method so that the surfaces of the semiconductor substrate 11 and the gate 17 are exposed. 19 is formed.

Subsequently, as shown in FIG. 7, arsenic As or phosphorus P is used by using the gate 17 and the side wall 19 as a mask.
1 × 10 ¹⁵ -1 × 10 ¹⁶ / c
The impurity region 21 is formed by implantation with an implanted ion amount of about m ² and an acceleration voltage of about 30 to 80 KeV. At this time, the gate 17 is used as a mask so that impurity ions to be implanted are implanted only on both sides of the gate 17. Therefore, the impurity regions 21 are formed on both sides of the gate so as to overlap with the depletion layer 13. In the above, the depletion layer 13 below the gate 17 formed in the impurity region 21 serves as a channel, and the formed transistor has a depletion type.

Next, as shown in FIG. 8, a photosensitive film 23 is applied to the entire surface of the above-described structure, and then the photosensitive film 23 is
Gate 1 of a predetermined transistor to be programmed with data
Exposure, development and patterning are performed so that 7 is exposed. Then, using the photoresist 23 as a mask, a P-type impurity ions such as boron B or BF _2, 1 × 10
^The implantation ion amount is about ^{13 to} 2 × 10 ¹³ / cm ² and is implanted at a high acceleration voltage of about 140 to 180 KeV so as to penetrate through the exposed gate 17 and implant into the depletion layer 13.

In this case, the depletion layer 13 below the gate 17 reacts with the N-type impurity ions doped with the P-type impurity ions implanted therethrough to form the canceling layer 25. The canceling layer 25 serves as a channel of a predetermined transistor. The canceling layer 25 has a threshold voltage Vth of the channel larger than 0 V (approximately 0.7 V).
V). Therefore, the predetermined transistor is changed from a depletion type to an enhancement type (enhancement type).
ment type), whereby the mask ROM is programmed with data. Then, the photosensitive film 23 used as the mask is removed.

[0009]

However, according to the above-described conventional method of manufacturing a mask ROM, each ion is formed for forming source and drain regions and for programming data (switching from depletion type to enhancement type). Since the injection step is required, there is a problem that the step is complicated.

An object of the present invention is to provide a mask ROM in which formation of source and drain regions and programming of data can be performed in one ion implantation step, and a method of manufacturing the same.

[0011]

According to another aspect of the present invention, there is provided a mask ROM comprising a semiconductor substrate of a first conductivity type, first and second gates formed on the semiconductor substrate, and A sidewall formed on a side surface of the first gate; a second conductivity type impurity region formed on both sides of the first gate of the semiconductor substrate; and a second gate formed on both sides of the second gate of the semiconductor substrate. And a second conductivity type impurity region formed to extend to near the center.

According to this configuration, the effective lengths of the two channels formed in the first and second gates are different from each other due to the impurity region, and an ON transistor and an OFF transistor are formed. Here, it is preferable that side walls are formed only on side surfaces of the first gate of the first gate and the second gate.

Further, it is preferable that the first and second gates have a gate oxide film. When the effective channel length of the first gate is L1, the effective channel length of the second gate is L2, and the length of the side wall of the first gate is Ls, the effective channel length L2 is: It is good to make L2 = L1-2 · Ls.

In order to achieve the above object, a method of manufacturing a mask ROM according to the present invention comprises the steps of forming first and second gates on a semiconductor substrate of a first conductivity type, and forming the first and second gates on side surfaces of the first and second gates. Forming a side wall on each side, removing the side wall formed on the side surface of the second gate, implanting impurity ions of a second conductivity type into an exposed portion of the semiconductor substrate to form an impurity region. Forming first and second channels having different effective channel lengths from each other.

According to this structure, after removing the side wall of the second gate, impurity ions are implanted by using the gate and the side wall as a mask, so that channels having different effective lengths can be formed by one ion implantation. Thus, an ON transistor and an OFF transistor are formed. In the above-described manufacturing method, the impurity region of the second conductivity type may be 1 × 10 ¹⁵
~ 1 × 10 ¹⁶ / cm ² about 30-80K
It is preferable to form by implanting at an acceleration voltage of about eV.

Also, the step of forming the first and second gates includes the step of forming an oxide film on the semiconductor substrate;
The method may include a step of forming a polycrystalline silicon layer on the oxide film, and a step of patterning the polycrystalline silicon layer and the oxide film. Further, it is preferable that the effective channel length of the first channel is formed longer than the effective channel length of the second channel by the side wall.

Furthermore, when the effective channel length of the first channel is L1, the effective channel length of the second channel is L2, and the length of the side wall of the first gate is Ls, the effective channel length is L1. L2 is preferably formed such that L2 = L1-2 · Ls.

Here, the effective channel length L2 of the second channel may be formed such that L2 = L1-2Ls> 0 or L2 = L1-2Ls <0. According to another aspect of the present invention, there is provided a method of manufacturing a mask ROM, comprising: forming a gate oxide film on a semiconductor substrate of a first conductivity type; depositing polysilicon on the gate oxide film; Forming a plurality of gates, forming side walls each having a length Ls on each of the plurality of gate side surfaces, and applying a photosensitive film to cover the plurality of gates; Patterning so that the remaining gate is not exposed, removing the sidewall formed on the side surface of the exposed predetermined gate, removing the patterned photosensitive film, and removing the remaining gate. And exposing the exposed portion of the semiconductor substrate with an impurity ion of a second conductivity type to activate the impurity region to form an impurity region. An effective length L2 (L2 = L1-2) that is shorter than the effective length L1 of the channel by a sum of the length Ls of the side walls formed on both sides of the gate below the predetermined gate.・ L
and s) forming a channel.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows a mask ROM according to the present invention.
FIG. In the mask ROM according to the present invention, a gate oxide film 33 is interposed on a surface of a semiconductor substrate 31 made of P-type (first conductivity type) silicon, and first and second gates 3 are formed.
5, 36 are formed. Here, P of the semiconductor substrate 31
Although formed from the silicon substrate of the mold type, there may be a p-type wale region formed on the silicon substrate of the p-type or the n-type.

A length L is provided on the side surface of the first gate 35.
The side wall 37 having s is formed. N on the semiconductor substrate 31
Type (second conductivity type) impurity ions are doped at a high concentration to form impurity regions 41 used as source and drain regions. The impurity region 41 is formed using the first and second gates 35 and 36 and the side wall 37 as a mask, and is separated from the first and second channels 43 and 45 having different effective lengths L1 and L2. It is formed.

The first channel 4 below the first gate 36
3 is formed so as to have an effective length L1 approximately equal to the channel length of the MOS transistor. Therefore, the effective length L
The transistor having one first channel 43 is an enhancement type and has off characteristics. That is, the enhancement-mode transistor having the first channel 43 of the effective length L1 has a positive threshold voltage Vth, and thus maintains the off state unless a drive voltage is applied to the first gate 35, and the drive voltage is reduced. When applied, it is turned on.

On the other hand, the second gate 36
Channel 45 is the effective length L1 of the first channel 43
Side walls 3 formed on both sides of first gate 35
7 is a short effective length L2 that is the sum of the lengths Ls (2 · Ls)
Having. Therefore, the effective length L2 of the second channel 45
Is compared with the effective length L1 of the channel 43, L2 =
L1-2 · Ls. Accordingly, the transistor having the second channel 45 of the effective length L2 is a depletion type and has a negative threshold voltage Vth, so that no driving voltage is applied to the second gate 36 and a voltage lower than the driving voltage. Is turned on even if is applied.

In the above, if the sum (= 2 · Ls) of the lengths Ls of the side walls 37 is smaller than the effective length L1 of the first channel 43, that is, if L2 = L1-2Ls> 0, the impurity region 41 Are separated by a second channel 45 having a very short effective length L2. Therefore, during the operation of the mask ROM, the transistor having the second channel 45 causes a punch-through between the impurity regions 41 due to the drain voltage regardless of whether the driving voltage is applied to the second gate 36. It turns on.

The sum of the lengths Ls of the side walls 37 (= 2 · L
If s) is greater than the effective length L1 of the first channel 43, the effective length L2 of the second channel 45 is L2 = L
1-2Ls <0. That is, the impurity region 41
It overlaps below the second gate 36. Therefore, in the transistor where the impurity region 41 overlaps, the source and the drain are short-circuited and turned on.

As described above, the mask ROM according to the present invention
When 0 V is applied to the first gate 35 and a voltage is applied to the impurity region 41 constituting the drain, the transistor having the first channel 43 is not driven, and thus has an off characteristic. However, the transistor having the second channel 45 is turned on because the impurity region 41 used for the source and the drain is short-circuited or punched through by the drain voltage and a current flows from the source to the drain. Therefore, the data stored in the mask ROM can be read by sensing the operation of each cell transistor.

FIGS. 2 to 4 show a mask ROM according to the present invention.
FIG. 4 is a process chart showing a method for manufacturing the same. First, as shown in FIG. 2, a surface of a semiconductor substrate 31 made of P-type (first conductivity type) silicon is thermally oxidized to form an oxide film, and polycrystalline silicon doped with impurities is formed on the oxide film. Is deposited by a CVD method to form a polycrystalline silicon layer. Then, the polycrystalline silicon layer and the oxide film are patterned by a photolithography method to form a gate oxide film 33 and a number of first and second gates 35 and 36. In the above description, the semiconductor substrate is formed from a P-type silicon substrate, but may be a P-type wale region formed on a P-type or N-type silicon substrate.

An oxide is deposited on the semiconductor substrate 31 by a CVD method so as to cover the first and second gates 35 and 36.
Then, the oxide is etched back by the RIE method so that the surfaces of the semiconductor substrate 31 and the first and second gates 35 and 36 are exposed, and a length Ls is added to each of the side surfaces of the first and second gates 35 and 36. Is formed. Next, as shown in FIG. 3, a photosensitive film 39 is applied on the entire surface of the above-described structure so as to cover the first and second gates 35 and 36, and then the gate of a predetermined transistor, that is, the second gate 36 is formed. Exposure and development are performed so as to expose the pattern. Then, the exposed side wall 37 of the second gate 36 is removed using the photosensitive film 39 as a mask. In the above, the side wall 37 on the side surface of the second gate 36
Can be removed by a dry etching method or a wet etching method using a solution such as hydrofluoric acid HF.

Subsequently, as shown in FIG. 4, the photosensitive film 39 is removed, and the remaining first gate 35 is exposed. Then, using the first and second gates 35 and 36 and the side wall 37 as a mask, the arsenic As
Alternatively, N-type (second conductivity type) impurity ions such as phosphorus P are implanted with an implanted ion amount of about 1 × 10 ¹⁵ to 1 × 10 ¹⁶ / cm ² and an acceleration voltage of about 30 to 80 KeV for activation. The impurity regions 4 used for the source and drain regions.
Form one.

In this case, the first and second gates 35, 36
And first and second channels 43, 4 having effective lengths L1, L2 different from each other depending on the impurity region 41.
5 are formed. That is, the first channel 43 has an effective length L1 about the length of the MOS transistor, and the second channel 45 is formed on both sides of the first gate 35 with the effective length L1 of the first channel 43. It has a short effective length L2 (L2 = L1-2 · Ls) which is only the sum of the length Ls of the side walls 37 and 2 · Ls.

Therefore, the first channel 4 of the effective length L1
3 is an enhancement type transistor having a positive threshold voltage Vth, ie, an off transistor, while a transistor having a second channel 45 having an effective length L2 is a depletion type transistor having a negative threshold voltage Vth. A transistor, that is, an ON transistor.

Here, the second channel 45 is formed such that the effective length L2 is extremely short or the impurity region 41 is formed.
Are overlapped and the effective length L2 is lost and short-circuited, so that a depletion type transistor is obtained.
The sum 2 · Ls of the lengths Ls of the side walls 37 formed on both sides of the gate 35 is the effective length L of the first channel 43.
If the length is longer than 1 (if L1-2Ls <0), the impurity region 41 overlaps below the second gate 36, loses the effective length L2, is short-circuited, and the second channel 45 is not formed.

In the above, the method of manufacturing the mask ROM according to the embodiment of the present invention has been described as a configuration in which an N-type (second conductivity type) transistor is formed on a P-type (first conductivity type) semiconductor substrate. , The first conductivity type is N type, and the second conductivity type is P
As a type, a P-type transistor can be formed on an N-type semiconductor substrate. As described above, in the method of manufacturing a mask ROM according to the present invention, a side wall having a length Ls is formed on each of the side surfaces of the first and second gates, and then the second side surface is formed.
The side wall formed on the side surface of the gate is removed. And 1
At the same time as forming impurity regions forming source and drain regions by ion implantation, channels having different effective lengths L1 and L2 are formed, and an ON transistor and an OFF transistor are formed.

[0033]

As described above, according to the mask ROM of the present invention, channels having different effective lengths are provided depending on the impurity regions, thereby forming the ON transistor and the OFF transistor. There is an effect that it can be easily manufactured by only one ion implantation for forming.

According to the method of manufacturing a mask ROM according to the present invention, of the side walls formed on the first and second gates, after removing the side wall of the second gate, impurity ions are implanted to form the impurity region. By forming the first and second channels, the effective lengths of which are different from each other, data is programmed, so that there is no need to perform two ion implantations, and the manufacturing process is simplified. .

[Brief description of the drawings]

FIG. 1 is a sectional view of a mask ROM according to the present invention.

FIG. 2 is a manufacturing process diagram of a mask ROM according to the present invention.

FIG. 3 is a manufacturing process diagram of a mask ROM according to the present invention.

FIG. 4 is a manufacturing process diagram of a mask ROM according to the present invention.

FIG. 5 is a manufacturing process diagram of a mask ROM according to a conventional technique.

FIG. 6 is a manufacturing process diagram of a mask ROM according to a conventional technique.

FIG. 7 is a manufacturing process diagram of a mask ROM according to a conventional technique.

FIG. 8 is a manufacturing process diagram of a mask ROM according to a conventional technique.

[Explanation of symbols]

 31: Semiconductor substrate 33: Gate oxide film 35: First gate 36: Second gate 37: Side wall 39: Photosensitive film 41: Impurity region 43: First channel 45: Second channel

Claims (12)

[Claims] A semiconductor substrate of a first conductivity type; first and second gates formed on the semiconductor substrate; sidewalls formed on side surfaces of the first gate; Second formed on both sides of the gate
A mask ROM comprising: a conductivity type impurity region; and a second conductivity type impurity region formed on both sides of the second gate of the semiconductor substrate so as to extend to near the center of the second gate. 2. The mask ROM according to claim 1, wherein a side wall is formed only on a side surface of the first gate of the first gate and the second gate. 3. The mask ROM according to claim 1, wherein said first and second gates have a gate oxide film. 4. An effective channel length of the first gate is L.
1. When the effective channel length of the second gate is L2 and the length of the side wall of the first gate is Ls, the effective channel length L2 is L2 = L1-2 · Ls. 4. The mask ROM according to claim 1, wherein: 5. The method according to claim 1, wherein the first and second semiconductor substrates are formed on a first conductive type semiconductor substrate.
Forming a gate; forming sidewalls on each of the first and second gate side surfaces; removing the side walls formed on the side surfaces of the second gate; exposing the semiconductor substrate; Forming impurity regions by implanting impurity ions of the second conductivity type into the portions to form first and second channels having different effective channel lengths. Method. 6. The method according to claim 1, wherein the impurity region of the second conductivity type is 1 × 10 ¹⁵
~ 1 × 10 ¹⁶ / cm ² about 30-80K
6. The method for manufacturing a mask ROM according to claim 5, wherein the mask ROM is formed by implanting at an acceleration voltage of about eV. 7. The step of forming the first and second gates, the steps of: forming an oxide film on the semiconductor substrate; forming a polysilicon layer on the oxide film; 7. The method for manufacturing a mask ROM according to claim 5, comprising a step of patterning a layer and said oxide film. 8. The effective channel length of the first channel is longer than the effective channel length of the second channel by the side wall.
8. The method for manufacturing a mask ROM according to any one of items 7. 9. The effective channel length of the first channel is L1, and the effective channel length of the second channel is L1.
2. When the length of the side wall of the first gate is Ls,
The mask R according to claim 8, wherein the effective channel length L2 is formed such that L2 = L1-2 · Ls.
OM manufacturing method. 10. The method according to claim 9, wherein the effective channel length L2 of the second channel is formed such that L2 = L1-2Ls> 0. 11. The method according to claim 9, wherein the effective channel length L2 of the second channel is formed such that L2 = L1-2Ls <0. 12. A step of forming a gate oxide film on a semiconductor substrate of a first conductivity type, depositing polycrystalline silicon on the gate oxide film and patterning the same to form a plurality of gates; Forming a sidewall having a length of Ls on each of the side surfaces of the plurality of gates; applying a photosensitive film so as to cover the plurality of gates; and patterning such that predetermined gates are exposed and the remaining gates are not exposed. Removing the side wall formed on the side surface of the exposed predetermined gate; removing the patterned photosensitive film, exposing the remaining gate, and forming a second portion on the exposed portion of the semiconductor substrate.
Impurity ions are implanted and activated to form an impurity region, and at the same time, a channel having an effective length L1 below the remaining gate and an effective length L1 of the channel below the predetermined gate. Forming a channel having an effective length L2 (L2 = L1-2 · Ls) shorter by the sum of the lengths Ls of the side walls formed on both sides of the mask ROM. Method.