JPH10289578A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device permitting to improve a refresh characteristic by controlling a well-bias voltage according to an operation mode. SOLUTION: A semiconductor storage device set to occasional. operation mode based an externally inputted control signal is provided with a bias voltage generation circuit 11. The bias voltage generation circuit 11 is connected with a well 12 in which memory cell is formed, and generates and supplies a well bias voltage to the well 12 and controls the well bias voltage to a constant potential. Further, the bias voltage generation signals ϕ1-ϕn corresponding to an occasional operation mode are inputted to the bias voltage generation circuit 11, which controls the well bias voltage to be a constant potential corresponding to an occasional operation mode, and supplies it to the well 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device having a bias voltage generating circuit for supplying a bias voltage to a well of a memory cell.

2. Description of the Related Art In recent years, portable devices such as notebook personal computers and the like are equipped with a large-capacity memory, and a dynamic random access memory (DRAM) having a high degree of integration is used as the large-capacity memory.

In a DRAM, it is necessary to always refresh a memory cell in order to retain data, and the refresh current is related to a use time of a battery provided in a portable device, that is, a use time of the portable device. There is a demand for improved refresh characteristics.

[0004]

2. Description of the Related Art Generally, a DRAM is provided with a bias voltage generating circuit 1 as shown in FIG. 5 on a semiconductor chip. The bias voltage generation circuit 1 is provided for supplying a well bias voltage of a predetermined negative voltage to a well and holding cell information of a memory cell formed in the well.

The bias voltage generation circuit 1 includes a bias voltage detection circuit 2 and a bias voltage generation circuit 3. The bias voltage detection circuit 2 keeps the well bias voltage VBB generated by the bias voltage generation circuit 3 constant. The bias voltage detection circuit 2 is a P-channel MOS connected in series.
Transistor (hereinafter referred to as PMOS transistor) T
P1 and N-channel MOS transistors (hereinafter referred to as NMO
TN1 (referred to as an S transistor). A plurality (three in FIG. 5) of diode-connected NMOS transistors TNa1 to TNa3 are connected to the NMOS transistor TN1.
Are connected in series. NMOS transistors TNa1-T
The number (the number of stages) of Na3 is set according to the potential of the well bias voltage VBB kept constant.

The level of the node N1 between the transistors TP1 and TN1 is supplied to a bias voltage generating circuit 3 via an inverter circuit. The bias voltage generating circuit 3
For example, it comprises a known charge pumping circuit, and operates and stops based on the level of the supplied node N1. Then, the bias voltage generating circuit 3 lowers the well bias voltage VBB from the low potential power supply VSS during the operation.

When the power is turned on, the level of the well bias voltage VBB is 0 volt (V) and the node N1 is at the H level, so that the bias voltage generating circuit 3 operates to reduce the well bias voltage VBB to minus. Start pulling to the side. The well bias voltage VBB is applied to the NMOS transistor T
When the level reaches the level determined by the number of stages N1, TNa1 to TNa3, the NMOS transistors TN1, TNa1 to TN
a3 turns on, the node N1 goes low, and the bias voltage generation circuit 3 stops. When the well bias voltage VBB rises and the NMOS transistors TN1 and TNa1 to TNa3 turn off, the node N1 goes to the H level, and the bias voltage generation circuit 3 operates again. Accordingly, the bias voltage generation circuit 1 detects the well bias voltage VBB by the bias voltage detection circuit 2 to drive and control the bias voltage generation circuit 3, and the well bias voltage VBB is determined by the number of NMOS transistors TN1, TNa1 to TNa3. To a constant level.

Some DRAMs have a bias voltage generating circuit 5 as shown in FIG. 6 mounted on a semiconductor chip. The bias voltage generation circuit 5 includes a bias voltage generation circuit 6 and a clamp circuit 7. The bias voltage generation circuit 6 is composed of, for example, a known charge pumping circuit, and operates constantly by supplying power to lower the well bias voltage VBB from the low potential power supply VSS.

The clamp circuit 7 includes an NMOS transistor TN2 having a drain connected to the low potential power supply Vss.
The NMOS transistor TN2 has a plurality (3 in FIG. 6).
) Diode-connected NMOS transistors TN
b1 to TNb3 are connected in series. NMOS transistor T
The number (the number of stages) of N2, TNb1 to TNb3 is set in accordance with the potential of the well bias voltage VBB kept constant.

When the power is turned on, the bias voltage generating circuit 6 operates to start pulling the well bias voltage VBB to the negative side. When the well bias voltage VBB reaches a level determined by the number of stages of the NMOS transistors TN2, TNb1 to TNb3, the NMOS transistors TN2, TN
Since b1 to TNb3 are turned on and current flows from the wiring of the low potential power supply VSS to the wiring of the well bias voltage VBB, the well bias voltage VBB is prevented from lowering further. Therefore, the well bias voltage VBB is kept constant.

[0011]

By the way, a general D
The RAM is controlled to switch to a plurality of operation modes based on a control signal input from the outside. The operation modes include
For example, there are a standby mode in which the operating power supply voltage is reduced to reduce power consumption, an active mode in which cell information can be read from and written to a memory cell, and the like.
However, the above bias voltage generation circuits 1 and 5
The well bias voltage VBB is always controlled to a constant potential regardless of the operation mode, that is, the well bias voltage VBB is controlled to an intermediate potential in each operation mode. Therefore, depending on the operation mode, the refresh characteristics may be poor, that is, the refresh time may be short, which hinders reduction in power consumption of the DRAM.

The tests performed on the DRAM include an accelerated test for testing the product life of the DRAM. In the accelerated test, the operating power supply voltage of the packaged DRAM and the well bias voltage VBB are repeatedly increased and decreased, thereby shortening the time until failure and performing the test in a short time. However, since the bias voltage generation circuits 1 and 5 are formed on a DRAM chip, it is difficult to change and supply the well bias voltage from outside. For this reason, since the accelerated test cannot be performed by changing the well bias voltage VBB, it has been difficult to reduce the test time and the test cost of the DRAM.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor memory device capable of controlling a well bias voltage in accordance with an operation mode to improve refresh characteristics. Is to do.

Another object of the present invention is to provide a semiconductor memory device capable of controlling a well bias voltage in a test mode to shorten a test time.

[0015]

FIG. 1 is a diagram illustrating the principle of the present invention. That is, a semiconductor memory device in which an operation mode is set based on a control signal input from the outside is provided with a bias voltage generation circuit. The bias voltage generation circuit is connected to a well in which a memory cell is formed, and generates and supplies a well bias voltage to the well. Further, a bias voltage control signal corresponding to the set operation mode is input to the bias voltage generation circuit, and the bias voltage generation circuit selects one of a plurality of voltage values based on the bias voltage control signal. Then, a well bias voltage having the selected voltage is output.

According to a second aspect of the present invention, in the semiconductor memory device according to the first aspect, a control signal input from the outside is input, and a bias corresponding to the set operation mode is set based on the control signal. A gist of the present invention is that a control signal generation circuit for generating a voltage control signal is provided, and the bias voltage generation circuit is configured to input a bias voltage control signal generated by the control signal generation circuit.

According to a third aspect of the present invention, there is provided the first or second aspect.
5. The semiconductor memory device according to claim 2, wherein the bias voltage generation circuit operates and stops based on an input detection signal, and lowers the well bias voltage during operation. A voltage control signal is input, and a first transistor is connected to each of the plurality of diodes and connected in series in a plurality of stages.
A bias voltage detection circuit for changing the number of stages of the first transistor in response to the bias voltage control signal to change a detection potential, comparing the changed detection potential with the bias voltage, and outputting a comparison result The gist is that the bias voltage generation circuit is configured to input the comparison result output from the bias voltage detection circuit as the detection signal.

The invention described in claim 4 is the first or second invention.
In the semiconductor memory device described in the above, the bias voltage generation circuit, a bias voltage generation circuit that operates based on the supply of drive power supply to lower the well bias voltage,
A first transistor to which the well bias voltage and the bias voltage control signal are input and which are diode-connected to each other and connected in series in a plurality of stages; and wherein the number of the first transistors is changed according to the bias voltage control signal To set the detection potential, and when the well bias voltage reaches the set detection potential, the first of the changed number of stages is set.
And a clamp circuit for supplying a charge from the low potential power supply to the well through the transistor to clamp the well bias voltage so as not to be lower than the detection potential.

The invention described in claim 5 is the invention according to claim 3 or 4
2. The semiconductor memory device according to claim 1, wherein a second transistor is connected in parallel to each of the first transistors, and a control terminal of the second transistor is supplied with the bias voltage control signal. Is turned on and off based on the bias voltage control signal to change the number of stages of the first transistor.

The invention according to claim 6 is the invention according to claims 2 to 5
In the semiconductor memory device according to any one of the above, the control signal generation circuit inputs a row address strobe signal from the outside as the control signal, and the operation mode at that time is active based on the row address strobe signal. A standby mode, and a bias voltage control signal is generated corresponding to both modes so that the well bias voltage is shallow in the standby mode and deep in the active mode. The gist is that they have done so.

The invention according to claim 7 is the invention according to claims 2 to 5
In the semiconductor memory device according to any one of the above, the control signal generation circuit inputs a row address strobe signal and a write control signal from the outside as the control signal, and the operation mode at that time is based on both signals. A standby mode, a write mode, or a read mode is determined, and the bias voltage control is performed so that the well bias voltage is shallow during the standby mode and the write mode, and is deep during the read mode. The gist is to generate a signal.

The invention described in claim 8 is the invention according to claims 2 to 7
In the semiconductor memory device according to any one of the above, a test mode signal is externally input to the control signal generation circuit as the control signal, and the control signal generation circuit is configured to perform a current operation based on the test mode signal. When the operation mode is the test mode, the bias voltage control signal for increasing the well bias voltage and the bias voltage control signal for decreasing the well bias voltage are alternately output. And

(Operation) Therefore, according to the first aspect of the present invention, a bias voltage control signal corresponding to the set operation mode is input to the bias voltage generation circuit. As the well bias voltage, a well bias voltage having one of a plurality of voltage values selected according to the operation mode set based on the bias voltage control signal is supplied to the well. Therefore, the refresh characteristic of the memory cell is a characteristic corresponding to each operation mode.

According to the second aspect of the present invention, a control signal is externally input to the control signal generation circuit, and a bias voltage control signal corresponding to an operation mode set based on the control signal is generated. . Then, the bias voltage generation circuit inputs the bias voltage control signal generated by the control signal generation circuit, and the bias voltage is controlled to a potential corresponding to each operation mode.

According to the third aspect of the present invention, the bias voltage generation circuit includes a bias voltage generation circuit and a bias voltage generation circuit. A detection signal is input to the bias voltage generation circuit, and operation and stop are performed based on the detection signal, and the well bias voltage is reduced during operation. The bias voltage detection circuit is supplied with a well bias voltage and a bias voltage control signal, and includes a first transistor in which a plurality of diodes are connected in series and a plurality of stages are connected in series. The changed detection potential is changed, the changed detection potential is compared with the bias voltage, and the comparison result is output. And
The bias voltage generation circuit receives the comparison result output from the bias voltage detection circuit as a detection signal, and generates and outputs a well bias voltage based on the detection signal.

According to the fourth aspect of the present invention, the bias voltage generation circuit includes a bias voltage generation circuit and a clamp circuit. The bias voltage generation circuit operates based on the supply of the driving power to lower the well bias voltage. The clamp circuit is provided with a first transistor to which a well bias voltage and a bias voltage control signal are input and which is connected in series with a plurality of diodes by diode connection. The clamp circuit sets the detection potential by changing the number of stages of the first transistor in response to the bias voltage control signal, and sets the first number of the changed number of stages when the well bias voltage reaches the set detection potential. Is supplied from a low-potential power supply to the well through the transistor, and the well bias voltage is clamped so as not to be lower than the detection potential.

According to the fifth aspect of the present invention, a second transistor is connected in parallel to each of the first transistors, and a bias voltage control signal is input to a control terminal of the second transistor. Then, each of the second transistors is turned on / off based on the bias voltage control signal, and the number of stages of the first transistor is changed.

According to the invention described in claim 6, a row address strobe signal is externally input to the control signal generation circuit as a control signal, and the operation mode at that time is an active mode or a standby mode based on the row address strobe signal. Is determined. A bias voltage control signal is generated corresponding to both modes so that the well bias voltage is shallow in the standby mode and deep in the active mode.

According to the seventh aspect of the present invention, a row address strobe signal and a write control signal are externally input to the control signal generation circuit as control signals, and the operation mode at that time is a standby mode, One of the write mode and the read mode is determined. Then, the bias voltage control signal is generated so that the well bias voltage is shallow in the standby mode and the write mode, and is deep in the read mode.

According to the eighth aspect of the present invention, a test mode signal is externally input to the control signal generation circuit as a control signal, and the control signal generation circuit changes the operation mode at that time to the test mode based on the test mode signal. In this case, a bias voltage control signal for increasing the well bias voltage and a bias voltage control signal for decreasing the well bias voltage are output alternately. Therefore, in the test mode, the well bias voltage of the well is raised and lowered at predetermined intervals.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. FIG. 2 shows a dynamic random access memory (DRAM: Dynamic Ru
3 is a schematic block circuit diagram of an ndom access memory (21). FIG. The DRAM 21 includes a memory cell array 22, a row decoder 23, a column decoder 24, a control circuit 25, and a bias voltage generation circuit 26. Memory cell array 2
2 comprises a plurality of memory cells C, each of which is connected to an intersection of a plurality of word lines WL and bit lines BL. FIG. 2 shows only one memory cell C connected to the intersection of one word line WL and one bit line BL.

Each word line WL is connected to a row decoder 23, and each bit line BL is connected to a column decoder 24. The row decoder 23 decodes an externally input row address signal RA to select (activate) one word line WL. The column decoder 24 selects (activates) one bit line BL by decoding a column address signal CA input from the outside. Then, the memory cell C connected to the intersection of the selected word line WL and the selected bit line BL is selected, and the selected memory cell C
, Data is written or cell information of the memory cell C is read. The read cell information is rewritten to the selected memory cell C, and the memory cell C
Is refreshed.

A control circuit 25 as a control signal generating circuit has a row address strobe signal (hereinafter simply referred to as a row control signal) RAS and a column address strobe signal (hereinafter simply referred to as a column control signal) as control signals from outside. Bar CAS and write control signal bar W
E is input. The control circuit 25 controls the control signal bar RA
Based on S, CAS, and WE, a control signal for controlling the row decoder 23 and the column decoder 24 is generated and output to each decoder. Each decoder latches and decodes an address signal based on the control signal, and activates the word line WL and the bit line BL.

The control circuit 25 determines an operation mode to be set based on a control signal such as a row control signal / RAS. For example, the control circuit 25 determines a standby mode when the control signal RAS is at an H level and an active mode when the control signal RAS is at an L level based on the row control signal RAS. The active mode is a mode in which data can be written to and read from the memory cell C. Standby mode is D
This is a mode in which the RAM 21 holds the cell information stored in the memory cell C by lowering the operating power supply voltage. By reducing the operating power supply voltage, the power consumption of the DRAM 21 is reduced, so that a mobile phone (not shown) having the DRAM 21 is provided. Reduce equipment battery consumption.

The control circuit 25 generates a plurality of bias voltage control signals Φ according to the determined operation mode at that time.
1 to Φn are generated and output to the bias voltage generation circuit 26. For example, the control circuit 25 sets the bias voltage control signal Φ1 to the H level and the bias signals Φ2 to Φn in the standby mode based on the H level row control signal RAS.
Is set to L level and output. Further, the control circuit 25
In the active mode based on the row control signal / RAS of the level, the bias voltage control signals Φ1 to Φ3 are set to H level, and the bias voltage control signals Φ4 to Φn are set to L level and output.

The bias voltage generation circuit 26 is connected to a well 27 (see FIG. 3) in which the memory cell C is formed, and a predetermined negative well bias voltage VBB is applied to the well 27.
To generate and supply The bias voltage generation circuit 26 selects one of the plurality of voltage values based on the plurality of bias voltage control signals Φ1 to Φn input from the control circuit 25. Then, the bias voltage generation circuit 26 outputs the well bias voltage V having the selected voltage.
Outputs BB. A plurality of bias voltage control signals Φ1 to Φn
Are generated by the control circuit 25 in accordance with the current operation mode in which the DRAM 21 operates. Therefore, the bias voltage generation circuit 26 selects one of the plurality of voltage values according to the operation mode of the DRAM 21, changes the potential of the well bias voltage VBB generated to the selected voltage, and resets the memory cell C. It is supplied to the formed well 27.

For example, when the operation mode of the DRAM 21 is the active mode, the control circuit 25 sets the bias voltage control signals Φ1 to Φ3 to H level and the bias voltage control signals Φ4 to Φn to L level according to the operation mode. Output. The bias voltage generation circuit 26 lowers the well bias voltage VBB based on the input bias voltage control signals Φ1 to Φn and supplies the lower voltage to the well 27.

When the operation mode of the DRAM 21 is the standby mode, the control circuit 25 outputs the bias voltage control signal Φ1 at H level and the bias voltage control signals Φ2 to Φn at L level according to the operation mode. The bias voltage generation circuit 26 generates a well bias voltage VBB based on the input bias voltage control signals Φ1 to Φn.
Is supplied to the well 27 at a higher potential than the well bias voltage VBB in the active mode.

That is, the potential of the well 27 is shallow in the standby mode and deep in the active mode. Then, in the standby mode, since the potential of the well 27 is controlled to be shallow, the leak current from the memory cell C is reduced based on the surrounding environment, as compared with the conventional case where the potential of the well 27 is constantly controlled. That is, the refresh time interval can be lengthened and D
The refresh characteristics of the RAM 21 are improved. And
Since the refresh time interval becomes longer, the DRAM 21
Power consumption in the standby mode is reduced.

In the active mode, since the potential of the well 27 is controlled deeply, the leak current from the memory cell C is reduced depending on the surrounding environment as compared with the conventional case, and the refresh characteristics are improved.

Further, as shown in FIG. 2, a test mode signal TM is externally input to the control circuit 25. The control circuit 25 determines, based on the test mode signal TM, whether the operation mode at that time is a normal mode for reading / writing cell information or a test mode for performing an acceleration test. When the operation mode at that time is the test mode, the control circuit 25 sets the well bias voltage V at every predetermined interval measured by time measuring means such as a counter (not shown).
The levels of the bias voltage control signals Φ1 to Φn are changed and output so as to repeatedly raise and lower BB.

The bias voltage generation circuit receives the bias voltage control signals Φ1 to Φn, and changes between a high detection potential and a low detection potential at predetermined intervals based on the bias voltage control signals Φ1 to Φn. Then, the bias voltage generation circuit repeatedly raises and lowers the well bias voltage VBB based on the changed detection potential.

That is, the well bias voltage VBB is applied by the bias voltage generation circuit 26 mounted on the chip of the DRAM 21.
Can be repeatedly raised and lowered. Therefore, D
There is no need to change the well bias voltage VBB from outside the RAM 21, and the accelerated test of the packaged DRAM 21 can be performed. As a result, the test time of the DRAM 21 is shortened, and the test cost is reduced by shortening the test time.

Next, the configuration of the bias voltage generation circuit 26 will be described. As shown in FIG. 3, the bias voltage generation circuit 2
6 includes a bias voltage detection circuit 27 and a bias voltage generation circuit 28.

The output terminal of the bias voltage generation circuit 28 is connected to the well 27. In the well 27, a memory cell C is formed. Specifically, the memory cell C
Is composed of an N-channel MOS transistor (hereinafter, referred to as an NMOS transistor) 30 and a capacitor 31, and an NMOS transistor 30 is formed in the well 27. The source of the NMOS transistor 30 is connected to the first electrode of the capacitor 31, and the second electrode of the capacitor 31 has a predetermined potential (in this embodiment, the high potential power supply V
cc). The drain of the NMOS transistor 30 is connected to the bit line BL, and the gate is connected to the word line WL.

The bias voltage generating circuit 28 includes, for example, a known oscillation circuit and a charge pump circuit. The detection signal S1 is input from the bias voltage detection circuit 27 to the bias voltage generation circuit 28, and the detection signal S1
1 to operate or stop the oscillation circuit. The oscillating circuit outputs a rectangular wave signal of a predetermined frequency during its operation.
The charge pump circuit supplies charges to the well 27 based on the charge pumping principle based on the rectangular wave signal output from the oscillation circuit. That is, the bias voltage generation circuit 28 operates or stops based on the detection signal, and at the time of the operation, drops the potential (well bias voltage VBB) of the well 27 connected to the output terminal to a negative voltage.

The bias voltage detection circuit 27 has a plurality of bias voltage control signals Φ1 to Φ1 output from the control circuit 25.
Φn is input. The potential of the well 27, that is, the well bias voltage VBB is input to the bias voltage detection circuit 27.

The bias voltage detection circuit 27 detects the potential of the well bias voltage VBB, and outputs the detection result as a detection signal via an inverter circuit. The bias voltage generation circuit 28 operates or operates based on the detection signal. Stop. As a result, the well bias voltage VBB is maintained at the detected voltage.

The bias voltage detection circuit 27 changes the detection potential of the well bias voltage VBB detected based on the input bias voltage control signals Φ1 to Φn, and detects the well bias voltage detected based on the changed detection potential. V
The detection result of BB is output as a detection signal to the bias voltage generation circuit 28 via the inverter circuit. Then, the bias voltage generation circuit 28 operates or stops based on the input detection signal. Therefore, the well bias voltage VBB
Is held at a detection voltage changed based on the bias voltage control signals Φ1 to Φn.

The bias voltage detection circuit 27 includes a P-channel MOS transistor (hereinafter, referred to as a PMOS transistor) TP1 and an NMOS transistor TN1. The node N1 to which the drains of the transistors TP1 and TN1 are connected is connected to the input terminal of the inverter circuit 29, and the output terminal of the inverter circuit 29 is connected to the input terminal of the bias voltage generation circuit. Further, the gates of both transistors TP1 and TN1 are connected to supply a low potential power supply Vss. The high potential power supply Vcc is supplied to the source of the PMOS transistor TP1.
The well bias voltage VBB is supplied to the source of the S transistor TN1 via a plurality of stages of NMOS transistors TNa1 to TNan (n is a natural number).

The NMOS transistors TNa1 to TNan are connected in series. That is, the NMOS transistor TN
The sources of a1 to TNa-1 are NMOS transistors TNa2 to
It is connected to the drain of TNan. In addition, the NMOS transistors TNa1 to TNan are so-called diode-connected, each having its gate and drain connected. The drain of the uppermost NMOS transistor TNa1 is connected to the source of the NMOS transistor TN1. The well bias voltage VBB is supplied to the source of the lower NMOS transistor TNan.

PMOS transistors TPa1 to TPan are connected in parallel to the NMOS transistors TNa1 to TNan, respectively. Each PMOS transistor TPa1-T
Bias voltage control signals Φ1 to Φn are input to the gate of Pan.

Each of the PMOS transistors TPa1-TPan
Are controlled on and off in accordance with the levels of the control signals Φ1 to Φn, respectively. Then, the PMOS transistors TPa1 to TPan that are turned on are connected to the NMOs connected in parallel.
The source and drain of the S transistors TNa1 to TNan are short-circuited (short-circuited).

Therefore, the number (the number of stages) of the PMOS transistors TPa1 to TPan turned off in accordance with the bias voltage control signals Φ1 to Φn is connected in series to the NMOS transistor TN1. . That is, the NMOS transistor TNa1
To TNan are N by bias voltage control signals Φ1 to Φn.
The number of stages connected to MOS transistor TN1 is changed.

Here, based on the bias control signals Φ1 to Φn, the NMOS transistors TN1 have k (0 ≦ k ≦ n) NMOS transistors TNa1 to TNa1 to TN1.
It is assumed that TNak is connected in series. That is, k + 1 NMOS transistors T connected in series are connected to the node N1.
Well bias voltage VBB via N1, TNa1 to TNak
Is supplied.

The well bias voltage VBB drops from the low potential power supply Vss by the operation of the bias voltage generation circuit 28. When the well bias voltage VBB drops to the detection potential determined by the number (the number of stages, k + 1) of the NMOS transistors TN1 and TNa1 to TNak connected in series, the potential of the node N1 becomes L level. The potential of the node N1 is inverted by the inverter circuit 29 and an H level signal is input to the bias voltage generation circuit 28, and the bias voltage generation circuit 28 stops operating based on the H level signal. Therefore, the well bias voltage VBB is
NMOS transistors TN1 and TNa1 to
It calms down and becomes constant at the detection potential determined by the number of TNaks (the number of stages, in this case, k + 1 stages).

The NMOS transistor TN1 has no relation to the bias voltage control signals Φ1 to Φn, ie, N
MOS transistor TN1 is always included. Therefore, the well bias voltage VBB is equal to the bias voltage control signals Φ1 to Φ1.
NMOS transistor TNa1 changed based on Φn
It becomes constant at a potential corresponding to the number of stages of ＴTNan.

As described above, the bias voltage control signal Φ
1 to φn are stored in the DRAM 2 at that time by the control circuit 25.
1 bias voltage control signals Φ1 to Φ in accordance with the operation mode
Generate and output n. For example, the control circuit 25 sets only the bias voltage control signal Φ1 to the H level and sets the other bias voltage control signals Φ2 to Φn to the L level in the standby mode. Then, the H-level bias voltage control signal Φ1
, The PMOS transistor TPa1 is turned off, and the PM transistor TPa1 is turned off based on the L-level bias voltage control signals.
The OS transistors TPa2-TPan are turned on.

As a result, the detection potential of the bias voltage detection circuit 27 is changed to a potential determined by the NMOS transistors TN1 and TNa1. When the well bias voltage reaches the determined detection potential, the node N1 becomes L level, and the bias voltage generation circuit 28 receives the H level detection signal in which the potential of the node N1 is inverted by the inverter circuit 29, and performs an operation. Stop. As a result, the well bias voltage VBB becomes the NMOS transistors TN1 and TNa1.
Is maintained at the potential determined by

On the other hand, the control circuit 25 sets the bias voltage control signals Φ1 to Φ3 to H level in the active mode,
The other bias voltage control signals Φ4 to Φn are set to L level. Then, the H-level bias voltage control signals Φ1 to Φ
3, the PMOS transistors TPa1 to TPa3 are turned off, and the PMOS transistors TPa4 to TPan are turned on based on the L-level bias voltage control signals Φ4 to Φn.

As a result, the detection potential of the bias voltage detection circuit 27 becomes the NMOS transistors TN1, TNa1 to TN
The potential is changed to the potential determined by a3. The changed detection potential is lower than the detection potential changed in the standby mode by the amount of the NMOS transistors TNa2 and TNa3.

When the well bias voltage reaches the determined detection potential, the node N 1 goes to L level, and the bias voltage generation circuit 28 receives the H level detection signal obtained by inverting the potential of the node N 1 by the inverter circuit 29. And stop the operation. As a result, the well bias voltage VBB
Is maintained at a potential determined by the NMOS transistors TN1, TNa1 to TNa3. Then, the well bias voltage VBB kept constant becomes lower (deeper) than in the standby mode.

That is, the well 2 in which the memory cell C is formed
The well bias voltage VBB of 7 is maintained at a potential corresponding to the operation mode of the DRAM 21. As a result, the refresh characteristics correspond to the operation mode, and the refresh characteristics are improved as compared with the conventional case.

As described above, the present embodiment has the following advantages. The control circuit 25 provided in the DRAM 21 performs the following based on the row control signal / RAS.
When the control signal RAS is at the H level, it is determined to be in the standby mode, and when the control signal RAS is at the L level, it is determined to be the active mode. Then, the control circuit 25 outputs the bias voltage control signal Φ1 at the H level and the bias signals Φ2 to Φn at the L level in the standby mode according to the determined operation mode at each time, and outputs the same. In the active mode, the control circuit 25 sets the bias voltage control signals Φ1 to Φ3 to H level, and sets the bias voltage control signals Φ4 to
Φn is set to L level and output. The bias voltage generation circuit 26 changes a plurality of potentials of the well bias voltage VBB to be generated based on the plurality of bias voltage control signals Φ1 to Φn input from the control circuit 25. The plurality of bias voltage control signals Φ1 to Φn are
It is generated according to the current operation mode in which the RAM 21 operates. Therefore, the bias voltage generation circuit 26
One of a plurality of voltage values according to the operation mode of AM21.
One of them is selected, the potential of the well bias voltage VBB generated at the selected voltage is changed, and the voltage is supplied to the well 27 in which the memory cell C is formed. As a result, the well bias voltage V of the well 27 in which the memory cell C is formed
BB is maintained at a potential corresponding to the operation mode of the DRAM 21. Therefore, the refresh characteristics are determined according to the operation mode, and the refresh characteristics can be improved. The control circuit 25 outputs the test mode signal TM input from the outside.
, It is determined whether the operation mode at that time is the normal mode or the test mode. If the operation mode at that time is the test mode, the bias voltage control signal Φ1 is set so that the well bias voltage VBB is repeatedly raised and lowered at predetermined intervals. ~
The level of Φn is changed and output. Based on the bias voltage control signals Φ1 to Φn, the bias voltage control circuit 2
Reference numeral 5 changes the detection potential at predetermined intervals to repeatedly raise and lower the well bias voltage VBB. As a result, the acceleration test for shortening the test time of the DRAM 21 can be performed without changing the well bias voltage VBB from the outside, so that the acceleration test of the packaged DRAM 21 can be performed. Further, the test cost can be reduced by shortening the test time.

The present invention may be carried out in the following modes in addition to the above embodiment. In the above embodiment, the refresh characteristics may be improved by supplying the well 27 with the well bias voltage VBB according to an operation mode other than the standby mode and the active mode.

For example, based on the input write control signal / WE, the control circuit 25 operates in a read mode for reading cell information from the memory cell C or a write mode for writing cell information to the memory cell C. Judge. The control circuit 25 adjusts the bias voltage control signals Φ1 to Φ1 so that the well bias voltage VBB is shallow in the write mode and deep in the read mode in accordance with the determined operation mode.
Change the level of n and output. Based on the bias voltage control signals Φ1 to Φn, the bias voltage generation circuit 26
Changes the detection potential according to the operation mode at that time, so that the well bias voltage VBB is constant at a shallow potential in the write mode, and is constant at the deep potential in the read mode. Control. With this configuration, the well bias voltage VBB is set in accordance with the current operation mode (read mode, write mode).
, The refresh characteristic in each mode can be improved.

The write mode and the read mode are performed when the DRAM 21 is in the active mode. That is, the DRAM 21 has an active mode and a standby mode, and the active mode is further classified into a write mode and a read mode. Therefore, the control circuit 25 controls the bias voltage control signals Φ1 to Φn based on the row selection signal RAS and the write control signal WE.
Generate Then, the bias voltage generation circuit 26 generates the well bias voltage VBB based on the input bias voltage control signals Φ1 to Φn. The well bias voltage VBB supplied to the well 27 in the standby mode and the write mode is shallow, and the read voltage is low. In the mode, the well bias voltage VBB becomes deep. As a result, the refresh time in each mode becomes longer, and the refresh characteristics can be improved.

The control circuit 25 sets the DRA at that time.
M21 state (for example, page mode, EDO, CBR)
And the like, the levels of the bias voltage control signals Φ1 to Φn are changed and output. The bias voltage control signals Φ1-
The bias voltage generation circuit 26 may supply the well bias voltage VBB to the well 27 based on Φn to improve the refresh characteristics.

In the above embodiment, the circuit configuration of the bias voltage generation circuit 26 may be changed as appropriate. For example, the bias voltage generation circuit 51 configured as shown in FIG. The bias voltage generation circuit 51 includes a bias voltage generation circuit 52 and a clamp circuit 53. Bias voltage generation circuit 5
2 operates at all times by the supply of drive power to lower the well bias voltage VBB.

The clamp circuit 53 includes an NMOS transistor TN2 having a drain connected to the low potential power supply Vss, and a plurality (n) of NMs connected in series to the transistor TN2.
OS transistors TNb1 to TNbn and a plurality (n)
PMOS transistors TPb1 to TPbn. NM
The OS transistors TNb1 to TNbn are diode-connected with their gates and drains connected. PMOS transistors TPb1 to TPbn are connected in parallel to the NMOS transistors TNb1 to TNbn, respectively. The bias voltage control signals Φ1 to Φn are input to the gates of the PMOS transistors TPb1 to TPbn, respectively. The level of each of the bias voltage control signals Φ1 to Φn is changed by the control circuit 25 in accordance with the respective operation mode (for example, active mode and standby mode). Therefore, each of the PMOS transistors TPb1 to TPbn is turned on or off according to the operation mode. The NMOS transistor TN2 is connected in series with NMOS transistors TNb1 to TNbn of a number corresponding to the operation mode at each time. When the well bias voltage VBB drops to the detection potential determined by the number of stages of the NMOS transistors TNb1 to TNbn according to the operation mode, the clamp circuit 53 clamps the well bias voltage VBB to the detection potential, that is, the low potential power supply Vss. From the NMOS transistors TN2, TNb1 to TN
A charge is supplied via bn, and the well bias voltage VBB is maintained at a potential according to the operation mode. With this configuration, the refresh characteristics can be improved as in the above embodiment.

[0071]

As described in detail above, according to the first to seventh aspects of the present invention, there is provided a semiconductor memory device capable of controlling a well bias voltage in accordance with an operation mode to improve refresh characteristics. Can be provided.

According to the invention described in claim 8, a semiconductor memory device capable of controlling a well bias voltage in a test mode to shorten a test time can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block circuit diagram of a DRAM of one embodiment.

FIG. 3 is a circuit diagram of a well bias voltage generation circuit according to one embodiment;

FIG. 4 is a circuit diagram of another well bias voltage generation circuit.

FIG. 5 is a circuit diagram of a conventional well bias voltage generation circuit.

FIG. 6 is a circuit diagram of a conventional well bias voltage generation circuit.

[Explanation of symbols]

 11 Bias voltage generation circuit 12 Well Φ1-Φn Control signal VBB Well bias voltage

Claims (8)

[Claims] A bias voltage generation circuit connected to a well in which a memory cell is formed and configured to generate a well bias voltage for the well; and an operation mode set based on a control signal input from the outside. In the semiconductor memory device that operates in response, a bias voltage control signal corresponding to the set operation mode is input to the bias voltage generation circuit, and the bias voltage generation circuit receives a bias voltage control signal based on the bias voltage control signal. A semiconductor memory device which selects one of a plurality of voltage values and outputs the well bias voltage having the selected voltage. 2. The semiconductor memory device according to claim 1, wherein a control signal input from the outside is input, and a bias voltage control signal corresponding to said set operation mode is generated based on said control signal. A semiconductor memory device comprising: a signal generation circuit; wherein the bias voltage generation circuit receives a bias voltage control signal generated by the control signal generation circuit and selects one of the plurality of voltage values. 3. The semiconductor memory device according to claim 1, wherein said bias voltage generation circuit operates and stops based on an input detection signal, and lowers said well bias voltage during operation. A circuit, a first transistor to which the well bias voltage and the bias voltage control signal are input, each of which is diode-connected and a plurality of stages are connected in series, and the number of stages of the first transistor corresponding to the bias voltage control signal And a bias voltage detection circuit for comparing the changed detection potential with the bias voltage and outputting a result of the comparison. The bias voltage generation circuit includes a bias voltage detection circuit. A semiconductor memory device wherein a comparison result output from a circuit is input as the detection signal. 4. The semiconductor memory device according to claim 1, wherein said bias voltage generation circuit operates based on a supply of a drive power supply to lower said well bias voltage; A bias voltage and the bias voltage control signal are input, a plurality of first transistors are diode-connected to each other and connected in series, and the number of stages of the first transistor is changed according to the bias voltage control signal. A detection potential is set, and when the well bias voltage reaches the set detection potential, the first number of the changed stages is set.
And a clamp circuit for supplying a charge from a low-potential power supply to the well through the transistor to clamp the well bias voltage so as not to be lower than a detection potential. 5. The semiconductor memory device according to claim 3, wherein a second transistor is connected in parallel with each of the first transistors, and a control terminal of the second transistor has a bias voltage control signal. Are respectively input, and the second transistors are respectively turned on and off based on the bias voltage control signal to change the number of stages of the first transistor. 6. The semiconductor memory device according to claim 2, wherein said control signal generation circuit inputs a row address strobe signal from outside as said control signal, and Based on the signal, it is determined whether the operation mode at that time is the active mode or the standby mode, and the well bias voltage is shallow in the standby mode and deep in the active mode corresponding to both modes. A semiconductor memory device that generates a bias voltage control signal. 7. The semiconductor memory device according to claim 2, wherein the control signal generation circuit inputs a row address strobe signal and a write control signal from outside as the control signal, Based on both signals, the operation mode at that time is determined to be any one of a standby mode, a write mode, and a read mode. In the standby mode and the write mode, the well bias voltage is shallow, and in the read mode, the well bias voltage is low. A semiconductor memory device that generates the bias voltage control signal so that the voltage is increased. 8. The semiconductor memory device according to claim 2, wherein an external test mode signal is input to said control signal generation circuit as said control signal, and said control signal generation circuit When the operation mode is the test mode based on the test mode signal, the bias voltage control signal for increasing the well bias voltage and the bias voltage control signal for decreasing the well bias voltage A semiconductor memory device that outputs data alternately.