JPH10288976A - Liquid crystal controller and liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal controller constituted so that the flow and the flicker of an intermediate gradation display part is reduced and the number of pins is suppressed from being increased when it is made into an LSI. SOLUTION: This controller is provided with an FRC(frame rate control) processing part 1 producing the plural pieces of display on/off data every pixel according to gradation data and producing the display on/off data of three frames of liquid crystal output data within one frame term of the gradation data, a line memory group 3 for writing the display on/off data of three frames in frame memories 7 and 8 within one frame term of the gradation data and a data-cum-data width conversion part 4. By a data selector-cum-data width conversion part 9, the display on/off data of three frames written in the memories 7 and 8 are successively read out synchronously with the frame cycle of the liquid crystal output data in cooperation with frame memory control parts 5 and 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a simple matrix type liquid crystal display device.

[0002]

2. Description of the Related Art Pixels are arranged at intersections of scanning electrodes and data electrodes which are orthogonal to each other, and the transmittance of the pixels is determined by the difference between the voltage applied to the scanning electrodes and the voltage applied to the data electrodes.
In a liquid crystal display device using a so-called simple matrix display type STN (Super-twisted nematic) system which changes according to a root mean square, a driving frame frequency for obtaining an optimum contrast varies depending on a response time of a liquid crystal material.

In general, when the response time of the liquid crystal material (the time obtained by adding the rise time to display on and the fall time to display off) is 300 ms, the driving frame frequency is 90 to 12
It is said that an optimum contrast is obtained at 0 Hz.

When the response time is 150 ms, the driving frame frequency is 150 Hz, and when the response time is 100 ms, the driving frame frequency is 180 Hz or more.
It is said that optimal contrast can be obtained for each.

[0005] These drive frame frequencies are CRT
(Cathode-ray tube) displays and TFTs (Thin fil
m transistor) The driving frame frequency of the liquid crystal display is higher than 60 to 75 Hz.

Therefore, CRT displays and TFTs
In order to convert a display signal for a liquid crystal display into a display signal for an STN liquid crystal display, the drive frame frequency must be converted using a frame memory for storing display data.

By the way, in the STN liquid crystal display,
Display on / off for each pixel constituting the liquid crystal display
A driving method for giving off binary information (1 bit data) is mainly used.

For this reason, special processing is required to display an STN liquid crystal display at an intermediate gradation. As a method for realizing this processing, a frame rate for displaying an intermediate gray scale is set by setting a period of several frames as one cycle and setting a display ON / OFF ratio of each pixel in the one cycle in a frame cycle unit.・ Control (FRC)
There is a method.

FIG. 29 is a diagram for explaining an example of the halftone processing according to the conventional FRC method.

[0010] In the example shown in FIG.
As a cycle, a pattern consisting of display ON and display OFF (hereinafter, referred to as an FRC pattern) is switched for each frame of a certain size of the display screen in units of one frame period.

In a liquid crystal display device using the STN method, the above-described drive frame frequency conversion processing
An apparatus that realizes the halftone processing by the C method is usually
It is called a liquid crystal controller.

FIGS. 30 and 31 are schematic block diagrams of a conventional liquid crystal controller.

The liquid crystal controller shown in FIG. 30 is of a type which executes an intermediate gradation process prior to a drive frame frequency conversion process.

First, for each of the R, G, and B colors, n bits of gradation data per pixel (normally, 6 bits of data) are received by the input interface 51.

Next, in the gradation processing section 52, in accordance with the received gradation data, intermediate gradation processing by the FRC method is executed to generate 1-bit display on / off data, which is written into the frame memory 53. .

Thereafter, the display ON / OFF data is read out from the frame memory 53 in synchronization with the drive frame frequency of the liquid crystal output display data to convert the frame frequency, and the STN liquid crystal display (not shown) is converted via the liquid crystal output interface 54. ).

On the other hand, the liquid crystal controller shown in FIG.
This is a type in which frame frequency conversion processing is executed prior to halftone processing.

First, the input interface 51 receives n-bit gradation data (normally, 6-bit data) per pixel for each of R, G, and B colors. After that, the gradation data is written into the frame memory 53.

Next, the frame frequency is converted by reading out the gradation data from the frame memory 53 in synchronization with the drive frame frequency of the liquid crystal output display data. The 1-bit display ON / OFF data is generated by executing the halftone processing according to the above.

Then, the data is output to an STN liquid crystal display (not shown) via the liquid crystal output interface 54.

[0021]

The above-mentioned conventional liquid crystal controller shown in FIGS. 30 and 31 has the following problems.

In the conventional liquid crystal controller shown in FIG. 30, the frame frequency of an input signal (usually 60 to 75H
In z), display on / off data is written. Therefore, even if the display ON / OFF data is read from the frame memory 53 at the frame cycle of the liquid crystal output display data,
The switching frequency of the display ON / OFF data (FRC pattern) itself becomes the same as the frame frequency of the input signal.

For example, if the frame frequency of the input signal is 6
0Hz, LCD display data frame frequency is 120Hz
In this case, the display on / off data written to the frame memory 53 at a 60 Hz cycle becomes 2 at a 120 Hz cycle.
It will be read out consecutively. Therefore, the cycle at which the display on / off data is switched to the next data is the frame frequency of the input signal of 60 Hz.

For this reason, the switching of the FRC pattern is visually recognized, and the halftone display portion appears to flow or flicker.

In the conventional liquid crystal controller shown in FIG. 31, since the halftone processing is performed after the drive frame frequency conversion, the switching frequency of the FRC pattern becomes the same as the drive frame frequency output to the STN liquid crystal display. Therefore, the phenomenon that the switching of the FRC pattern is visually recognized and the middle gradation display portion flows or appears to flicker is reduced.

However, in the conventional liquid crystal controller shown in FIG. 31, n-bit gradation data is written in the frame memory 53. For this reason, the capacity of the frame memory 53 must be increased as compared with the case where 1-bit display on / off data is written, and the data width is larger than the case where 1-bit display on / off data is read from the frame memory. Therefore, in order to make the liquid crystal controller an LSI, an expensive package having a large number of pins must be used.

Also, for a so-called dual scan type STN liquid crystal display which divides the display screen into upper and lower parts and simultaneously drives them, a liquid crystal controller for performing intermediate gradation display shown in FIGS. 30 and 31 is used. When the halftone display is performed, the display on / off of the pixels on the lower screen is switched before the display on / off of the pixels on the upper screen at the pixels near the boundary between the upper and lower screens. There is also a problem that the interference fringes of the FRC display may appear to move at the boundary of the screen.

Further, the n-bit gradation data input to the liquid crystal controller shown in FIGS.
When generating from analog display data for a CRT display using a converter, gradation data, especially gradation data of the least significant bit, may fluctuate due to a quantization error of the A / D converter. In this case, for example, when a solid-color display at a certain intermediate gradation rate is performed, FRC patterns of gradation rates before and after the intermediate gradation rate are mixed, and image quality deterioration such as interference fringes and flicker occurs. There is also the problem of doing.

The present invention has been made in view of the above circumstances, and a first object of the present invention is to reduce the flow and flicker of a halftone display portion and to increase the number of pins when an LSI is used. It is an object of the present invention to provide a liquid crystal controller and a liquid crystal display device that can be suppressed.

A second object of the present invention is to provide a liquid crystal controller and a liquid crystal device capable of preventing interference fringes generated when a halftone display is performed on upper and lower screens for a so-called dual scan STN liquid crystal display. A display device is provided.

Further, a third object of the present invention occurs when converting analog display data into digital gradation data when digital gradation data generated from analog display data for a CRT display is used as an input signal. An object of the present invention is to provide a liquid crystal controller and a liquid crystal display element that can suppress the occurrence of image quality deterioration of halftone display due to a quantization error.

[0032]

In order to solve the above-mentioned problems, a first aspect of the present invention is to output to a liquid crystal display for each pixel according to pixel-by-pixel gradation data included in an input signal. A liquid crystal controller that sets a display ON / OFF ratio of the pixel during a plurality of frame periods of the output signal in frame units of the output signal and performs a halftone display of the liquid crystal display, and By generating a plurality of display on / off data for each pixel in accordance with the included pixel unit gradation data, the output signal M (M
> N) generating means for generating display on / off data for frames, and M of the output signal generated by the generating means
Writing control means for writing display on / off data for frames into a frame memory within N frame periods of the input signal; display on / off data for M frames of the output signal written in the frame memory; Reading control means for sequentially reading out each frame in synchronization with the frame period of the output signal.

Here, the gradation data is, for example, a TFT
(Thin Film Transister) Display data for a liquid crystal display.

In the first aspect of the present invention, with the above configuration, the output signal M (M
> N) The display ON / OFF data for the frame is written into the frame memory, and the display ON / OFF for the written M frames is written.
The OFF data is sequentially read out in synchronization with the frame period of the output signal.

By doing so, the data written to the frame memory is not grayscale data but 1-bit display on / off data, so that the data bus width when accessing the frame memory can be reduced. . Therefore, it is possible to suppress an increase in the number of pins when implementing the LSI.

Also, since the frame period of the output signal can be set faster than the frame period of the input signal,
It is possible to reduce the flow and flicker of the halftone display portion.

Further, normally, gradation data is 6 to 8 bits per pixel. On the other hand, the display ON / OFF data is one bit per pixel.

Accordingly, the total number of bits of the data to be stored in the frame memory in units of one frame period of the input signal is as follows: When writing gradation data into the frame memory, the number of pixels constituting one frame × 6 to 8 bits When writing OFF data to the frame memory: The number of pixels constituting one frame × 1 bit × M / N bits.

Therefore, by setting the M / N smaller than 6 to 8, the memory capacity can be reduced as compared with the case where the grayscale data is written in the frame memory.

According to a second aspect of the present invention, the display of the pixel in a plurality of frame periods of the output signal to be output to the liquid crystal display is performed for each pixel in accordance with the gradation data of the pixel included in the input signal. A liquid crystal controller that sets an on / off switching pattern and performs a halftone display of the liquid crystal display, wherein the liquid crystal display is a dual scan liquid crystal display that divides a display screen into upper and lower parts and simultaneously drives the display screen. A first setting unit for setting a display on / off switching pattern of the pixel during a plurality of frame periods of the output signal in accordance with gradation data of a pixel positioned above the display screen included in the input signal; And according to the gradation data about the pixel located on the lower side of the display screen included in the input signal, Second setting means for setting a display on / off switching pattern of the pixel during a plurality of frame periods of the output signal, wherein the second setting means displays a pixel located on a lower side of the display screen. The on / off switching pattern is set to be delayed by one frame of the output signal from the display on / off switching pattern of the pixel located on the upper side of the display screen set by the first setting means. Features.

According to the second aspect of the present invention, with the above-described configuration, the display on / off of the pixels on the lower screen is set to be one unit more than on the upper screen.
It can be output with a frame delay.

Thus, the display ON / OFF of the pixels near the boundary between the upper and lower screens can be set to the same frame, so that it is possible to prevent the interference fringes from appearing to move near the boundary between the upper and lower screens. .

According to a third aspect of the present invention, a plurality of frames of an output signal to be output to a liquid crystal display are provided for each pixel in accordance with pixel-based grayscale data generated by quantizing an analog grayscale signal. A liquid crystal controller that sets a display on / off switching pattern of the pixel during a cycle and performs an intermediate gradation display of the liquid crystal display, wherein the display on / off switching pattern has an adjacent value for each pixel. The data corresponding to the gray scale data to be displayed is set in advance so that the frames for which the display is turned on or the display is turned off are made substantially common.

Here, the analog gradation signal is, for example, display data for a CRT (Cathord Ray Turbe).

According to the third aspect of the present invention, with the above-described configuration, for the display ON / OFF data for one frame of the output signal, the switching of the display ON / OFF of each pixel due to the fluctuation of the value of the gradation data is performed. A pixel whose display is on,
This can be performed smoothly without extremely changing the arrangement relationship with the pixels whose display is turned off.

Thus, when digital grayscale data generated from analog grayscale signals such as analog display data for a CRT display is used as an input signal, a quantum generated when the analog grayscale signal is converted into digital grayscale data. It is possible to suppress the deterioration of the image quality of the halftone display due to the conversion error.

[0047]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of the present invention will be described.

FIG. 1 is a schematic block diagram of a liquid crystal controller according to a first embodiment of the present invention.

The liquid crystal controller shown in FIG. 1 arranges pixels at intersections of scanning electrodes and data electrodes which are orthogonal to each other.
A liquid crystal display of a simple matrix display type in which the transmittance of the pixel is changed in accordance with a root mean square of a difference between voltages applied to a scanning electrode and a data electrode, and the display screen is vertically divided and driven simultaneously. This is for a so-called dual scan type STN liquid crystal display. The resolution of the display screen is a so-called X of 1024 × 768 dots.
GA.

In FIG. 1, reference numeral 1 denotes an FRC processing unit for performing FRC halftone processing, reference numerals 2 and 12 denote data width conversion units, reference numerals 3 and 10 denote line memory groups, and reference numerals 4 and 9 denote data selectors. Data width converters, 5 and 6 are frame memory read / write controllers, 7 and 8 are frame memories for driving frame frequency conversion, 11 is a data selector, 13 and 14 are line memory read / write controllers. , And reference numeral 15 denotes a synchronization signal generator.

In FIG. 1, RA and RB are 6-bit R (red) gradation data per pixel, and GA and GB are 1 bit.
G (green) gradation data of 6 bits per pixel and B
A and BB are B (blue) gradation data of 6 bits per pixel. Here, it is assumed that RA, GA, and BA are gradation data of each color for odd-numbered pixels, and RB, GB, and BB are gradation data of each color for even-numbered pixels.

DotCK is a synchronization signal synchronized with the grayscale data, Hsync is a horizontal synchronization signal indicating switching of a horizontal period, Vsync is a vertical synchronization signal (frame period signal) indicating switching of a vertical (frame) period, DispTMG.
Is a signal indicating an effective display period.

OA is 12-bit parallel liquid crystal display data corresponding to the upper screen of the STN liquid crystal display, and OB is 12-bit parallel liquid crystal display data corresponding to the lower screen.

CL2 is a synchronization signal synchronized with the liquid crystal display data, CL1 is a horizontal synchronization signal indicating switching of a horizontal period,
FLM is a frame period signal (vertical synchronization signal) indicating switching of a frame period (vertical period).

In this embodiment, the frequency of the frame period signal FLM output to the STN liquid crystal display is set to 2.5 times the frequency of the frame period signal Vsync of the input signal. Therefore, five frame periods of the output signal are completed in two frame periods of the input signal.

Therefore, in the present embodiment, access control to the memory frames 7 and 8 is performed in units of two frame periods of the input signal.

Next, each part shown in FIG. 1 will be described in detail.

First, the synchronizing signal generator 15 will be described.

The synchronization signal generator 15 generates FLM, CL1, CL2, and other control signals (for example, a read / write clock) based on DotCK, Hsync, Vsync, and DispTMG input to the liquid crystal controller.

Here, DotCK, Hsync, Vsync, Disp.TM.
For the timing of G, for example, a signal according to the signal described in Hitachi LCD Controller / Driver LSI Data Book, page 1001, published by Hitachi, Ltd. as shown in FIG. 26 can be used.

Further, C generated by the synchronization signal generation unit 15
The timings of L2, CL1, and FLM are, for example, as shown in FIG.
7 and FIG.
A signal conforming to the CL2, CL1, and FLM signals described on page 8 can be used.

Next, the FRC processing section 1 will be described.

The FRC processing section 1 performs the gradation data RA, RB, GA, GB, BA, B input to the liquid crystal controller.
For each of B, three types of display on / off data are generated per pixel. As a result, display on / off data for three frames, that is, three FRC patterns are generated from the gradation data for one frame.

The FRC processing section 1 outputs each gradation data (RA,
An FRC processing circuit is provided for each of RB, GA, GB, BA, and BB.

The FRC processing circuit generates three types of display on / off data per pixel for the corresponding gradation data.

FIG. 2 is a schematic block diagram of the FRC processing circuit 101.

Here, reference numerals 101 to 104 denote FRC decoders, reference numeral 105 denotes a Vsync counter, and reference numeral 106 denotes a write data selector.

The Vsync counter 105 counts Vsync and outputs a 2-bit Vsync count value.
Therefore, the possible value of the Vsync count value is 0 to
3.

The FRC decoders 101 to 104 generate display on / off data corresponding to the input gradation data of a certain pixel.

FIG. 3 is a schematic block diagram of the FRC decoders 101 to 104.

The FRC decoders 101 to 104 generate FRC pattern generators for generating display on / off data for generating 64 types of FRC patterns corresponding to the number of bits (6 bits) of gradation data per pixel. 107
And according to the value of the input gradation data of a certain pixel,
A selector 108 for selecting one of the 64 types of display on / off data generated by the FRC pattern generator 107.

Here, the relationship between the display on / off data output from each of the FRC decoders 101 to 104 will be described.

FIG. 4 is a timing chart for explaining display on / off data output from the FRC decoders 101 to 104 and read / write control of the frame memories 7 and 8.

Here, the FRC processing data A is display on / off data output from the FRC decoder 101, and F
The RC processing data B is display on / off data output from the FRC decoder 102, and the FRC processing data C is F
The display ON / OFF data output from the RC decoder 103 and the FRC processing data D are the FRC decoder 10
4 shows the display on / off data output from FIG.
Further, D-FN (N is an integer) means display on / off data constituting an FRC pattern to be output in the Nth frame.

As shown in FIG. 4, FRC decoder 101
If the display on / off data generated in step (1) constitutes an FRC pattern to be output in the Nth frame, the FRC decoder 102 performs display on / off for forming an FRC pattern to be output in the (N + 1) th frame.・
The OFF data, the FRC decoder 103 supplies display ON / OFF data for forming an FRC pattern to be output in the (N + 2) th frame, and the FRC decoder 104
Generates display on / off data for forming an FRC pattern to be output in the (N + 3) th frame.

Each of the FRC decoders 101 to 104
Is Vsync output from the Vsync counter 105
Every time the c count value is incremented by one, display on / off data forming an FRC pattern to be output in a frame two frames ahead is generated, and Vs
Each time the sync count value is reset, ie, Vs
Each time the nc count value switches from “3” to “0”, display on / off data forming an FRC pattern to be output in a frame four frames ahead is generated.

In this embodiment, the number of FRC patterns equal to the number of frames (Vsync) included in one cycle of the FRC processing (hereinafter, this cycle is also referred to as FRC cycle) is generated.

For example, if the number of frames included in the FRC cycle is 10, the FRC decoders 101 to 104 may be set in the following manner.

Each of the 64 types of gradation pattern generators corresponding to the number of gradation data bits provided in the FRC pattern generator 107 of the FRC decoder 101 is specified by Vsync, Hsync, and Dotck input to the FRC decoder 101. Of the pixels included in the FRC cycle, the first (Vsync count value = 0), the third (Vsync count value = 1), the fifth (Vsync count value = 2), and the seventh (Vs
F to be output in the frame of the value of the sync count value = 3)
The display on / off data for configuring the RC pattern is set to be generated according to the Vsync count value.

Each of the 64 types of gradation pattern generators provided in the FRC pattern generator 107 of the FRC decoder 102 corresponding to the number of gradation data bits is specified by Vsync, Hsync, and Dotck input to the FRC decoder 101. Out of the frames included in the FRC cycle, the second (Vsync count value = 0), the fourth (Vsync count value = 1), the sixth (Vsync count value = 2), and the eighth (Vs
F to be output in the frame of the value of the sync count value = 3)
The display on / off data for configuring the RC pattern is set to be generated according to the Vsync count value.

Each of the 64 types of gradation pattern generators provided in the FRC pattern generator 107 of the FRC decoder 103 corresponding to the number of gradation data bits is specified by Vsync, Hsync, and Dotck input to the FRC decoder 101. Out of the frames included in the FRC cycle, the third (Vsync count value = 0), the fifth (Vsync count value = 1), the seventh (Vsync count value = 2), and the ninth (Vs count)
F to be output in the frame of the value of the sync count value = 3)
The display on / off data for configuring the RC pattern is set to be generated according to the Vsync count value.

Each of the 64 types of gradation pattern generators provided in the FRC pattern generator 107 of the FRC decoder 104 corresponding to the number of gradation data bits is specified by Vsync, Hsync, and Dotck input to the FRC decoder 101. Out of the frames included in the FRC cycle, the fourth (Vsync count value = 0), the sixth (Vsync count value = 1), the eighth (Vsync count value = 2), and the tenth (Vsync count value)
Display on / off data for forming an FRC pattern to be output in the frame of (sync count value = 3) is set to be generated according to the Vsync count value.

In order to explain the relation between the display on / off data output from the FRC decoders 101 to 104 more clearly, the matrix shown in FIG. Consider a case where an FRC pattern is obtained.

Here, P-FN indicates an FRC pattern to be output in the N-th frame.

The FRC pattern shown in FIG.
A frame is defined as one FRC cycle, and FR
The configuration is such that the C pattern is switched. Therefore, the FRC patterns shown in PF11 to PF16 are
The FRC patterns shown by P-F1 to P-F6 are the same.

In this case, each of the decoders 101 to 104
What is necessary is just to set for each input pixel to generate the display on / off data for forming the FRC pattern as shown in FIG.

Here, the FRC pattern A is an FRC pattern constituted by display on / off data output from the FRC decoder 101, and the FRC pattern B is F
The FRC pattern composed of the display ON / OFF data output from the RC decoder 102 and the FRC pattern C are the display ON / OFF output from the FRC decoder 103.
The FRC pattern output by the OFF data and the FRC pattern D indicate the FRC pattern formed by the display ON / OFF data output from the FRC decoder 104.

Returning to FIG. 2, the description will be continued.

The write data selector 106 outputs Vsyn
According to the Vsync count value output from the c counter 105, the display ON / OFF data that configures each of the three FRC patterns from the display ON / OFF data that configures the four FRC patterns output from the FRC decoders 101 to 104, respectively. Select off data.

Specifically, as shown in FIG.
If the c count value is an even number (“0” or “2”), F
Display on / off data output from the RC decoder 101 (this data constitutes the first FRC pattern (1st)), display on / off data output from the FRC decoder 102 (this data is the second F
RC pattern (2nd)), FR
The display on / off data output from the C decoder 103 (this data constitutes the third FRC pattern (3rd)) is selected.

On the other hand, when the Vsync count value is an odd number (“1” or “3”), the FRC decoder 102
Display on / off data output from
The fourth FRC pattern (4th)), the display ON / OFF signal outputted from the FRC decoder 103.
OFF data (this data is the fifth FRC pattern (5
th)), the FRC decoder 104
Display on / off data output from
Of the FRC pattern (6th).

As described above, in the FRC processing section 1 of the present embodiment, the FRC processing circuit shown in FIG. 2 is used for each gradation data (RA, RB, GA, GB, BA, BB) inputted to the liquid crystal controller. Is provided.

Therefore, the FRC processing unit 1 calculates the gradation data RA, RB, GA, GB, BA, BB
Display on / off data for three frames (1st, 2nd, 3rd, or 4t) from gradation data for one frame
h, 5th, 6th), that is, three FRC patterns can be generated.

That is, within one frame period, the display on / off data constituting each of the three types of FRC patterns is output in 2-bit parallel for each of the R, G, and B colors.

Next, the display data width converter 2 will be described.

The display data width conversion unit 2 outputs three types of display on / off data (1st, 2nd, and 3rd) output from the FRC processing unit 1 in 2-bit parallel for each of R, G, and B colors.
3rd or 4th, 5th, 6th) to 16
Convert to bit parallel display on / off data.

FIG. 7 is a timing chart for explaining the processing in the display data width converter 2 shown in FIG.

Here, PRA is display on / off data corresponding to gradation data RA, PRB is display on / off data corresponding to gradation data RB, and PGA is gradation data GA.
, PGB is display on / off data corresponding to gradation data GB, PBA is display on / off data corresponding to gradation data BA, and P
BB is display on / off data corresponding to the gradation data BB.

RN, GN, BN (N is an integer)
This indicates that the data is display on / off data corresponding to the gradation data of the Nth pixel.

In FIG. 7, for the sake of simplicity, three types of display on / off data (1st, 2nd, and 3rd) output in 2-bit parallel for each of R, G, and B colors are shown.
3rd or 4th, 5th, and 6th), only processing of one type of display on / off data is shown.

As shown in FIG. 7, the display data width conversion unit 2 converts the display on / off data of each color output from the FRC processing unit 1 into R0, G0, B0, R1, G1, B1, R1, and R2.
The rearrangement is performed in the order of pixels, such as 2,... So that the order of each color in the pixels is R, G, and B. Then, a plurality of data (here, 16 data) are output in parallel.

Note that such processing can be realized by, for example, using a plurality of buffers and controlling writing and reading of display on / off data to and from the buffers.

Next, the line memory group 3 and the line memory read / write control unit 13 will be described.

As shown in FIG. 1, the line memory group 3
A plurality of line memories having a 16-bit bus width are connected in parallel.

Line memory read / write control unit 13
Are the three types of 1s output from the display data width conversion unit 2.
6-bit parallel display on / off data (1st, 2nd
nd, 3rd or 4th, 5th, 6th) are sequentially written for two lines each, and read out after 2Hsync.

At this time, control is performed so that the read clock from the line memory is faster than the write clock to the line memory.

Next, the data selector / data width converter 4
Will be described.

FIG. 8 shows a data selector / data width converter 4.
9 and 10 are timing charts for explaining the display ON / OFF data output bus width conversion processing in FIG. 9 and FIG. 9 for explaining the display ON / OFF data order rearrangement processing in the data selector / data width conversion unit 4. It is a timing chart.

As shown in FIG. 8, the data selector / data width converter 4 reads the 1
The 6-bit parallel display on / off data is converted to 8-bit parallel display on / off data.

In the present embodiment, as described above, the line memory read / write control unit 13 determines that the read clock for display on / off data from the line memory group 3 is higher than the write clock for the line memory group 3. Is also controlled to be faster.

As a result, as shown in FIG. 8, the transfer speed of the display on / off data whose data width has been converted by the data selector / data width conversion unit 4 is changed according to the display on / off data input to the line memory group 3. It is designed to be 4/3 times the transfer speed.

In FIG. 8, for the sake of simplicity, three types of display on / off data (1st, 2nd, and 3rd) read from the line memory group 3 in units of two lines are shown.
3rd or 4th, 5th, 6th) shows only one type of display ON / OFF data.

The data selector / data width converter 4
Is a line memory group 3 as shown in FIGS.
Are read in units of two lines, and thereafter, three types of display on / off data (1st, 2nd, 3rd or 4th, 5t) whose data width is converted into 8-bit parallel data
h, 6th), and converts the data into display on / off data 1st-L for even lines and display on / off data 2nd-L for odd lines. Then, output is performed in the next 2Hsync period.

Here, FIG. 9 shows the line memories 3 to 2
The case where three types of display on / off data read in line units are 1st, 2nd, and 3rd is shown, and these data are the display on / off data 1st-L of the even line and the odd number. An example is shown in which the data is converted into the display on / off data 2nd-L of the line and is output in the next 2Hsync period.

FIG. 10 shows that the line memories 3 to 2
The three types of display on / off data read in line units are 4th, 5th and 6th, and these data are the display on / off data 1st-L of the even line and the odd number. An example is shown in which the data is converted into the display on / off data 2nd-L of the line and is output in the next 2Hsync period.

As shown in FIGS. 9 and 10, the transfer rates of the display on / off data 1st-L and 2nd-L output from the data selector / data width converter 4 are input to the line memory group 3. The transfer speed of the display ON / OFF data to be displayed is 3/2 times the transfer speed.

That is, the transfer speed 4 of the display ON / OFF data whose data width has been converted with respect to the transfer speed of the display ON / OFF data input to the line memory group 3 shown in FIG.
/ 3 times faster.

The reason is that it is assumed that there is a so-called horizontal blanking period which is a period other than the transfer period of the input valid display data.

For example, a so-called XG display having a resolution of 1024 × 768 dots on a display screen of an STN liquid crystal display.
When A is used, the input signal has a horizontal retrace period of 64 dots.
CK or more is set so that data to be written to the frame memories 7 and 8 does not have a horizontal blanking period.

In this case, (512 + the number of dots in the horizontal blanking period 64) × 2Hsyn
The relational expression of c × 4/3 ≧ 512 × 3Hsync holds.

Here, 512 is a value obtained by dividing the number 1024 of DotCKs in the 1 Hsync period by the number of bits 2 of the display ON / OFF data. 4/3 indicates the ratio 4/3 of the transfer speed of the display ON / OFF data input to the line memory group 3 to the transfer speed of the display ON / OFF data whose data width has been converted.

From the above relational expression, 3 is obtained in the 2Hsync period.
It can be seen that the display on / off data for the line can be read.

Next, the frame memory read / write control units 5 and 6 will be described.

The frame memory read / write control unit 5,
Reference numeral 6 alternately switches read / write operations to the frame memory 7 and the frame memory 8 every 2 Vsync.

More specifically, as shown in FIG.
When the c count value is “0” or “1”, the frame memory 7 is controlled to be in the write state and the frame memory 8 is in the read state, and when the Vsync count value is “2” or “3”, , The frame memory 7 is in the read state, and the frame memory 8 is in the write state.

As described above, as shown in FIGS. 9 and 10, the data selector and data width converter 4 performs three types of 8-bit parallel display on / off data (1st,
2nd, 3rd or 4th, 5th, 6th) are rearranged and converted into display on / off data 1st-L for even-numbered lines and display on / off data 2nd-L for odd-numbered lines. In the 2Hsync period.

Therefore, when the Vsync count value is "0" or "1" in frame 7, and when the Vsync count value is "0" or "1" in frame 8, the even-numbered line 8 bit parallel display on / off data 1st-L and odd 8th line
Bit parallel display ON / OFF data 2nd-L (total 16-bit parallel display ON / OFF data) will be written.

As a result, 2 Vs
Display on / off data for six frames is written in the sync period.

Here, FIG. 11 shows frame memories 7 and 8
2 shows an example of a storage location of display on / off data in the example.

As described above, this embodiment assumes that the liquid crystal controller is for a so-called dual scan type STN liquid crystal display that divides the screen vertically and drives the screen simultaneously.

Therefore, in the example shown in FIG. 11, the display on / off data of the pixels constituting the screen are stored in the frame memories 7 and 8 separately for the upper screen and the lower screen. .

The display on / off data is stored in frame units for each of the upper and lower screens.
In FIG. 11, for example, 1st indicates a display on / off data group forming the first frame, and 2nd indicates a display on / off data group forming the second frame.

[0133] Such allocation of the storage locations of the frame memories 7 and 8 can be realized by referring to Vsync and Hsync.

As the frame memories 7 and 8, for example, HM52216165 manufactured by Hitachi, Ltd. (described in pages 953 to 1000 of an IC memory data book issued by Hitachi, Ltd.) can be used.

Next, the data selector / data width converter 9
Will be described.

The data selector / data width converter 9 can transfer the display on / off data at a transfer rate that is 4/5 times the transfer rate when the display on / off data is written to the frame memories 7 and 8. In this way, the read timing of the display on / off data from the frame memories 7 and 8 is adjusted.

FIG. 12 is a timing chart showing the display on / off data read timing from the frame memories 7 and 8 using the write clock and the read clock for the frame memories 7 and 8 as a time axis.

Actually, two lines (1 line) are simultaneously outputted from each of the frame memories 7 and 8 every 2 Vsync periods.
The display ON / OFF data (line is 8-bit parallel) is alternately read out. Here, for the sake of simplicity,
Only the timing is shown for the display on / off data for one line.

The data selector / data width converter 9
Reads the display on / off data on the upper screen side and the display on / off data on the lower screen side alternately for two lines from frames 7 and 8.

FIG. 13 is a timing chart showing the display on / off data read timing from either one of the frame memories 7 and 8, using Hsync and CL1 as a time axis. Here, N + 384. The line after LINE indicates display on / off data of the line on the lower screen side.

As described above, the data 7 and 8 are supplied with 2 Vs by the data selector / data width converter 4.
The display ON / OFF data for six frames is written in the sync period, but the display ON / OFF data read out by the data selector / data width converter 9 in the next 2Vsync period. The OFF data corresponds to five frames according to the timing chart shown in FIG.

Specifically, as shown in FIG.
When the c count value is “0” or “1”, display on / off data of the frame is read from the frame memory 8 in the order of 2nd, 3rd, 4th, 5th, and 6th. When the Vsync count value is “2” or “3”, the first, second, third, and third frames are read from the frame memory 7.
The display on / off data of the frame is read in the order of 4th and 5th.

Here, as shown in FIG. 13, the horizontal period Hsync of the input signal and the horizontal period CL1 of the liquid crystal output data are set.
Is 5CL1 for 4Hsync. This is, as shown in FIG.
8, the transfer rate of the display on / off data read from
Transfer speed when the display on / off data is written to the frame memories 7 and 8 (for 6 frames at 2 Vsync)
As a result, the driving frame frequency FLM of the liquid crystal output data is equal to the driving frame frequency Vsync × 5/4 × 2 of the input signal.
(Upper and lower two screen driving) = 2.5 Vsync. Therefore, the driving frame frequency output to the STN liquid crystal display is 2.5 times the driving frame frequency of the input signal.

Further, the data selector / data width converter 9 reads the display on / off data on the upper screen side and the display on / off data on the lower screen side alternately by reading two lines from the frames 7 and 8 respectively. , The data width is 8
Conversion from bit parallel to 16-bit parallel.

In FIG. 1, the 16-bit parallel display ON / OFF data corresponding to the display ON / OFF data on the upper screen and the display ON / OFF data on the lower screen read from the frame 7 are shown.
The off data is indicated by 1st-L ', and the 16-bit parallel display on / off data corresponding to the display on / off data on the upper screen and the display on / off data on the lower screen read from frame 8 is indicated by 2nd-L'. ing.

Next, the line memory group 10 and the line memory read / write control unit 14 will be described.

As shown in FIG. 1, the line memory group 10 includes line memories A to D having a 16-bit bus width.

Line memory read / write controller 14
Is the 16-bit parallel display on / off data 1st-L output from the data selector / data width converter 9
′ And 2nd-L ′ are controlled.

The data selector / data width converter 9
Of the 16-bit parallel display on / off data 1st-L 'and 2nd-L' output from the display memory, the display on / off data corresponding to the predetermined line is output to the data selector 11 through the line memory group 10. .

FIG. 14 is a timing chart showing the timing of the process of writing and reading display on / off data to and from the line memory group 10 and the timing of display on / off data output to the data selector 11.

As shown in FIG. 14, the data selector / data width converter 9 outputs a 16-bit parallel display signal.
Two lines of off data are output alternately on the upper screen side and the lower screen side.

Line memory read / write controller 14
Controls the writing and reading of two lines of 16-bit parallel display on / off data sequentially output from the data selector / data width converter 9 to the output terminal a of the line memory group 10 E, the display on / off data of the line on the upper screen and the display on / off data of the line corresponding to the line on the upper screen on the lower screen are output simultaneously. .

The above process will be specifically described with reference to FIG.

First, the display on / off data 1-Li of the first line, which is the display on / off data on the upper screen, simultaneously sent from the data selector / data width converter 9
ne, display on / off data of the second line 2-Lin
e is written to the line memories A and B, respectively.

Next, the display on / off data 38 of the 385th line, which is the display on / off data on the lower screen side, simultaneously sent from the data selector / data width converter 9
The 5-Line and the display on / off data 386-Line of the 386th line are output from the output terminal e through the 385-Line, and 386-
Line is written to the line memory C.

Also, in synchronization with the output from the output terminal e of the 385-Line, the 1-
Line is read and output from the output terminal a.

Next, the display on / off data 3-Li of the third line, which is the display on / off data on the upper screen, simultaneously sent from the data selector / data width converter 9
ne, display on / off data of the fourth line 4-Lin
e is written to the line memories A and D, respectively.

At the same time, the 2-Line written in the line memory B and the 386 written in the line memory C
Line is read out and output from output terminals b and c simultaneously.

By repeating the same processing as above, the display on / off data of the line on the upper screen and the display on / off data of the line on the lower screen are output simultaneously.

Next, the data selector 11 will be described.

As shown in FIG. 1, the data selector 11 selects one of the output terminals a to e of the line memory group 10.
Of the display on / off data of the line on the upper screen and the display on / off data of the line on the lower screen, which are output simultaneously from the
And the line on the lower screen side is controlled to be output from the output terminal g.

Next, the data width converter 12 will be described.

The data width converter 12 is provided with the data selector 1
For each of the display on / off data of the line on the upper screen side and the display on / off data of the line on the lower screen side output from 1, the data width is converted into 12-bit parallel for STN liquid crystal display.

The upper and lower screen 12-bit parallel data (24 bits in total) are output to an STN liquid crystal display (not shown) together with CL1, CL2 and FLM generated by the synchronizing signal generator 15.

In the first embodiment of the present invention, one of the input signals
Within the frame period, display on / off data for three frames of the output signal is written into the frame memories 7 and 8, and the written display on / off data for three frames are sequentially synchronized with the frame period FLM of the output signal. Reading.

By doing so, the data written to the frame memories 7 and 8 becomes 1-bit display on / off data on which the FRC processing has been performed. Memory 1
The number can be reduced to 16 per unit.

Further, by sequentially writing display on / off data for three frames within one frame period of the input signal, the FRC is output every frame cycle FLM of the output signal output at 2.5 times the input frame frequency. You can switch patterns.

Therefore, it is possible to reduce the flow of the halftone display portion, which is the object of the present invention, and to suppress an increase in the number of pins when implementing an LSI.

Further, the total number of bits of the data stored in the frame memories 7 and 8 is 1 frame number × 3 frames × 1 bit in units of one frame period of the input signal.

On the other hand, when 6-bit grayscale data is written directly into the frame memory, the total number of bits of data to be input to the frame memory within one frame period of the input signal is the number of pixels constituting one frame. × 6 bits.

Therefore, the memory capacity can be reduced as compared with the case where the gradation data is directly written in the frame memory.

Next, a second embodiment of the present invention will be described.

FIG. 15 is a schematic block diagram of a liquid crystal controller according to a second embodiment of the present invention.

The liquid crystal controller shown in FIG. 15 is similar to the liquid crystal controller of the first embodiment shown in FIG.
It is for N liquid crystal displays. The resolution of the display screen is so-called XGA of 1024 × 768 dots.

In FIG. 15, reference numeral 1a denotes an FRC processing unit for performing FRC halftone processing, reference numerals 5a and 6a denote frame memory read / write control units, and reference numeral 9a denotes a data selector and data width conversion unit.

Since the other configuration is the same as that of the first embodiment shown in FIG. 1, the detailed description thereof will be omitted by attaching the same reference numerals.

In the liquid crystal controller according to the first embodiment shown in FIG. 1, the driving frame frequency FLM of the liquid crystal output data is
Although the frame frequency Vsync of the input signal (grayscale data) is set to 2.5 times, the liquid crystal controller of the present embodiment shown in FIG.
LM is the frame frequency Vs of the input signal (gradation data)
The value is three times as large as that of the signal “ync.

Therefore, one frame period of the input signal completes three frame periods of the output signal.

Thus, in the present embodiment, access control to the memory frames 7 and 8 is performed in units of one frame period of the input signal.

Next, the configuration of this embodiment different from the liquid crystal controller of the first embodiment shown in FIG. 1 will be described in detail.

First, the FRC processing section 1a will be described.

The FRC processing section 1a performs the gradation data RA, RB, GA, GB, BA,
For each BB, three types of display on / off data are generated per pixel. As a result, display on / off data for three frames, that is, three FRC patterns are generated from the gradation data for one frame.

The FRC processing section 1a outputs each gradation data (R
A, RB, GA, GB, BA, BB) are provided with FRC processing circuits.

The FRC processing circuit generates three types of display on / off data per pixel for the corresponding gradation data.

FIG. 16 is a schematic block diagram of the FRC processing circuit.

Here, reference numerals 101a to 103a denote FRCs.
A decoder 105a is a Vsync counter.

The Vsync counter 105a outputs Vsync
And outputs a 1-bit Vsync count value. Therefore, the possible value of the Vsync count value is 0 to 1.

The FRC decoders 101a to 103a generate display on / off data corresponding to the input gradation data of a certain pixel in accordance with the value of the gradation data.

FIG. 17 shows the FRC decoders 101a to 101c.
It is a schematic block diagram of a.

FRC decoders 101 to 103a are FRC pattern generators for generating display on / off data for generating 64 types of FRC patterns corresponding to the number of bits (6 bits) of gradation data per pixel. 10
7a and a selector 108a for selecting one of 64 types of display on / off data generated by the FRC pattern generator 107a in accordance with the value of the input gradation data of a certain pixel.

Here, FRC decoders 101a-101
a The relationship between the display on / off data output by each of them will be described.

FIG. 18 shows the FRC decoders 101a to 101a to 101c.
FIG. 9 is a timing chart for explaining display on / off data output from 3a and read / write control of frame memories 7 and 8;

Here, the FRC processing data A is display on / off data output from the FRC decoder 101a,
The FRC processing data B indicates display on / off data output from the FRC decoder 102a, and the FRC processing data C indicates display on / off data output from the FRC decoder 103a. Further, D-FN (N is an integer) means display on / off data constituting an FRC pattern to be output in the Nth frame.

As shown in FIG. 18, FRC decoder 10
Assuming that the display on / off data generated in 1a constitutes an FRC pattern to be output in the Nth frame, the FRC decoder 102a performs display for forming an FRC pattern to be output in the (N + 1) th frame. ON / OFF data and the FRC decoder 103a
Generates display on / off data for forming an FRC pattern to be output in the (N + 2) th frame.

Further, each FRC decoder 101a-103
a is Vs output from the Vsync counter 105a.
Every time the nc count value changes, display on / off data constituting an FRC pattern to be output in a frame three frames ahead is generated.

As described above, in the FRC processing section 1a of the present embodiment, each gradation data (RA, RB, GA, GB, BA, BB) inputted to the liquid crystal controller is processed as shown in FIG.
6 is provided.

Therefore, the FRC processing section 1a performs display on / off data for three frames, ie, three FRCs, from one frame of gray data for each of the gray data RA, RB, GA, GB, BA, and BB. Patterns can be generated.

That is, within one frame period, the display on / off data constituting each of the three types of FRC patterns is output in 2-bit parallel for each of the R, G, and B colors.

Next, the frame memory read / write control units 5a and 6a will be described.

Frame memory read / write controller 5
a and 6a are a frame memory 7 and a frame memory 8
Read / write operation is alternately switched every 1 Vsync.

Specifically, as shown in FIG.
When the nc count value is “0”, control is performed so that the frame memory 7 is in the write state and the frame memory 8 is in the read state. When the Vsync count value is “1”, the frame memory 7 is in the read state. Control is performed so that the frame memory 8 enters the write state.

Next, the data selector / data width converter 9
a will be described.

The data selector / data width converter 9a is
The display on / off data is transferred from the frame memories 7 and 8 so that the display on / off data can be transferred at the same transfer rate as when the display on / off data is written to the frame memories 7 and 8. Adjust the read timing.

FIG. 19 is a timing chart showing the display on / off data read timing from the frame memories 7 and 8 using the write clock and the read clock for the frame memories 7 and 8 as a time axis.

Actually, two lines (1) are simultaneously output from each of the frame memories 7 and 8 every 2 Vsync periods.
The display ON / OFF data (line is 8-bit parallel) is alternately read out. Here, for the sake of simplicity,
Only the timing is shown for the display on / off data for one line.

The data selector / data width converter 9
In a, the display on / off data on the upper screen and the display on / off data on the lower screen are alternately read from the frames 7 and 8 by two lines.

FIG. 20 is a timing chart showing the display on / off data read timing from either one of the frame memories 7 and 8, using Hsync and CL1 as a time axis. Here, N + 384. The line after LINE indicates display on / off data of the line on the lower screen side.

Here, the ratio between the horizontal period Hsync of the input signal and the horizontal period CL1 of the liquid crystal output data is 4Hsync.
nc is 6CL1. This is because, as shown in FIG. 19, the transfer speed of the display on / off data read from the frame memories 7 and 8 is changed by the transfer speed (1 Vsync at the time of writing the display on / off data to the frame memories 7 and 8). As a result, the driving frame frequency FLM of the liquid crystal output data becomes equal to the driving frame frequency Vsync × 6/4 × 2 of the input signal.
(Upper and lower two screen drive) = 3Vsync. Therefore, the driving frame frequency output to the STN liquid crystal display is three times the driving frame frequency of the input signal.

Further, the data selector / data width converter 9a reads the display on / off data on the upper screen side and the display on / off data on the lower screen side, which are read alternately by two lines from the frames 7 and 8, respectively. , The data width is converted from 8-bit parallel to 16-bit parallel.

In FIG. 15, the 16-bit parallel display on / off data corresponding to the display on / off data on the upper screen and the display on / off data on the lower screen read from frame 7 are 1st-L 'and frame 8 The 16-bit parallel display on / off data corresponding to the display on / off data on the upper screen side and the display on / off data on the lower screen side read out from the memory are indicated by 2nd-L '.

In the second embodiment of the present invention, one of the input signals
Within the frame period, display on / off data for three frames is written into the frame memories 7 and 8, and the written display on / off data for three frames are sequentially read out in synchronization with the frame period FLM of the output signal. .

By doing so, the data written to the frame memories 7 and 8 becomes 1-bit display on / off data on which the FRC processing has been performed. Memory 1
The number can be reduced to 16 per unit.

Also, by sequentially writing display on / off data for three frames within one frame period of the input signal, the FRC pattern is changed every frame period FLM of the output signal output at three times the input frame frequency. Can switch.

Further, the data stored in the frame memory becomes 3 bits per pixel.

Therefore, it is possible to reduce the flow of the halftone display portion and to suppress the increase in the number of pins when implementing the LSI.

Further, the memory capacity can be reduced as compared with the case where all the 6-bit gradation display data is written in the frame memory.

In the first and second embodiments described above, the frame frequency of the liquid crystal output data is set to be 2.5 times and 3 times the frame frequency of the input signal. However, the present invention is not limited to this. However, for example, the case where the frame frequency of the liquid crystal output data is made twice as large as the frame frequency of the input signal can also be realized in the same way as in the first and second embodiments.

In the first and second embodiments, the liquid crystal controller for a so-called dual scan type STN liquid crystal display has been described. However, the present invention is widely applied as a liquid crystal controller for a simple matrix type liquid crystal display. It is possible.

Incidentally, the liquid crystal controllers of the first and second embodiments may be constituted by LSI. In this case, the liquid crystal controller constituted by the LSI may be arranged together with the frame memory in a liquid crystal module such as on a printed circuit board on which the liquid crystal driver is arranged or on the back side of the panel.

By doing so, the interface of the liquid crystal module can be the same as the interface of digital RGB having a plurality of bits of gradation information, that is, the interface of the TFT liquid crystal. Furthermore, the liquid crystal controllers according to the first and second embodiments of the present invention may have a configuration in which a frame memory is built in. In this case, further space saving can be achieved.

In the first and second embodiments, the components having the same function are shared,
One liquid crystal controller may correspond to the first and second embodiments. in this case,
The configuration may be such that the mode switching of the first and second embodiments can be performed by, for example, a signal input terminal or the like.

Next, a third embodiment of the present invention will be described.

As described above, in the conventional liquid crystal controller, when the intermediate gray scale display is performed on the upper and lower screens on the so-called dual scan type STN liquid crystal display, the interference fringe of the FRC display is formed at the boundary between the upper and lower screens. There is a problem that it may appear to move.

The cause of the interference fringes will be described with reference to FIG.

FIG. 21 is a diagram for explaining interference fringes generated when a conventional liquid crystal controller displays an FRC pattern over an upper and lower screen on a dual scan STN liquid crystal display.

Here, it is shown how the vertical FRC pattern moves for each frame.

As shown in FIG. 21, in the STN liquid crystal display, scanning is performed in line order. Therefore, even when the first line of the lower screen has already been scanned, the last line of the upper screen has not been scanned yet. The frame pattern remains.

As a result, the vertical lines on the lower screen move slightly ahead, and the appearance of the display data on the upper screen and the lower screen is not continuous.

This causes a phenomenon in which the interference fringes appear to move at the boundary between the upper and lower screens.

The liquid crystal controller according to the present embodiment is for solving the above-mentioned problem. As shown in FIG. 22, the FRC pattern on the lower screen is output one frame later than the upper screen. .

FIG. 23 is a block diagram showing a main structure of a liquid crystal controller according to a third embodiment of the present invention.

Here, reference numeral 21 denotes an FRC processing unit for the upper screen, reference numeral 22 denotes an FRC processing unit for the lower screen, reference numeral 23 denotes a pattern selector, and reference numeral 24 denotes a pattern selector control unit.

The liquid crystal controller of the present embodiment has the same configuration as that of the liquid crystal controller of the first embodiment of the present invention shown in FIG. 1 except that the configuration shown in FIG.

Therefore, the configuration of the present embodiment other than that shown in FIG. 23 is the same as that of the first embodiment shown in FIG. 1, and a detailed description thereof will be omitted.

Upper screen FRC processing section 21, lower screen FR
The C processing unit 22 is basically the same as that of the first embodiment shown in FIG. However, the lower screen FRC processing unit 22
Is set to generate display on / off data delayed by one frame with respect to the upper screen FRC processing unit 1.

The pattern selector control unit 24 counts the number of clocks of the input signal Hsync immediately after the input signal DispTMG becomes active. Then, until the count number becomes half of the resolution of the chairman data (for example, in the case of XGA of 1024 × 768 dots, 0 to 0).
384 counts) causes the pattern selector 23 to select the output of the upper screen FRC processing unit 21.

On the other hand, after the count number becomes half of the resolution (for example, 385 to 768 counts in an XGA of 1024 × 768 dots), the pattern selector 2
3 causes the output of the lower screen FRC processing unit 22 to be selected.

Note that the count number of Hsync is Vsy.
Reset at nc.

In the present embodiment, with the above configuration, the FRC pattern on the lower screen can be output one frame later than the upper screen. Thus, it is possible to prevent the interference fringes from appearing to move at the boundary between the upper and lower screens.

In this embodiment, the configuration shown in FIG. 23 is applied to the first embodiment of the present invention.
It is possible to apply to a liquid crystal controller.

Next, as a fourth embodiment of the present invention, a liquid crystal display device using the liquid crystal controller of the first to third embodiments will be described.

FIG. 24 is a schematic configuration diagram of a liquid crystal display device according to a fourth embodiment of the present invention.

Here, reference numeral 25 denotes an A / D converter, reference numeral 26 denotes a liquid crystal controller according to the first to third embodiments of the present invention described above, and reference numeral 27 denotes a function as the frame memories 7 and 8 described above. A frame memory 28 is a dual scan type STN liquid crystal display.

The A / D converter 25 generates 6-bit gradation data R per pixel based on the R (red), G (green), and B (blue) analog display data used in the CRT monitor.
Generate A, RB, GA, GB, BA, BB.

Specifically, R, G, and B analog display data are extracted in pixel units, and these are converted into 6-bit gradation data. If the order of the pixels specified by these gradation data is even, the pixel is output to RA, GA, and BA, and if the order is odd, it is output to RB, GB, and BB.

Here, the order of the pixels can be obtained by providing a counter that increments according to DotCK and resets according to Vsync.

In the liquid crystal display device shown in FIG. 24, if the input signal is the same as the interface of the TFT liquid crystal, that is, if the input signal is digital RGB having a plurality of bits of gradation information, the A / D converter 25 is used.
Is unnecessary.

As described above, when the analog display data is quantized by the A / D converter 25, the gradation data, particularly the gradation data of the least significant bit, may fluctuate due to a quantization error. In this case, for example,
When a solid-color display at a certain intermediate gradation ratio is performed, there is a problem that FRC patterns of gradation ratios before and after the intermediate gradation ratio are mixed, and image quality deterioration such as interference fringes and flicker occurs. .

According to the present invention and the like, as a result of various experiments, it has been found that the above-described image quality deterioration occurs more noticeably as the patterns of the adjacent FRC patterns of the intermediate gradation ratio differ greatly, and becomes smaller as the patterns approach each other. It was confirmed.

Therefore, in the present embodiment, when the analog display data is converted to digital gradation data using the A / D converter 25 in order to solve the above-mentioned problem, the FRC pattern generated by the liquid crystal controller is as follows. It is set as follows.

FIG. 25 is a view for explaining an FRC pattern generated in the fourth embodiment of the present invention.

In this embodiment, as shown in FIG. 25, when the gradation rate is increased by one step, the display on is added without changing the display on / off arrangement in the FRC pattern of the current gradation rate. Pattern. Also, the FRC pattern is set so that this relationship is always maintained even if the frame changes.

In this way, when digital grayscale data generated from analog display data for a CRT display is input, an intermediate error is generated due to a quantization error generated when converting the analog display data into digital grayscale data. It is possible to suppress the deterioration of the image quality of the gradation display.

By the way, usually, an FRC pattern uses an inversion pattern at a gradation rate located at the midpoint between display ON and OFF. For this reason, the arrangement of the display ON / OFF greatly changes at the gradation rate serving as the boundary point, and the image quality is likely to deteriorate.

Therefore, it is important not to disturb the display ON / OFF arrangement as much as possible even at the boundary point, for example, by shifting the entire pattern in the horizontal or vertical direction, instead of simply using the inverted pattern.

[0256]

As described above, according to the first aspect of the present invention, it is possible to reduce the flow and flicker of the halftone display portion with a small memory capacity, and to increase the number of pins when an LSI is used. Can be suppressed.

Further, according to the second aspect of the present invention, it is possible to prevent interference fringes that occur when halftone display is performed on the upper and lower screens of a so-called dual scan type STN liquid crystal display. .

Further, according to the third aspect of the present invention, C
When digital grayscale data generated from analog display data for an RT display is used as an input signal, image quality degradation of halftone display occurs due to a quantization error generated when converting analog display data to digital grayscale data. Can be suppressed.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a liquid crystal controller according to a first embodiment of the present invention.

FIG. 2 is a schematic block diagram of a circuit used in the FRC processing unit 1 shown in FIG.

FIG. 3 is a schematic block diagram of FRC decoders 101 to 104 shown in FIG.

4 is a timing chart for explaining display on / off data output from FRC decoders 101 to 104 shown in FIG. 3 and read / write control of frame memories 7 and 8 shown in FIG. 1;

5 is a diagram for more clearly explaining the relationship between display on / off data output from FRC decoders 101 to 104 shown in FIG. 3, and is a diagram showing an example of an FRC pattern displayed on a liquid crystal display; It is.

FIG. 6 is a diagram showing an FRC pattern configured by display on / off data generated by FRC decoders 101 to 104 in order to configure the FRC pattern as shown in FIG.

FIG. 7 is a timing chart for explaining processing in a display data width conversion unit 2 shown in FIG. 1;

8 is a data selector / data width converter 4 shown in FIG.
FIG. 9 is a timing chart for explaining display on / off data output bus width conversion processing in FIG.

9 is a data selector and data width converter 4 shown in FIG.
FIG. 9 is a timing chart for explaining the display on / off data order rearranging process in FIG.

FIG. 10 is a timing chart for explaining display on / off data order rearrangement processing in the data selector / data width converter 4 shown in FIG. 1;

11 is a diagram showing an example of a storage location of display on / off data in the frame memories 7 and 8 shown in FIG.

12 is a timing chart showing display on / off data read timings from the frame memories 7 and 8 shown in FIG. 1 using a write clock and a read clock for the frame memories 7 and 8 as a time axis.

FIG. 13 is a timing chart showing display on / off data read timing from either one of the frame memories 7 and 8 shown in FIG. 1 using Hsync and CL1 as a time axis.

14 is a timing chart showing the timing of writing and reading of display on / off data to and from the line memory group 10 shown in FIG. 1 and display on / off data output to the data selector 11 shown in FIG. 1; It is.

FIG. 15 is a schematic block diagram of a liquid crystal controller according to a second embodiment of the present invention.

FIG. 16 shows an FR used in the FRC processing unit 1a shown in FIG.
It is a schematic block diagram of C processing part.

FIG. 17 shows FRC decoders 101a-10 shown in FIG.
It is a schematic block diagram of 3a.

FIG. 18 shows FRC decoders 101a-10 shown in FIG.
Display on / off data output from FIG. 3a and FIG.
5 is a timing chart for explaining read / write control of the frame memories 7 and 8 shown in FIG.

19 is a timing chart showing display on / off data read timings from the frame memories 7 and 8 shown in FIG. 15 using a write clock and a read clock for the frame memories 7 and 8 as a time axis.

FIG. 20 is a timing chart showing display on / off data read timing from one of the frame memories 7 and 8 shown in FIG. 15 using Hsync and CL1 as a time axis.

FIG. 21 is a diagram for explaining interference fringes generated when an FRC pattern is displayed over an upper and lower screen on a dual scan STN liquid crystal display by a conventional liquid crystal controller.

FIG. 22 is a diagram illustrating a change in an FRC pattern according to a third embodiment of the present invention.

FIG. 23 is a block diagram showing a main configuration of a liquid crystal controller according to a third embodiment of the present invention.

FIG. 24 is a schematic configuration diagram of a liquid crystal display device according to a fourth embodiment of the present invention.

FIG. 25 is a diagram for explaining an FRC pattern generated in the fourth embodiment of the present invention.

FIG. 26 shows an input signal DotC of the liquid crystal controller.
It is a timing chart for explaining an example of timing of K, Hsync, Vsync, and DispTMG.

FIG. 27 is a timing chart for explaining an example of the timing of CL2, CL1, and FLM generated by the synchronization signal generator 15 shown in FIGS. 1 and 15;

FIG. 28 is a timing chart for explaining an example of the timing of CL2, CL1, and FLM generated by the synchronization signal generator 15 shown in FIGS. 1 and 15;

FIG. 29 is a diagram for explaining an example of halftone processing according to the conventional FRC method.

FIG. 30 is a schematic block diagram of a conventional liquid crystal controller.

FIG. 31 is a schematic block diagram of a conventional liquid crystal controller.

[Explanation of symbols]

1, 1a FRC processing unit 2 data width conversion unit 3, 10 line memory group 4, 9, 9a data selector / data width conversion unit 5, 5a, 6, 6a frame memory read / write control unit 7, 8, 27 frame memory Reference Signs List 11 data selector 12 data width conversion unit 13, 14 line memory read / write control unit 15 synchronization signal generation unit 21 FRC processing unit for upper screen 22 FRC processing unit for lower screen 23 pattern selector 24 pattern selector control unit 25 A / D converter 26 liquid crystal controller 28 liquid crystal display panel 101-104, 101a-104a FRC decoder 105, 105a Vsync counter 106 write data selector 107, 107a FRC pattern generator 108, 108a selector

 ──────────────────────────────────────────────────の Continuing from the front page (72) Inventor ▲ Shin ▼ Hiroyuki No 1099 Ozenji Temple, Aso-ku, Kawasaki City, Kanagawa Prefecture Inside Hitachi, Ltd.System Development Laboratory (72) Inventor Shinji Uchida 3300 Hayano, Mobara City, Chiba Prefecture Stock (72) Inventor Tatsuhiro Inuzuka 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Japan

Claims (9)

[Claims] 1. A display on / off ratio of a pixel in a plurality of frame periods of an output signal to be output to a liquid crystal display for each pixel in accordance with gradation data of the pixel included in an input signal. A liquid crystal controller that sets a signal frame unit and performs an intermediate gray scale display of the liquid crystal display, wherein display on / off data is displayed for each pixel according to pixel-level gray data included in the input signal. Generating a plurality of display on / off data for M (M> N) frames of the output signal within N frame periods of the input signal; and Writing control means for writing display on / off data for M frames of the output signal into a frame memory within N frame periods of the input signal; A read control unit for sequentially reading out the written display on / off data for M frames of the output signal for each frame in synchronization with a frame period of the output signal. . 2. The liquid crystal controller according to claim 1, wherein said writing control means temporarily stores a plurality of display on / off data sequentially generated for each pixel by said generation means; A liquid crystal controller comprising: memory control means for controlling writing and reading of off data to and from the memory such that a reading speed is higher than a writing speed. 3. The liquid crystal controller according to claim 1, further comprising a conversion unit for converting the display on / off data read by the read control unit into a data width according to the specification of the liquid crystal display. A liquid crystal controller. 4. The liquid crystal controller according to claim 1, wherein the liquid crystal display is a dual scan type liquid crystal display that divides a display screen into upper and lower parts and simultaneously drives the display screen. Display on / off data sequentially read out for each frame of the signal, display on / off data for a pixel located on the upper side of the display screen,
The display on / off data for the pixel located on the lower side is the upper screen data and the lower screen data, respectively.
A liquid crystal controller further comprising a conversion means for converting so as to be synchronously output with a data width according to the specification of the liquid crystal display. 5. A liquid crystal display device comprising: a simple matrix display type liquid crystal display; a frame memory; and the liquid crystal controller according to claim 3 or 4. 6. A switching pattern of a display ON / OFF of a pixel in a plurality of frame periods of an output signal to be output to a liquid crystal display is set for each pixel in accordance with gradation data of the pixel included in the input signal. A liquid crystal controller that performs halftone display of the liquid crystal display, wherein the liquid crystal display is a dual scan liquid crystal display that divides a display screen into upper and lower parts and simultaneously drives the display screen; First setting means for setting a display on / off switching pattern of the pixel during a plurality of frame periods of the output signal in accordance with the gradation data of the pixel located on the upper side of the screen; and the display included in the input signal. According to the grayscale data of the pixel located at the lower side of the screen, a plurality of frames of the output signal And a second setting means for setting a display on / off switching pattern of the pixel in the second setting means, wherein the second setting means sets a display on / off switching pattern of a pixel located on a lower side of the display screen. A liquid crystal controller wherein the output signal is set to be delayed by one frame from a display on / off switching pattern of a pixel positioned above the display screen set by the first setting means. 7. A liquid crystal display device comprising: a dual scan type simple matrix type liquid crystal display which divides a display screen into upper and lower parts and is simultaneously driven; and the liquid crystal controller according to claim 6. 8. A display ON / OFF operation for each pixel during a plurality of frame periods of an output signal to be output to a liquid crystal display, for each pixel, according to pixel-level grayscale data generated by quantizing an analog grayscale signal. A liquid crystal controller that sets an off switching pattern and performs an intermediate gradation display of the liquid crystal display, wherein the display on / off switching pattern is for each pixel,
A liquid crystal controller, wherein values corresponding to adjacent gradation data are set in advance so that frames whose display is turned on or turned off are substantially common to each other. 9. A liquid crystal display of a simple matrix display type, conversion means for quantizing an analog gray scale signal and converting the analog gray scale signal into gray scale data in pixel units, and a liquid crystal controller according to claim 8. Characteristic liquid crystal display device.