JPH10285457A - Edit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify a device and to reduce cost by using a video signal mixed with an audio signal, so as to place a video-processing section and an audio- processing section in a same case. SOLUTION: An embedded audio/video signal is reproduced from VTRs 71A-71n and the signal is fed to an edit processing unit 72. A signal which is fed to a video processor circuit 72B via an A/V matrix circuit 72A is given to a blanking circuit included in the circuit 72B, where the audio signal is deleted and only the video signal is extracted, and video effect processing is applied to the video signal. The audio signal is extracted from the signal supplied via the circuit 72A in an audio separator circuit 72C, and the audio processor circuit 72D applies audio effect processing to the audio signal. The audio signal is superimposed on the video signal in an A/V combiner 72E, in which the embedded audio/video signal is generated and from which the signal is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[Table of Contents] The present invention will be described in the following order.

BACKGROUND OF THE INVENTION Problems to be Solved by the Invention Means for Solving the Problems Embodiments of the Invention Effects of the Invention

[0003]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an editing apparatus that can edit a video signal and an audio signal using a transmitted audio mixed video signal.

[0004]

2. Description of the Related Art Hitherto, as an editing apparatus, an editing apparatus using a video tape recorder (hereinafter, abbreviated as VTR) as a recording means for recording video and audio has been proposed. In such an editing apparatus, video and audio as materials are recorded on a VTR, and editing is performed by reading and using a desired video and audio from the VTR.

In a conventional editing apparatus, it is necessary to separately prepare a device for processing video signals (video switcher, video effector, etc.) and a device for processing audio signals (audio mixer, audio effector, etc.). was there.

In recent years, a video / audio signal transmission method using a mixed digital signal in which audio is mixed with video data, that is, an audio mixed video signal (hereinafter referred to as an embedded audio / video signal) has been established. Specifically, as shown in FIG. 11, the audio signal and the video signal are transmitted such that the audio signal is superimposed on the blanking interval of the video signal. In fact, in broadcasting equipment, major digital equipment such as a digital VTR has already transmitted in this signal form.

FIG. 12 is a schematic diagram of the editing apparatus. In the digital VTRs 81A to 81n, embedded audio / video signals are reproduced. The reproduced embedded audio / video signal is output from a digital VTR.
81A to 81n are supplied to A / V separators 82A to 82n. In the A / V separators 82A to 82n, the supplied embedded audio / video signal is separated into an embedded audio signal and a video signal.
The video signals separated by the A / V separators 82A to 82n are supplied to a video processor 83, and the audio signals are supplied to an audio processor 84. In the video processor 83, the supplied video signal is subjected to special effects and the like, and is supplied to the A / V combiner 85. Similarly, the audio signal supplied to the audio processor 84 is also subjected to special effects and the like, and is supplied to the A / V combiner 85. In the A / V combiner 85, the audio signal is superimposed on the video signal as shown in FIG.

As described above, in the conventional editing device,
When video and audio signals are transmitted as embedded audio / video signals, they must first be separated into video and audio signals. Then, in the video processor 83, switching and mixing of video signals, and addition of special effects and the like are performed. This processing system includes a video signal cross point circuit, and performs the above-described processing on the selected signal. Also,
In the audio processor 84, a required audio signal is selected from a plurality of audio signal inputs by an audio signal crosspoint circuit included in the audio processor 84 (this selection is sometimes made using a dedicated device). Processing such as mixing and audio special effects is performed on the signal. In this way, the video signal and the audio signal are separately processed, and the output of each is finally combined with a circuit (A / V) for mixing the audio signal with the video signal.
The signal is output as one system signal by a device having the combiner 85).

[0009]

As described above, in the conventional editing apparatus, the video processing and the audio processing are performed completely independently. In recent years, the input and output of a non-linear editing machine also include a video signal and an audio signal. For this reason, when an embedded audio / video signal is used, it is necessary to adopt a configuration in which the video signal and the audio signal are once separated before being input to each device and then passed through the respective processing blocks. .

Further, since the video processing unit and the audio processing unit are completely different housings, it is naturally necessary to provide a cross point having a mouth for each of the number of inputs (the number of inputs to be processed). Was. Of course, cables were needed accordingly.

Accordingly, it is an object of the present invention to edit a video signal and an audio signal in a single housing using an embedded audio / video signal to be transmitted, thereby minimizing cable connections in the system. In addition, an object of the present invention is to provide an editing apparatus which can reduce the number of inputs to each device, thereby reducing the cost of the entire editing apparatus.

[0012]

According to the first aspect of the present invention, an audio mixed video signal in which an audio signal is superimposed in a blanking section of a video signal is supplied, and the video signal and the audio signal of the supplied audio mixed video signal are supplied. In an editing device capable of editing a signal, a plurality of audio-mixed video signals are input, and a cross-point means for selecting a plurality of audio-mixed video signals, and a video signal from the audio-mixed video signal selected by the cross-point means. Video processing means for extracting the audio signal from the audio mixed video signal selected by the cross point means, processing the audio signal, and outputting the video signal. Combiner means for synthesizing the output of the processing means and generating an audio mixed video signal. It is an editing apparatus for the.

When a video signal and an audio signal are edited using an embedded audio / video signal in which an audio signal is superimposed on a blanking section of the video signal, a plurality of embedded audio / video signals are sent to an A / V matrix circuit. Supplied. In the A / V matrix circuit, the supplied embedded audio /
It is determined whether the video signal is supplied to the video processing unit or the audio processing unit, and is supplied to the corresponding processing unit. In the video processing section, an audio signal is extracted from the supplied embedded audio / video signal by an ordinary blanking circuit, and only a video signal is extracted. Editing processing is performed on the extracted video signal. From the embedded audio / video signal supplied to the audio processing unit, only the audio signal is extracted by an audio separator circuit before the input of the audio processing unit. The audio processing unit performs an editing process on the extracted audio signal. In the processed video signal and audio signal, the audio signal is superimposed on the video signal by the A / V combiner and output.

[0014]

An embodiment of the present invention will be described in detail with reference to the drawings.

(1) Overall Configuration of Editing Apparatus In FIG. 1, reference numeral 1 denotes an editing apparatus to which the present invention is applied as a whole, and is roughly composed of a computer 2 and an editing processing apparatus 3.

The computer 2 includes a main body 2A having a CPU (central processing unit) and various processing circuits, a floppy disk drive, a hard disk drive, and the like, and a monitor 2B as a display means connected to the main body 2A.
And a keyboard 2C and a mouse 2D as input means. In such a computer 2, an application program is preinstalled on a hard disk drive as software for editing.
By running the application program under the operating system, the application program is started as a computer for the editing apparatus.

By the way, when this application program is operated, a graphic display for a GUI (graphical user interface) is displayed on the monitor 2B. A control command for editing can be input through this GUI. Note that the computer 2 generates a control signal S1 corresponding to the control command if the content of the input control command controls the operation of the editing processing device 3, and sends the control signal S1 to the editing processing device 3. Has been made.

A video signal S2 is input to the computer 2 via the editing processor 3, whereby the video of each material is displayed on the monitor 2B, and the contents are checked while checking the contents. (Start point of the event) and Out point (End point of the event) can be indicated, and the event material or the video of the edited program cut out by indicating the In and Out points can be displayed. The contents can be displayed and confirmed (hereinafter, confirming the contents of the cut material or the edited program is referred to as preview).

On the other hand, the editing processing device 3 has a matrix switch unit, an image processing unit and an audio processing unit therein, and performs actual processing such as cutting and joining of materials or signal processing for video signals and audio signals. This is a device that performs editing work.

The editing processor 3 is connected not only to the computer 2 as described above, but also to dedicated controllers 4 and 5, so that even if the dedicated controllers 4 and 5 are used, editing is performed. The user can input a control command.

Incidentally, the dedicated controller 4 has a button operator for instructing an in point or an out point of a material, a button operator for instructing reproduction of a material, or a command for recording an edited program. In addition to having button operators and the like, it also has dial operators and the like for inputting instructions for variable-speed playback (so-called shuttle playback) and frame-by-frame playback (so-called jog playback). The control signal S3 corresponding to the instruction information input via the dial operator is transmitted to the editing processing device 3. Also, the dedicated controller 5 has a slide operator (so-called audio-off ada) for inputting an audio level, a slide element (so-called video fader) for inputting a switching ratio when switching between two images, and the like. A control signal S4 corresponding to the instruction information input via these slide operators is sent to the editing processing device 3.

A daily server 6 (storage means for storing editing materials such as video and audio in a broadcasting station) is connected to the editing processing device 3 and stored in the daily server 6. Video and audio signals. in this case,
The daily server 6 has output ports for two channels, and reads desired video and audio signals S7 and S8 from the storage medium 6A in accordance with control signals S5 and S6 for each channel supplied from the editing processing device 3. Output. The storage medium 6A has a compression ratio
1/10 MPEG (Moving Picture coding Experts Grou
p) Video and audio signals compressed according to the standard are stored, and the read video and audio signals are decoded via decoders 6B and 6C, respectively, and then read out from a serial digital interface (hereinafter referred to as "digital interface"). ,
This is called an SDI) standard format.
The SDI standard video and audio signals S7, S8
Is supplied to the editing processing device 3.

The editing processing device 3 has a VTR
7 is also connected so that the video and audio signals stored in the VTR 7 can also be captured. In this case, the VTR 7 has an SDI-standard input / output interface, and reads and outputs a desired video and audio signal S10 in accordance with a control signal S9 supplied from the editing processing device 3. The VTR 7 receives the video and audio signals after the editing processing and the video and audio signals S7 and S8 read from the daily server 6 from the editing processing device 3 as the recording target video and audio signals S11. In addition, the video and audio signal S11 are recorded on a video tape in response to a control signal S9.

A local storage 8 composed of a plurality of hard disks is also connected to the editing processor 3 so that video and audio signals stored in the local storage 8 can be taken in. In this case, the local storage 8 has an input / output interface conforming to the SDI standard, has a port for two channels as an output port, and responds to a control signal S12 supplied from the editing processing device 3. The desired video and audio signals S13 and S14 are read and output. The local storage 8 receives the video and audio signal after the editing process and the video and audio signal read from the daily server 6 or the VTR 7 from the editing processing device 3 as a video and audio signal S15 to be recorded. The video and audio signal S15 is recorded on an internal hard disk in response to the control signal S12.

An on-air buffer (storage means for temporarily storing a program at the time of broadcasting) 9 is also connected to the editing processing device 3, and the editing processing device 3 edits the data. The video and audio signal S16 of the processed program can be stored in the on-air buffer 9. In this case, since the on-air buffer 9 has an input interface of the SDI standard,
The transmitted video and audio signal S16 is S
It is a DI format signal format. In the on-air buffer 9, the supplied video and audio signals S16 are compressed by the encoder 9A according to the MPEG standard with a compression ratio of 1/10, and then stored in the internal storage medium 9B.

The on-air buffer 9 and the computer 2 of the editing apparatus 1 are connected to a local area network (hereinafter, referred to as a LAN) 10 such as an Ethernet.
The control command for the on-air buffer 9 is sent to the on-air buffer 9 via the computer 2 and the LAN 10. An edit list (generally called an edit decision list) indicating what kind of material the edited program is made of is also sent to the on-air buffer 9 via the LAN 10.

The computer 2 of the editing device 1 and the daily server 6 are also connected via this LAN 10.
The computer 2 can refer to the file name and the like of each material stored in the daily server 6 via the LAN 10.

Speakers 11 and 12 are connected to the editing processing device 3 as option connections, and the audio signals S17 and S18 edited by the editing processing device 3 are transmitted to the speakers 11 and 12, respectively. 12 to confirm the editing contents related to audio.

Further, a monitor 13 for exclusive use of preview is also connected to the editing processing device 3 as an option connection, and the video signal S19 edited by the editing processing device 3 is displayed on the monitor 2B. Then, the contents of editing concerning the video can be confirmed on the monitor 13 as well. Incidentally, the preview screen displayed on the monitor 13 is larger than the preview screen displayed on the monitor 2B of the computer 2, so that the editing contents can be more clearly confirmed by connecting the monitor 13.

Here, an editing method in the editing apparatus 1 will be briefly described. First, in the editing apparatus 1, when the application program is started, the graphic display for the GUI is displayed on the monitor 2B as described above. The operator clicks on the GUI displayed on the monitor 2B using the mouse 2D to indicate the device (that is, the daily server 6, the VTR 7, or the local storage 8) in which the editing material is stored, and also displays the material. To play. Thus, the video signal S2 of the specified material is supplied to the computer 2 via the editing processing device 3, and the video of the material is displayed on the monitor 2B. The operator generates an event necessary for program creation by designating an in point and an out point while watching the video of the material. The operator repeats this process and prepares all events necessary for program creation.

Subsequently, the operator instructs the order of the program by rearranging the events specified earlier in a desired order in a display area called a program window. If a special effect is to be applied to a desired event, the position and the type of the special effect are designated in the program window. Incidentally, this program window is a virtual space used when creating a program, and a program is not created simply by arranging events in the program window.

When the outline of the program is determined in this way, the operator inputs a preview instruction via the GUI. Upon receiving this, the editing device 1 controls the editing processing device 3 to reproduce each event based on the order of the program specified in the program window, and also controls the editing processing device 3 to specify the event specified by the editing processing device 3. To generate a video signal S2.
This video signal S2 is supplied to the computer 2 and is displayed on the monitor 2B. Thus, the operator can confirm the contents of the set program.

As a result of the preview, if there is no change in the program contents, the operator inputs a recording instruction via the GUI. The editing apparatus 1 receiving this generates the video and audio signal S15 indicating the designated program by controlling the editing processing apparatus 3 in the same manner as described above, and supplies this to the local storage 8 for recording. Thus, by this processing, the program specified by the program window is completed and stored in the local storage 8. In the case of broadcasting the program generated by this editing, if a transfer instruction is input via a GUI, the video and audio signals are read out from the local storage 8 and the on-airbatches via the editing processing device 3. Forwarded to fa9.

In this way, in the editing apparatus 1, the program can be created while checking the video of each material and the video of the program on the monitor 2B, so that the editing convenience can be improved. Further, in the editing apparatus 1, since the editing can be performed without the operator directly operating the switch or the special effect apparatus, the editing operation can be easily performed, and the labor required for the editing can be reduced.

(2) Internal Configuration of Computer In this section, the internal configuration of the computer 2 will be specifically described. As shown in FIG. 2, the computer 2 includes a system bus 20 for transmitting command data and video data, a CPU 21 for controlling the entire computer, and a video processor for performing image processing and the like on an input video signal S2. 22, a display controller 23 for managing graphic data for video data and GUI displayed on the monitor 2B, an HDD interface 24 for controlling a local hard disk drive (local HDD) 24A, and a floppy disk drive (FDD)
FDD interface 25 for controlling 25A,
Pointing device interface 26 that generates control commands based on commands from pointing devices such as mouse 2D and keyboard 2C, and an external interface that includes a software driver for sending control signal S1 to edit processing device 3. 27.

The system bus 20 is a bus for communicating video data, command data, address data, and the like inside the computer 2, and includes an image data bus 20A for transmitting video data, a command data and address data. And a command data bus 20B for transmitting the command data.

The CPU 21, the video processor 22, the display controller 23, the HDD interface 24, and the FDD interface 25 are connected to the image data bus 20A, and the CPU 21, the video processor 22, the display controller 23, the HDD interface The face 24 and the FDD interface 25 transmit video data via the image data bus 20A.

On the other hand, the command data bus 20B has C
PU21, video processor 22, display controller 2
3, HDD interface 24, FDD interface 25, pointing device interface 2
6 and the external interface 27 are connected to each other (that is, all blocks in the computer 2 are connected), and command data and address data are transmitted via the command data bus 20B. .

The CPU 21 is a block for controlling the entire computer 2 and has a ROM 21A in which the operating system of the computer 2 is stored, and a RAM 21B in which an uploaded application program and the like are stored. When activating the computer 2, the CPU 21 executes a software program based on the operating system stored in the ROM 21A. When the application program is to be executed under the operating system being started, the CPU 21 first operates the hard disk drive 24.
The application program recorded on the hard disk of A is read and uploaded to the RAM 21B, and thereafter, the application program is executed.

The video processor 22 is connected to the computer 2
Receives the SDI standard video signal S2 input to the
While performing data conversion on the video signal S2,
This is a block for temporarily buffering the converted video data. Specifically, the video processor 22 extracts a composite video signal from a payload portion of the received video signal S2, and a processor controller 22A that controls the entire video processor 22, and outputs the composite video signal. Data conversion unit 2 that converts a video signal into a digital component video signal
2B and a frame memory 2 for temporarily storing video data of several frames transmitted from the data conversion unit 22B.
2C.

The processor controller 22A controls the data conversion operation of the data conversion unit 22B by sending a control signal to the data conversion unit 22B, and also transmits the time code from the video signal S2 to the data conversion unit 22B. Let it be extracted. Processor controller 2
2A controls a read / write timing and a read / write address of the frame memory 22C by sending a control signal to the frame memory 22C. Incidentally, regarding the read timing, the processor controller 22A controls the read timing of the frame memory 22C so that the time code transmitted to the display controller 23 and the video data (frame data) correspond to each other.

The data converter 22B converts a composite video signal into a digital component video signal based on a control signal from the processor controller 22A. Incidentally, the time code is extracted in this conversion process. The video data obtained by this conversion is sent to the frame memory 22C as described above, and the extracted time code is sent to the processor controller 22A.
Sent to

The frame memory 22C includes a data converter 22
The video data supplied from B is temporarily stored. The read / write timing of the frame memory 22C is controlled by the processor controller 22A as described above. The frame memory 22C is composed of two frame memories, and is capable of storing video data for two frames.

The video data stored in the frame memory 22C is read based on the read control of the processor controller 22A. At this time, the image size is made smaller than the original image by reading out the video data stored in the frame memory 22C, instead of reading out all pixels, at a predetermined interval. The video data whose image size has been reduced in this manner is transmitted to the monitor 2
Since it is displayed in the view window of B (details will be described later), it is transmitted to the display controller 23 via the image data bus 20A.

The display controller 23 is a control block for controlling data displayed on the monitor 2B.
The display controller 23 is connected to the memory controllers 23A and V
RAM (Video Random Access Memory) 23B
And The memory controller 23A controls the read / write timing of the VRAM 23B according to the internal synchronization of the computer 2. In this VRAM 23B,
The video data transmitted from the frame memory 22C of the video processor 22 and the image data generated by the CPU 21 are stored based on a timing control signal from the memory controller 23A. This VRAM
The video data and image data stored in 23B are
The data is read out based on the timing control signal from the memory controller 23A based on the internal synchronization of the computer 2 and displayed on the monitor 2B.

In this case, the graphic display based on the image data becomes the graphic display for the GUI. Incidentally, the image data transmitted from the CPU 21 to the VRAM 23B is, for example, image data such as a window, a cursor, a scroll bar, or an icon indicating a device. The computer 2 obtains a graphic display for the GUI by displaying these plural types of image data on the monitor 2B.

The HDD interface 24 is an interface block for communicating with a local hard disk drive (HDD) 24A provided inside the computer 2. The HDD interface 24 and the hard disk drive 24A are connected to a SCSI (Small Comp
The communication is performed based on a transmission format of a uter system interface.

An application program to be started by the computer 2 is installed in the hard disk drive 24A. When the application program is executed, the application program is read from the hard disk drive 24A and uploaded to the RAM 21B of the CPU 21. You. When the application program is terminated, various information (for example, file information) generated by the editing operation stored in the RAM 21B is stored in the hard disk drive 2.
Downloaded to the hard disk via 4A.

The FDD interface 25 is an interface block for communicating with a floppy disk drive (FDD) 25A provided inside the computer 2. The FDD interface 25 and the floppy disk drive 25A communicate with each other based on a SCSI transmission format.

The pointing device interface 26 is an interface block for receiving information from the mouse 2D and the keyboard 2C connected to the computer 2. The pointing device interface 26 receives, from the mouse 2D, detection information of a two-dimensional rotary encoder provided on the mouse 2D and click information of left and right buttons provided on the mouse 2D, and decodes the received information. CPU 21
To send to. Similarly, the pointing device interface 26 receives input information from buttons provided on the keyboard 2 </ b> C, decodes the received input information, and sends it to the CPU 21. Thereby, the CPU 21
It is possible to recognize which command button of the GUI displayed on the monitor 2B has been designated, and to use the keyboard 2
Various data input from C can be recognized, and control corresponding thereto can be performed.

The external interface 27 is a block for communicating with the editing processing device 3 connected to the outside of the computer 2. The external interface 27 is a CPU
A driver for converting various control commands such as a reproduction command and a recording command generated in 21 into data of a predetermined communication protocol, and sends a control signal S1 indicating the control command to the editing processing device 3 via the driver. Send out.

(3) Configuration of Editing Processing Apparatus In this section, the configuration of the editing processing apparatus 3 will be described. As shown in FIG. 3, the editing processing device 3 is roughly divided into a system control unit 3A, a matrix switch unit 3B,
It comprises an image processing unit 3C and an audio processing unit 3D. The system control unit 3A receives the control signal S1 sent from the computer 2 and the control signals S3 and S4 sent from the dedicated controllers 4 and 5, and receives the control signal S1.
The operation of each block is controlled based on 1, S3 or S4.
Specifically, the system control unit 3A controls the operations of the matrix switch unit 3B, the image processing unit 3C, and the audio processing unit 3D via the control bus 3E, and sends out control signals S5, S6, S9, or S12. Then, it controls the reproduction or recording operation of the daily server 6, the VTR 7 and the local storage 8, and the like. Incidentally, the system control unit 3A also receives a reference time code (REF-TC) supplied from the outside, and manages the time code.

The matrix switch unit 3B has a plurality of input terminals and a plurality of output terminals, and connects a desired input terminal to a desired output terminal under the control of the system control unit 3A. As a result, a desired signal among the video and audio signals read from each device (daily server 6, VTR 7, or local storage 8) can be transmitted to the image processing unit 3C and the audio processing unit 3D, and the desired signal can be transmitted. To the computer 2 or each device (VTR 7, local storage 8, or on-air buffer 9). Further, the video signal processed by the image processing unit 3C is sent to the computer 2, or the audio signal processed by the audio processing unit 3D is superimposed on the video signal, and each device (VTR 7, local storage 8) Alternatively, it can be sent to an on-air buffer 9).

The image processing unit 3C includes transition effects (effects such as switching from background video to foreground video such as wipes and page turns) and animation effects (mosaic, picture-in-picture, etc.). This is a block for applying a special effect such as special image processing or insertion processing to a video signal. The video signal is extracted from the video and audio signals selected by the matrix switch unit 3B, and the video signal is extracted. After applying the special effect to the matrix switch section 3B, the video signal is output to the matrix switch section 3B.

The audio processing unit 3D is a block for adjusting and synthesizing the level of the audio signal. After extracting the audio signal from the video and audio signals selected by the matrix switch unit 3D, the audio processing unit 3D applies the level to the audio signal. The audio signal is adjusted or the audio signals are combined with each other, and the resulting audio signal is combined with the matrix switch unit 3B or the speaker 11,
12 is output.

Here, the configuration of each of these blocks will be specifically described with reference to the drawings. As shown in FIG. 4, the system control unit 3A includes a main CPU (M-CPU).
30, a communication / unification CPU (C-CPU) 31, and a plurality of device control CPUs (D-CPUs) 32-34. The main CPU 30 is a CPU for controlling the operation of each block by giving a control command to each block (ie, the matrix switch unit 3B, the image processing unit 3C, and the audio processing unit 3D) via the control bus 3E. . The communication unit CPU 31 receives a reference time code (REF-TC) generated by an external time code generator (not shown) or controls the control signal S1 from the computer 2 or the dedicated controller 4, Communication CPU for receiving control signals S3 and S4 from
It is. The device control CPUs 32 to 34 send control signals S5, S6, S9 to each device (that is, the daily server 6, the VTR 7, and the local storage 8).
Alternatively, it is a CPU for sending S12 to control the operation of each device.

Such a system control unit 3A
The control signal S is transmitted by the communication unit CPU 31.
1, S3 or S4 is received and the control command indicated by the control signal S1, S3 or S4 is reproduced by the communication unit CPU 31. This control command is transferred to the main CPU 30 via the bus 35 inside the system control unit 3A. The main CPU 30 analyzes this control command, and sends a control command to the corresponding device control CPU 32, 33 or 34 if device control is necessary, and controls the operation of the device via the device control CPU 32, 33 or 34. If control is required, control of the matrix switch unit 3B, image processing unit 3C or audio processing unit 3D is sent to the corresponding block via the control bus 3E to control the operation of the block.

Incidentally, the communication unity CPU 31
Is the external interface 27 of the computer 2 inside.
And a control signal S sent from the computer 2 by the driver.
1 is received. Each of the device control CPUs 32 to 34 has an RS-422 standard driver therein, and the control signal S5, S6, S9, or S12 of the RS-422 standard is transmitted to each device by the driver. ing.

Next, the matrix switch section 3B will be described with reference to FIG. As shown in FIG. 5, the matrix switch unit 3B is roughly divided into a control circuit 40,
It comprises a matrix switch block 41 and a format conversion block 42. The control circuit 40 is a circuit for controlling the entire matrix switch section 3B, generates control signals S20 and S21 based on a control command received via the control bus 3E, and converts the control signals S20 and S21 into a matrix, respectively. The output is output to a switch block 41 and a format conversion block 42 to control the operation.

In the matrix switch block 41, a plurality of input lines connected to the input terminals IN1 to IN11 and a plurality of output lines connected to the output terminals OUT1 to OUT13 are arranged in a grid. The input line and the output line can be connected at a cross point (indicated by a cross in the figure) where the input line and the output line intersect. For this reason, if the input line and the output line are connected at a desired cross point on the basis of the control signal S20 supplied from the control circuit 40, the matrix switch block 41 can be connected to the input terminal IN.
Desired signals input to 1 to IN11 can be output to desired output terminals OUT1 to OUT13.

Incidentally, the matrix switch section 3B
In FIG. 5, the video and audio signals read from the devices of the daily server 6, the VTR 7, and the local storage 8 are input to the input terminals IN1 to IN8, respectively (however, in the example of FIG. Video and audio signals S7, S8, S10, S13, and S14 are input to the input terminals IN1 to IN5, and the input terminals IN5 to IN8 are empty terminals. The input terminals IN9 and IN10 receive video signals S31 and S32, respectively, which have been subjected to image processing by the image processing unit 3C, and the input terminal IN11 has audio signals subjected to signal processing by the audio processing unit 3D. The signal S33 is input.

In the matrix switch section 3B, the output terminal OUT1 is assigned to the local storage 8 as a terminal for outputting the video and audio signal S15, and the output terminal OUT2 outputs the video and audio signal S11 to the VTR 7. Output terminal OUT3 is allocated to the on-air buffer 9 as a terminal for outputting the video and audio signal S16, and the output terminals OUT1 to OUT0
UT3 is assigned as a terminal for program output. The output terminal OUT4 is assigned as a preview output terminal for outputting the video signal S19 to the monitor 13 dedicated to preview, and the output terminal OUT5 is used as a capture output terminal for outputting the video signal S2 to the computer 2. Assigned as. Further, the output terminals OUT6 to OUT10 are assigned as terminals for outputting video and audio signals S23 to S27 to the image processing unit 3C, and the output terminals OUT6 to OUT10 are output.
11 to OUT13 are assigned as terminals for outputting video and audio signals S28 to S30 to the audio processing unit 3D.

The format conversion block 42 is a circuit block for converting the signals output to the output terminals OUT1 to OUT5 into SDI standard signals based on the control signal S21 supplied from the control circuit 40, and the output terminal OUT1.
To an output processor 43 and an audio combiner 44 for format-converting a signal to be output to OUT3.
An output processor 45 for format-converting a signal output to an output terminal OUT4, and an output terminal OUT
And an output processor 46 for format-converting the signal to be output to the output terminal 5.

The output processor 43 outputs a video signal (ie, a video signal S3 input to the input terminal IN9 or IN10) which has been subjected to image processing by the image processing section 3C.
1 or S32), the video signal S31
Alternatively, S32 is converted into an SDI standard video signal. The audio combiner 44 outputs the embedded audio signal processed by the audio processing unit 3D (that is, the audio signal S33 input to the input terminal IN11), the S output from the output processor 43.
The embedded audio signal S33 is superimposed on the video signal of the DI standard. Thus, the video signals S31 and S32 processed by the image processing unit 3C and the audio processing unit 3
The audio signal S33 processed by D can be sent to the local storage 8, the VTR 7 or the on-air buffer 9 as an SDI standard signal. Incidentally, the input terminal IN1
When the video and audio signals input to .about.IN8 are output to the output terminals OUT1 to OUT3, since the video and audio signals are output from the respective devices according to the SDI standard, the output processor 43 and the audio combiner 44 are output. Performs no processing and outputs the input video and audio signals as they are to the output terminals OUT1 to OUT1.
Output to OUT3.

Similarly, the output processors 45 and 46 respectively output the video signal S31 or S32 image-processed by the image processing section 3C to the output terminal OUT4 or O4.
When outputting to the UT5, the video signal S31 or S3
2 is converted into an SDI standard video signal. As a result, the video signal S31 or S32 processed by the image processing unit 3C is converted into an SDI standard signal to a monitor 1 dedicated to preview.
3 or computer 2. Incidentally, the output processors 45 and 46 also have input terminals IN1 to IN1.
8 outputs the video and audio signals input to output terminal O
When outputting to the UT4 and OUT5, the video and audio signals are not processed at all and the output terminal OU is output as it is.
Output to T4 and OUT5.

Next, the image processing section 3C will be described with reference to FIG. As shown in FIG. 6, the image processing section 3C roughly includes a control circuit 50, a demultiplexer block 51, a switch block 52, a special effect block 53, and a mixer block 54. The control circuit 50 is a circuit that controls the entire image processing unit 3C, generates control signals S40, S41, S42, and S43 based on control commands received via the control bus 3E, and controls the control signals S40 and S41. , S42, S43
Are output to a demultiplexer block 51, a switch block 52, a special effect block 53, and a mixer block 54 to control the operation. As a result, the image processing unit 3C performs image processing on the video signal (S23 to S27) supplied from the matrix switch unit 3B. By the way, the image processing referred to here is an animation effect for applying a special effect to a source video signal or inserting a video signal having a special effect into a background video signal, or a foreground from a background video signal. This is a transition effect that switches video to a video signal.

The demultiplexer block 51 is connected to the SDI
This block extracts a video signal or a key signal from video and audio signals S23 to S27 sent in a standard signal format. This demultiplexer block 51
Are input video and audio signals S23 to S2
7 includes five demultiplexer circuits 51A to 51E for extracting signals. The demultiplexer circuit 51A is a circuit for extracting a key signal from a payload portion of each packet forming the video and audio signal S23, and performs extraction based on a synchronization signal and header information arranged at the head of the key signal. . The demultiplexer circuit 51B also controls the video and audio signals S
24 is a circuit for extracting a video signal from the payload portion of each packet forming the H.24, and performs extraction based on a synchronization signal and header information arranged at the head of the video signal. Similarly, the demultiplexer circuit 51C extracts the key signal from the video and audio signal S25, and the demultiplexer circuit 51D extracts the video and audio signal S26.
Video signal is extracted from the
Extracts a video signal from the video and audio signal S27.

The switch block 52 is a block for performing a process for a transition effect on the extracted key signal and video signal, and includes wipe signal generators 52A and 52B, key signal processing circuits 52C and 52D.
And video signal processing circuits 52E and 52F. The wipe signal generator 52A generates a wipe signal corresponding to the transition effect specified by the operator based on the control signal S41 from the control circuit 50, and applies the wipe signal to the key signal processing circuit 52C and the video signal processing circuit 52E. To send to. The key signal processing circuit 52C performs the demultiplexer circuit 5 based on the supplied wipe signal.
The key signal supplied from 1A is converted so as to correspond to the wipe signal (or a desired key signal corresponding to the wipe signal is newly generated based on the supplied wipe signal), and the resultant key is obtained. The signal is sent to a mixer block 54 described later. The video signal processing circuit 52E
Converts the video signal supplied from the demultiplexer circuit 51B based on the supplied wipe signal so as to correspond to the wipe signal, and sends the resulting video signal to a mixer block 54 described later.

Similarly, the wipe signal generator 52B generates a wipe signal corresponding to the transition effect specified by the operator based on the control signal S41 from the control circuit 50, and converts the wipe signal into a key signal processing circuit 52D. And to the video signal processing circuit 52F. The key signal processing circuit 52D converts the key signal supplied from the demultiplexer circuit 51C based on the supplied wipe signal so as to correspond to the wipe signal (or converts the key signal supplied to the wipe signal based on the supplied wipe signal). A corresponding desired key signal is newly generated), and the resulting key signal is sent to a special effect block 53 described later. The video signal processing circuit 52F converts the video signal supplied from the demultiplexer circuit 51D based on the supplied wipe signal so as to correspond to the wipe signal, and converts the resulting video signal into a special effect block described later. 53.

The special effect block 53 three-dimensionally converts the key signal output from the key signal processing circuit 52D and the video signal output from the video signal processing circuit 52F based on the control signal S42 supplied from the control circuit 50. This is a block for converting an image into a three-dimensional image, and comprises a three-dimensional address generation circuit 53A, frame memories 53B and 53C, and interpolation circuits 53D and 53E. The three-dimensional address generation circuit 53A generates a conversion address for performing three-dimensional image conversion specified by the operator based on the control signal S42, and stores the conversion address in the frame memory 53B,
53C and the interpolation circuits 53D and 53E.

The frame memory 53B sequentially stores the key signal supplied from the key signal processing circuit 52D in an internal memory area, and reads out the stored key signal based on the conversion address, thereby obtaining the key signal. On the other hand, three-dimensional image conversion is performed, and the key signal obtained as a result is sent to the interpolation circuit 53D. Similarly, the frame memory 53B sequentially stores the video signals supplied from the video signal processing circuit 52F in an internal memory area, and reads out the stored video signals based on the conversion address, thereby converting the video signals into the video signals. The image signal is subjected to three-dimensional image conversion, and the resulting video signal is sent to the interpolation circuit 53E.

The interpolation circuit 53D is a circuit for performing an interpolation process on the key signal that has been subjected to the three-dimensional conversion process. The interpolation circuit 53D spatially interpolates the pixels of the key signal based on the conversion address, and obtains the key signal obtained as a result. Is sent to a mixer block 54 described later. Similarly, the interpolation circuit 53E is a circuit that performs interpolation processing on a video signal that has been subjected to three-dimensional conversion processing.
The pixels of the video signal are spatially interpolated based on the conversion address, and the resulting video signal is sent to a mixer block 54 described later.

The mixer block 54 is a block for synthesizing a video signal in accordance with an instruction from the control signal S43.
It comprises two mixing circuits 54A and 54B. Based on the key signal output from the special effect block 53, the mix circuit 54A converts the video signal image-converted by the special effect block 53 and the video signal as the background video signal output from the demultiplexer circuit 51E. And the video signal S
31 is generated. Further, the mixing circuit 54B combines the video signal output from the switching block 52 and the video signal S31 output from the mixing circuit 54A based on the key signal output from the switching block 52, thereby obtaining a video signal. S32 is generated. The video signals S31 and S32 thus generated are
As described above, the signal is sent to the matrix switch unit 3B.

When performing a transition effect of simply switching between two images, the video signal output from the demultiplexer circuit 51E is input to the mix circuit 54B via the mix circuit 54A as a background video signal. At the same time, the video signal output from the video signal processing circuit 52E is input to the mixing circuit 54B as a foreground video signal, and the two video signals are synthesized based on the key signal output from the key signal processing circuit 52C. As a result, a video signal S32 that switches from the background video signal to the foreground video signal is generated.

When performing a transition effect involving image conversion such as a page turn, the video signal output from the demultiplexer circuit 51E is input to the mixer circuit 54A as a background video signal, and the video signal processing is performed. After the video signal output from the circuit 52F is converted as a foreground video signal through the special effect block 53, the mixing circuit 5
4A, and combines the two video signals via the special effect block 53 based on the key signal processed. As a result, a video signal S31 that switches from the background video signal to the foreground video signal is generated so as to turn the page.

When performing an animation effect such as a picture-in-picture, the video signal output from the demultiplexer circuit 51E is input to the mixer circuit 54A as a background video signal, and the video signal processing circuit The video signal output from the video signal 52F is converted as an insertion material through the special effect block 53 into an image and then input to the mixing circuit 54A. The two video signals are processed based on the key signal processed through the special effect block 53. And combine them. As a result, a picture-in-picture video signal S31 in which the insertion material has been inserted into the background video signal is generated.

Next, the audio processing unit 3D will be described with reference to FIG. As shown in FIG. 7, the audio processing unit 3D is roughly divided into a control circuit 55, an input signal processing block 5,
6. Auxiliary input signal processing block 57, mixer block 5.
8 and an output signal processing block 59. The control circuit 55 is a circuit that controls the entire audio processing unit 3D, and controls signals S45, S46, S47, and S48 based on a control command received via the control bus 3E.
And the control signals S45, S46, S47, S4
8 is output to an input signal processing block 56, an auxiliary input signal processing block 57, a mixer block 58, and an output signal processing block 59 to control the operation. As a result, in the audio processing unit 3D, the matrix switch unit 3
Audio processing is performed on the audio signal (S28 to S30) supplied from B. By the way, the audio processing here means the level adjustment and synthesis of the audio signal.

The input signal processing block 56 extracts an audio signal from the video and audio signals S28 to S30 sent in parallel with the signal format of the SDI standard, and processes the audio signal in a signal processing unit (DSP unit). This is a block to convert the audio signal into a DSP format audio signal and send it out. The input signal processing block 56 includes separators 56A to 56A as signal separation circuits.
56C. The separators 56A to 56C are circuits for extracting DSP format audio signals from the parallelized SDI standard video and audio signals S28 to S30, respectively. That is, the separators 56A to 56C extract the embedded audio signal from the input video and audio signals S28 to S30, serialize and send the serialized audio signal to the mixer block 58, respectively.

The auxiliary input signal processing block 57 is provided with an AES / EBU (Audio Engineering Soci
This block converts an audio signal of the format (ety / European Broadcasting Union) into an audio signal of the DSP format. The auxiliary input signal processing block 57 has sampling rate converters 57A to 57D for rate conversion and decoders 57E to 57H as format conversion circuits. In the sampling rate converters 57A to 57D, different sampling rates of the supplied AES / EBU format audio signal are converted into predetermined sampling rates in the audio processing unit 3D. The audio signals whose sampling rates have been converted are sent to decoders 57E to 57H. The decoders 57E to 57H are circuits for format-converting the audio signals, convert the input AES / EBU format audio signals into DSP format audio signals, and convert the resulting audio signals to the mixer block 58, respectively. Send out.

The mixer block 58 adjusts the level of the audio signal and synthesizes the signal. The mixer block 58 includes variable resistance circuits 58A to 58N, an addition circuit 580,
58P and a meter data generating circuit 5 for transmitting the signal levels of the variable resistance circuits 58A to 58N to the dedicated controller 5.
8Q. The audio signal supplied from the input signal processing block 56 and the audio signal supplied from the auxiliary input signal processing block 57 are separated into right and left components, respectively, and then are separated into variable resistance circuits 58A to 58A.
58G and the variable resistance circuits 58H to 58N. The variable resistance circuits 58A to 58G and 58H to 58N change their resistance values in conjunction with the operation of an audio off-adapter of the GUI displayed on the monitor 2B of the computer 2 or an audio off-ader provided in the dedicated controller 5. The level of the input audio signal is adjusted to a signal level designated by the operator.

The audio signals whose levels have been adjusted by the variable resistor circuits 58A to 58G are added to the adder circuit 58, respectively.
The signal is input to O, added here, and sent to an output signal processing block 59. Similarly, the variable resistance circuits 58H to 58H
The audio signals whose levels have been adjusted by 58N are input to adders 58P, respectively, where they are added to each other and sent to an output signal processing block 59. The meter data generating circuit 58Q converts the signal level at this time into data so as to directly control a digital meter on a panel of the dedicated controller 5 described later. The converted data is sent to the dedicated controller 5.

The output signal processing block 59 outputs the DS to be output.
This block converts a P format audio signal into an embedded audio signal obtained by parallelizing the signal format of the SDI standard. This output signal processing block 59
Is an embedded circuit 59A as a signal synthesis circuit,
Encoders 59B and 59 as format conversion circuits
C. The embedded circuit 59A is a circuit that performs signal conversion into a predetermined signal format so that the audio signal can be superimposed on the SDI standard video signal by the combiner 44 of the matrix switch unit 3B, and is supplied from the adders 580 and 58P. After the synthesized serial audio signal is synthesized, the signal is converted into a predetermined signal format, that is, a parallel embedded audio signal. The embedded audio signal S obtained by this processing
33 is sent to the combiner 44 of the matrix switch unit 3B as described above.

The encoder 59B converts the audio signal of the DSP format into an AES / EBU format audio signal. The encoder 59B converts the audio signal output from the adder circuit 580 into an AES / EBU signal.
The audio signal S17 is format-converted into an audio signal S17 in a format, and transmitted to a speaker 11 for audio confirmation (see FIG. 1). Similarly, the encoder 59C is a circuit for format-converting the audio signal of the DSP format into an audio signal of the AES / EBU format, and converts the audio signal output from the adder circuit 58P into the AES / EBU.
The audio signal is format-converted into an audio signal S18 in a format and transmitted to a speaker 12 for audio confirmation (see FIG. 1).

(4) Configuration of Local Storage Next, in this section, the local storage 8 will be described as data storage means connected to the editing processing device 3. As shown in FIG. 8, the local storage 8 has a data input / output block 60 as an input / output interface.
And a system control block 61 for controlling the operation of the entire local storage 8, a disk array block 62 for storing video data, and a disk array block 63 for storing audio data.

The data input / output block 60 has the structure of one input channel and two output channels. Based on the control signal S60 from the system control block 61, the video and audio signal S15 supplied from the editing processing device 3 are provided. The data read from the disk array blocks 62 and 63 are subjected to predetermined signal processing, and the data read from the disk array blocks 62 and 63 are subjected to predetermined signal processing and output as video and audio signals S13 and S14.

More specifically, first, the editing processor 3
The video and audio signal S15 supplied from is supplied to the encoder 60A. Encoder 60A is SDI
The video signal S61 and the audio signal S62 are extracted from the standard video and audio signal S15, the video signal S61 is output to the video compression circuit 60B, and the audio signal S62 is output to the audio compression circuit 60J. The video compression circuit 60B uses an MPEG compression rate of 1/10.
The video signal S61 is compressed according to the standard, and the compressed video data is stored in the buffer memory 60C. Similarly, the audio compression circuit 60J compresses the audio signal S62 using a predetermined audio compression method, and stores the compressed audio data in the buffer memory 60K. The video data and audio data stored in the buffer memories 60C and 60K are stored in the system control block 61.
Are sequentially read out under the control of, and are recorded in a disk array block 62 for video data and a disk array block 63 for audio, respectively.

On the other hand, the video data read from the disk array block 62 as the video data of the reproduction first channel is sequentially stored in the buffer memory 60F under the control of the system control block 61. Similarly, the audio data read from the disk array block 63 as the audio data of the reproduction first channel is sequentially stored in the buffer memory 60M under the control of the system control block 61. The first video decompression circuit 60E reads video data compressed according to the MPEG standard having a compression ratio of 1/10 from the buffer memory 60F, decompresses the video data, and then transmits the video data S63 to the first decoder 60D. Output. Similarly, the first audio decompression circuit 60L reads out the compressed audio data from the buffer memory 60M, decompresses the audio data, and
The audio data S64 is output to the first decoder 60D. The first decoder 60D superimposes the audio data S64 on the video data S63 based on the format of the SDI standard. As a result, the video data of the reproduced first channel read from the disk array block 62 and the audio data of the reproduced first channel read from the disk array block 63 can be transmitted as the SDI standard video and audio signal S13.

Similarly, video data read from the disk array block 62 as video data of the second reproduction channel is sequentially stored in the buffer memory 60I under the control of the system control block 61.
Also, audio data read from the disk array block 63 as audio data of the reproduction second channel is sequentially stored in the buffer memory 60P under the control of the system control block 61. The second video decompression circuit 60H reads video data compressed according to the MPEG standard having a compression rate of 1/10 from the buffer memory 60I, decompresses the video data, and then transmits the video data S65 to the second decoder 60G. Output.
Similarly, the second audio decompression circuit 60N reads the compressed audio data from the buffer memory 60P, decompresses the audio data, and outputs the audio data S66 to the second decoder 60G. The second decoder 60G converts the audio data S65 into the video data S65 based on the format of the SDI standard.
66 are superimposed. Thus, disk array block 6
2 and the reproduced second channel audio data read from the disk array block 63 can be transmitted as SDI standard video and audio signals S14.

The system control block 61 is a block for controlling the whole of the local storage 8, and includes a CPU 61A and a DMA controller (Direct Memory).
oryAccess controller) 61B, 61C and SCSI
Protocol controllers 61D and 61E and a control signal S
And 12 input interfaces 61F. C
The PU 61A constitutes a control circuit which is a central part of the system control block 61, and the editing processing device 3
From the DMA controller 61B, 61C and the SCSI protocol controllers 61D, 61E based on the control command indicated by the control signal S12. Control behavior.

As described above, when recording large-capacity data such as video data, a disk array device capable of operating a plurality of hard disks simultaneously in parallel is generally used. The disk array device used in this embodiment restores the data recorded on the failed hard disk even if one of the hard disks in the disk array fails due to the redundancy of the data to be recorded. (Also referred to as a reconstruction operation). Generally, a device having such a function is referred to as a RAID (Redandant Array of Ine
xpensive Disks).

FIG. 9 shows an example of the disk array.
The disk array block 62 includes a buffer memory 62A.
, A disk array controller 62B, a data multiplexer 62C, and a parity data operation circuit 62D.
And SCSI protocol controllers 62E, 62F,
62G, 62H, 62I and a hard disk (hereinafter referred to as H
DD) 62J, 62K, 62L, and 62M, and a parity data HDD 62N.

The disk array controller 62B controls each circuit of this block. Buffer memory 62A
Temporarily stores the data supplied from the SCSI protocol controller 61D. Data multiplexer 62
C selects the data supplied from the buffer memory 62A and distributes the data to each hard disk. SCSI protocol controllers 62E, 62F, 62G, 62H
Converts to the SCSI protocol.

HDD 62J, 62K, 62L, 62M
Stores the sorted general data. The parity data calculation circuit 62D receives the data distributed to the HDDs 62J, 62K, 62L, and 62M by the data multiplexer 62C, and calculates parity data PD from these data. HD for parity data
D62N stores the calculated parity data PD.

In the parity data operation circuit 62D,
Assuming that the data stored in the HDDs 62J, 62K, 62M, and 62N are D0, D1, D2, and D3, D0 + D1
When + D2 + D3 is an odd number, parity data PD = 0
When D0 + D1 + D2 + D3 is an even number,
The parity data PD = 1 is calculated.

For example, the disk array controller 62
B is the data D from the third HDD 62L due to the failure.
2 cannot be reproduced, the HDD 62
J, the data D1 recorded in the HDD 62K, the data D3 recorded in the HDD 62M, and the parity data PD recorded in the HDD 62N are reproduced. It is controlled so as to be supplied to the multiplexer 62C. The data multiplexer 62C performs a reconstruction operation,
Reconstructed data RD2 is generated. Then, the reconstructed data RD2 and the reproduced data D0, D1, D3
Generates and outputs the original data.

(5) Outline of Editing Apparatus Next, the editing apparatus will be described with reference to the schematic diagram of FIG. VT
In R71A to 71n, an embedded audio / video signal is reproduced. These VTRs 71A to 71n are
For example, it is composed of a digital VTR, but may be any device capable of reproducing embedded audio / video signals. The reproduced embedded audio / video signals are supplied from the digital VTRs 71A to 71n to the editing processing device 72. The editing device 72 corresponds to the above-described editing device 3 and has the same function, and has an A / V corresponding to the matrix switcher unit 3B.
It comprises a matrix circuit 72A, a video processor circuit 72B corresponding to the image processing unit 3C, an audio separator circuit 72C and an audio processor circuit 72D corresponding to the audio processing unit 3D, and an A / V combiner 72E corresponding to the audio combiner 44.

The A / V matrix circuit 72A determines whether the supplied embedded audio / video signal is a signal supplied to the video processor circuit 72B or a signal supplied to the audio separator circuit 72C. The signal determined to be a signal to be supplied to the video processor circuit 72B is supplied from the A / V matrix circuit 72A to the video processor circuit 72B, and the signal determined to be a signal supplied to the audio separator circuit 72C is an audio signal. It is supplied to the separator circuit 72C.

The video processor circuit 72B extracts a video signal from the supplied embedded audio / video signal. Since the audio signal is superimposed on the blanking interval of the video signal as shown in FIG. 11, the audio signal is erased by using the ordinary blanking circuit included in the demultiplexer block 51 described above. , Only the video signal can be extracted. The extracted video signal is processed by a video switcher, video effector, etc.,
A / V combiner 72 from video processor circuit 72B
E.

In the audio separator circuit 72C, an audio signal is extracted from the supplied embedded audio / video signal, and the extracted audio signal is supplied to an audio processor circuit 72D. In the audio processor circuit 72D, the supplied audio signal is processed by an audio mixer, an audio effector, and the like, and then supplied to the A / V combiner 72E. In the A / V combiner 72E, as shown in FIG. 11, an audio signal is superimposed on a video signal and output. The edited embedded audio / video signal is output from the editing device 72.

As described above, the embedded audio /
The video signal is transmitted such that the audio signal is superimposed on a blanking interval of the video signal. That is, in consideration of the fact that the video signal is used as a basis, the video signal and the audio signal are separated using the cross point circuit (A / V matrix circuit 72A) before being used for the respective processes. Select a signal having a video signal and an audio signal to be used. In the conventional editing device, the cross point for video and the cross point for audio are separately required, and the number of inputs is the same as the original number of inputs. Point circuits are greatly reduced.

Further, the video processing section usually has a blanking circuit, and the audio signal is erased in the video processing section, so that a dedicated separating circuit is not required. Therefore, it is understood that the separation circuit is necessary only for the selected audio signal. The audio separator circuit 72C corresponds to this. Usually, the number of voice inputs required at a certain editing time is smaller than the original number of inputs. Therefore, the video signal and the audio signal to which the present invention is applied are supplied to the respective processing units, and then the video signal and the audio signal are separated from the method of editing the video signal and the audio signal once, as in the conventional editing apparatus. It is considered that the method of separating signals from signals is that the number of separation circuits is small, so that the circuit scale can be reduced and cost can be reduced.

In this embodiment, the video processing unit and the audio processing unit are integrated. However, even if they are not integrated, the audio processing unit can take out only the audio signal after selecting the audio signal line. It can be easily imagined that the cost of the entire system can be reduced by doing so.

[0103]

According to the present invention, video processing and audio can be performed by using embedded audio / video signals as they are. Because the processing was integrated,
Since the number of connections and the number of input / output circuits can be reduced and the number of connections between devices can be reduced, the user can easily configure the system and reduce the cost of the entire system.

Further, according to the present invention, the circuit of the editing apparatus can be simplified, and the number of devices can be reduced, so that the failure of the system can be suppressed.

Further, according to the present invention, the embedded audio / video signal is used. However, when the conventional signal is used without using the embedded audio / video signal, the audio separator circuit 72C becomes unnecessary. Since the number of connection and connection devices is very small as compared with the conventional editing apparatus, the cost can be reduced even if the conventional signal is used.

[Brief description of the drawings]

FIG. 1 is an overall configuration of an example of an editing device to which the present invention is applied.

FIG. 2 is a schematic diagram of an internal configuration of an example of a computer according to the present invention.

FIG. 3 is an overall configuration of an example of an editing processing device to which the present invention is applied.

FIG. 4 is a configuration example of a system control unit according to the present invention;

FIG. 5 shows an example of a configuration of a matrix switcher section according to the present invention.

FIG. 6 is a configuration example of an image processing unit according to the present invention;

FIG. 7 shows an example of a configuration of an audio processing unit according to the present invention.

FIG. 8 is an example of a local storage according to the present invention.

FIG. 9 shows an example of the configuration of a disk array block according to the present invention.

FIG. 10 is a schematic diagram of an embodiment of the editing device of the present invention.

FIG. 11 is an example of an embedded audio / video signal.

FIG. 12 is a schematic diagram of a conventional editing device.

[Explanation of symbols]

71: VTR, 72: Edit processing device, 72A
..A / V matrix, 72B: video processor circuit, 72C: audio separator circuit, 72
D: audio processor circuit, 72E: A /
V combiner

Claims (2)

[Claims] An editing apparatus capable of supplying an audio mixed video signal in which an audio signal is superimposed in a blanking section of a video signal, and editing the video signal and the audio signal of the supplied audio mixed video signal. A cross-point means for inputting a plurality of audio-mixed video signals and selecting the plurality of audio-mixed video signals; extracting a video signal from the audio-mixed video signal selected by the cross-point means; Video processing means for performing processing; audio processing means for extracting an audio signal from the audio-mixed video signal selected by the cross-point means and performing processing on the audio signal; output from the video processing means; Combiner means for synthesizing the output of the means and generating an audio mixed video signal. Editing apparatus, characterized in that. 2. The editing apparatus according to claim 1, wherein said cross point means, said video processing means, said audio processing means, and said combiner means are included in one housing.